gdb/config/arm/tm-arm.h

   1 /* Definitions to target GDB to ARM targets.
   2    Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef TM_ARM_H
  23 #define TM_ARM_H
  24
  25 #include "regcache.h"
  26 #include "floatformat.h"
  27
  28 /* Forward declarations for prototypes.  */
  29 struct type;
  30 struct value;
  31
  32 /* Target byte order on ARM defaults to selectable, and defaults to
  33    little endian.  */
  34 #define TARGET_BYTE_ORDER_DEFAULT BFD_ENDIAN_LITTLE
  35
  36 /* IEEE format floating point.  */
  37 #define TARGET_DOUBLE_FORMAT  (target_byte_order == BFD_ENDIAN_BIG \
  38                                ? &floatformat_ieee_double_big    \
  39                                : &floatformat_ieee_double_littlebyte_bigword)
  40
  41 /* When reading symbols, we need to zap the low bit of the address,
  42    which may be set to 1 for Thumb functions.  */
  43
  44 #define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1)
  45
  46 /* Remove useless bits from addresses in a running program.  */
  47
  48 CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
  49
  50 #define ADDR_BITS_REMOVE(val)   (arm_addr_bits_remove (val))
  51
  52 /* Offset from address of function to start of its code.  Zero on most
  53    machines.  */
  54
  55 #define FUNCTION_START_OFFSET   0
  56
  57 /* Advance PC across any function entry prologue instructions to reach
  58    some "real" code.  */
  59
  60 extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
  61
  62 #define SKIP_PROLOGUE(pc)  (arm_skip_prologue (pc))
  63
  64 /* Immediately after a function call, return the saved pc.  Can't
  65    always go through the frames for this because on some machines the
  66    new frame is not set up until the new function executes some
  67    instructions.  */
  68
  69 #define SAVED_PC_AFTER_CALL(frame)  arm_saved_pc_after_call (frame)
  70 struct frame_info;
  71 extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
  72
  73 /* The following define instruction sequences that will cause ARM
  74    cpu's to take an undefined instruction trap.  These are used to
  75    signal a breakpoint to GDB.
  76
  77    The newer ARMv4T cpu's are capable of operating in ARM or Thumb
  78    modes.  A different instruction is required for each mode.  The ARM
  79    cpu's can also be big or little endian.  Thus four different
  80    instructions are needed to support all cases.
  81
  82    Note: ARMv4 defines several new instructions that will take the
  83    undefined instruction trap.  ARM7TDMI is nominally ARMv4T, but does
  84    not in fact add the new instructions.  The new undefined
  85    instructions in ARMv4 are all instructions that had no defined
  86    behaviour in earlier chips.  There is no guarantee that they will
  87    raise an exception, but may be treated as NOP's.  In practice, it
  88    may only safe to rely on instructions matching:
  89
  90    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  91    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  92    C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
  93
  94    Even this may only true if the condition predicate is true. The
  95    following use a condition predicate of ALWAYS so it is always TRUE.
  96
  97    There are other ways of forcing a breakpoint.  ARM Linux, RISC iX,
  98    and NetBSD will all use a software interrupt rather than an
  99    undefined instruction to force a trap.  This can be handled by
 100    redefining some or all of the following in a target dependent
 101    fashion.  */
 102
 103 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
 104 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
 105 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
 106 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
 107
 108 /* Stack grows downward.  */
 109
 110 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 111
 112 /* !!!! if we're using RDP, then we're inserting breakpoints and
 113    storing their handles instread of what was in memory.  It is nice
 114    that this is the same size as a handle - otherwise remote-rdp will
 115    have to change. */
 116
 117 /* BREAKPOINT_FROM_PC uses the program counter value to determine
 118    whether a 16- or 32-bit breakpoint should be used.  It returns a
 119    pointer to a string of bytes that encode a breakpoint instruction,
 120    stores the length of the string to *lenptr, and adjusts the pc (if
 121    necessary) to point to the actual memory location where the
 122    breakpoint should be inserted.  */
 123
 124 extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
 125 #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
 126
 127 /* Amount PC must be decremented by after a breakpoint.  This is often
 128    the number of bytes in BREAKPOINT but not always.  */
 129
 130 #define DECR_PC_AFTER_BREAK 0
 131
 132 /* Code to execute to print interesting information about the floating
 133    point processor (if any) or emulator.  No need to define if there
 134    is nothing to do. */
 135 extern void arm_float_info (void);
 136
 137 #define FLOAT_INFO      { arm_float_info (); }
 138
 139 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 140    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 141    real way to know how big a register is.  */
 142
 143 #define REGISTER_SIZE   4
 144
 145 /* Say how long FP registers are.  Used for documentation purposes and
 146    code readability in this header.  IEEE extended doubles are 80
 147    bits.  DWORD aligned they use 96 bits.  */
 148 #define FP_REGISTER_RAW_SIZE    12
 149
 150 /* GCC doesn't support long doubles (extended IEEE values).  The FP
 151    register virtual size is therefore 64 bits.  Used for documentation
 152    purposes and code readability in this header.  */
 153 #define FP_REGISTER_VIRTUAL_SIZE        8
 154
 155 /* Status registers are the same size as general purpose registers.
 156    Used for documentation purposes and code readability in this
 157    header.  */
 158 #define STATUS_REGISTER_SIZE    REGISTER_SIZE
 159
 160 /* Number of machine registers.  The only define actually required
 161    is NUM_REGS.  The other definitions are used for documentation
 162    purposes and code readability.  */
 163 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
 164    (and called PS for processor status) so the status bits can be cleared
 165    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
 166    in PS.  */
 167 #define NUM_FREGS       8       /* Number of floating point registers.  */
 168 #define NUM_SREGS       2       /* Number of status registers.  */
 169 #define NUM_GREGS       16      /* Number of general purpose registers.  */
 170 #define NUM_REGS        (NUM_GREGS + NUM_FREGS + NUM_SREGS)
 171
 172 /* An array of names of registers. */
 173 extern char **arm_register_names;
 174
 175 #define REGISTER_NAME(i) arm_register_names[i]
 176
 177 /* Register numbers of various important registers.  Note that some of
 178    these values are "real" register numbers, and correspond to the
 179    general registers of the machine, and some are "phony" register
 180    numbers which are too large to be actual register numbers as far as
 181    the user is concerned but do serve to get the desired values when
 182    passed to read_register.  */
 183
 184 #define A1_REGNUM 0             /* first integer-like argument */
 185 #define A4_REGNUM 3             /* last integer-like argument */
 186 #define AP_REGNUM 11
 187 #define FP_REGNUM 11            /* Contains address of executing stack frame */
 188 #define SP_REGNUM 13            /* Contains address of top of stack */
 189 #define LR_REGNUM 14            /* address to return to from a function call */
 190 #define PC_REGNUM 15            /* Contains program counter */
 191 #define F0_REGNUM 16            /* first floating point register */
 192 #define F3_REGNUM 19            /* last floating point argument register */
 193 #define F7_REGNUM 23            /* last floating point register */
 194 #define FPS_REGNUM 24           /* floating point status register */
 195 #define PS_REGNUM 25            /* Contains processor status */
 196
 197 #define THUMB_FP_REGNUM 7       /* R7 is frame register on Thumb */
 198
 199 #define ARM_NUM_ARG_REGS        4
 200 #define ARM_LAST_ARG_REGNUM     A4_REGNUM
 201 #define ARM_NUM_FP_ARG_REGS     4
 202 #define ARM_LAST_FP_ARG_REGNUM  F3_REGNUM
 203
 204 /* Instruction condition field values.  */
 205 #define INST_EQ         0x0
 206 #define INST_NE         0x1
 207 #define INST_CS         0x2
 208 #define INST_CC         0x3
 209 #define INST_MI         0x4
 210 #define INST_PL         0x5
 211 #define INST_VS         0x6
 212 #define INST_VC         0x7
 213 #define INST_HI         0x8
 214 #define INST_LS         0x9
 215 #define INST_GE         0xa
 216 #define INST_LT         0xb
 217 #define INST_GT         0xc
 218 #define INST_LE         0xd
 219 #define INST_AL         0xe
 220 #define INST_NV         0xf
 221
 222 #define FLAG_N          0x80000000
 223 #define FLAG_Z          0x40000000
 224 #define FLAG_C          0x20000000
 225 #define FLAG_V          0x10000000
 226
 227
 228
 229 /* Total amount of space needed to store our copies of the machine's
 230    register state, the array `registers'.  */
 231
 232 #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
 233                         (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
 234                         (NUM_SREGS * STATUS_REGISTER_SIZE))
 235
 236 /* Index within `registers' of the first byte of the space for
 237    register N.  */
 238
 239 #define REGISTER_BYTE(N) \
 240      ((N) < F0_REGNUM \
 241       ? (N) * REGISTER_SIZE \
 242       : ((N) < PS_REGNUM \
 243          ? (NUM_GREGS * REGISTER_SIZE + \
 244             ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
 245          : (NUM_GREGS * REGISTER_SIZE + \
 246             NUM_FREGS * FP_REGISTER_RAW_SIZE + \
 247             ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
 248
 249 /* Number of bytes of storage in the actual machine representation for
 250    register N.  All registers are 4 bytes, except fp0 - fp7, which are
 251    12 bytes in length.  */
 252 #define REGISTER_RAW_SIZE(N) \
 253      ((N) < F0_REGNUM ? REGISTER_SIZE : \
 254       (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
 255
 256 /* Number of bytes of storage in a program's representation
 257    for register N.  */
 258 #define REGISTER_VIRTUAL_SIZE(N) \
 259         ((N) < F0_REGNUM ? REGISTER_SIZE : \
 260          (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
 261
 262 /* Largest value REGISTER_RAW_SIZE can have.  */
 263
 264 #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
 265
 266 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 267 #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
 268
 269 /* Return the GDB type object for the "standard" data type of data in
 270    register N.  */
 271
 272 extern struct type *arm_register_type (int regnum);
 273 #define REGISTER_VIRTUAL_TYPE(N) arm_register_type (N)
 274
 275 /* The system C compiler uses a similar structure return convention to gcc */
 276 extern use_struct_convention_fn arm_use_struct_convention;
 277 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 278      arm_use_struct_convention (gcc_p, type)
 279
 280 /* Store the address of the place in which to copy the structure the
 281    subroutine will return.  This is called from call_function. */
 282
 283 #define STORE_STRUCT_RETURN(ADDR, SP) \
 284      write_register (A1_REGNUM, (ADDR))
 285
 286 /* Extract from an array REGBUF containing the (raw) register state a
 287    function return value of type TYPE, and copy that, in virtual
 288    format, into VALBUF.  */
 289
 290 extern void arm_extract_return_value (struct type *, char[], char *);
 291 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 292      arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
 293
 294 /* Write into appropriate registers a function return value of type
 295    TYPE, given in virtual format.  */
 296
 297 extern void convert_to_extended (void *dbl, void *ptr);
 298 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 299   if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) {                              \
 300     char _buf[MAX_REGISTER_RAW_SIZE];                                   \
 301     convert_to_extended (VALBUF, _buf);                                         \
 302     write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
 303   } else                                                                \
 304     write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
 305
 306 /* Extract from an array REGBUF containing the (raw) register state
 307    the address in which a function should return its structure value,
 308    as a CORE_ADDR (or an expression that can be used as one).  */
 309
 310 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 311   (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
 312
 313 /* Specify that for the native compiler variables for a particular
 314    lexical context are listed after the beginning LBRAC instead of
 315    before in the executables list of symbols.  */
 316 #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
 317 \f
 318
 319 /* Define other aspects of the stack frame.  We keep the offsets of
 320    all saved registers, 'cause we need 'em a lot!  We also keep the
 321    current size of the stack frame, and the offset of the frame
 322    pointer from the stack pointer (for frameless functions, and when
 323    we're still in the prologue of a function with a frame) */
 324
 325 #define EXTRA_FRAME_INFO        \
 326   struct frame_saved_regs fsr;  \
 327   int framesize;                \
 328   int frameoffset;              \
 329   int framereg;
 330
 331 extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi);
 332 #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
 333         arm_init_extra_frame_info ((fromleaf), (fi))
 334
 335 /* Return the frame address.  On ARM, it is R11; on Thumb it is R7.  */
 336 CORE_ADDR arm_target_read_fp (void);
 337 #define TARGET_READ_FP() arm_target_read_fp ()
 338
 339 /* Describe the pointer in each stack frame to the previous stack
 340    frame (its caller).  */
 341
 342 /* FRAME_CHAIN takes a frame's nominal address and produces the
 343    frame's chain-pointer.
 344
 345    However, if FRAME_CHAIN_VALID returns zero,
 346    it means the given frame is the outermost one and has no caller.  */
 347
 348 #define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe)
 349 extern CORE_ADDR arm_frame_chain (struct frame_info *);
 350
 351 extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *);
 352 #define FRAME_CHAIN_VALID(chain, thisframe) \
 353      arm_frame_chain_valid (chain, thisframe)
 354
 355 /* Define other aspects of the stack frame.  */
 356
 357 /* A macro that tells us whether the function invocation represented
 358    by FI does not have a frame on the stack associated with it.  If it
 359    does not, FRAMELESS is set to 1, else 0.
 360
 361    Sometimes we have functions that do a little setup (like saving the
 362    vN registers with the stmdb instruction, but DO NOT set up a frame.
 363    The symbol table will report this as a prologue.  However, it is
 364    important not to try to parse these partial frames as frames, or we
 365    will get really confused.
 366
 367    So I will demand 3 instructions between the start & end of the
 368    prologue before I call it a real prologue, i.e. at least
 369          mov ip, sp,
 370          stmdb sp!, {}
 371          sub sp, ip, #4. */
 372
 373 extern int arm_frameless_function_invocation (struct frame_info *fi);
 374 #define FRAMELESS_FUNCTION_INVOCATION(FI) \
 375 (arm_frameless_function_invocation (FI))
 376
 377 /* Saved Pc.  */
 378
 379 #define FRAME_SAVED_PC(FRAME)   arm_frame_saved_pc (FRAME)
 380 extern CORE_ADDR arm_frame_saved_pc (struct frame_info *);
 381
 382 #define FRAME_ARGS_ADDRESS(fi) (fi->frame)
 383
 384 #define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
 385
 386 /* Return number of args passed to a frame.
 387    Can return -1, meaning no way to tell.  */
 388
 389 #define FRAME_NUM_ARGS(fi) (-1)
 390
 391 /* Return number of bytes at start of arglist that are not really args. */
 392
 393 #define FRAME_ARGS_SKIP 0
 394
 395 /* Put here the code to store, into a struct frame_saved_regs, the
 396    addresses of the saved registers of frame described by FRAME_INFO.
 397    This includes special registers such as pc and fp saved in special
 398    ways in the stack frame.  sp is even more special: the address we
 399    return for it IS the sp for the next frame.  */
 400
 401 struct frame_saved_regs;
 402 struct frame_info;
 403 void arm_frame_find_saved_regs (struct frame_info * fi,
 404                                 struct frame_saved_regs * fsr);
 405
 406 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
 407         arm_frame_find_saved_regs (frame_info, &(frame_saved_regs));
 408
 409 /* Things needed for making the inferior call functions.  */
 410
 411 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 412      sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr))
 413 extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int,
 414                                      CORE_ADDR);
 415
 416 /* Push an empty stack frame, to record the current PC, etc.  */
 417
 418 void arm_push_dummy_frame (void);
 419
 420 #define PUSH_DUMMY_FRAME arm_push_dummy_frame ()
 421
 422 /* Discard from the stack the innermost frame, restoring all registers.  */
 423
 424 void arm_pop_frame (void);
 425
 426 #define POP_FRAME arm_pop_frame ()
 427
 428 /* This sequence of words is the instructions
 429
 430    mov  lr,pc
 431    mov  pc,r4
 432    illegal
 433
 434    Note this is 12 bytes.  */
 435
 436 #define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe}
 437 #define CALL_DUMMY_START_OFFSET  0      /* Start execution at beginning of dummy */
 438
 439 #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
 440 extern int arm_call_dummy_breakpoint_offset (void);
 441
 442 /* Insert the specified number of args and function address into a
 443    call sequence of the above form stored at DUMMYNAME.  */
 444
 445 #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
 446    arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
 447
 448 void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
 449                          int nargs, struct value ** args,
 450                          struct type * type, int gcc_p);
 451
 452 /* Most ARMs don't have single stepping capability, so provide a
 453    single-stepping mechanism by default */
 454 #undef SOFTWARE_SINGLE_STEP_P
 455 #define SOFTWARE_SINGLE_STEP_P() 1
 456
 457 #define SOFTWARE_SINGLE_STEP(sig,bpt) arm_software_single_step((sig), (bpt))
 458 void arm_software_single_step (int, int);
 459
 460 CORE_ADDR arm_get_next_pc (CORE_ADDR pc);
 461
 462 /* Macros for setting and testing a bit in a minimal symbol that marks
 463    it as Thumb function.  The MSB of the minimal symbol's "info" field
 464    is used for this purpose. This field is already being used to store
 465    the symbol size, so the assumption is that the symbol size cannot
 466    exceed 2^31.
 467
 468    COFF_MAKE_MSYMBOL_SPECIAL
 469    ELF_MAKE_MSYMBOL_SPECIAL
 470
 471    These macros test whether the COFF or ELF symbol corresponds to a
 472    thumb function, and set a "special" bit in a minimal symbol to
 473    indicate that it does.
 474
 475    MSYMBOL_SET_SPECIAL  Actually sets the "special" bit.
 476    MSYMBOL_IS_SPECIAL   Tests the "special" bit in a minimal symbol.
 477    MSYMBOL_SIZE         Returns the size of the minimal symbol,
 478                         i.e. the "info" field with the "special" bit
 479                         masked out
 480    */
 481
 482 extern int coff_sym_is_thumb (int val);
 483
 484 #define MSYMBOL_SET_SPECIAL(msym) \
 485         MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000)
 486 #define MSYMBOL_IS_SPECIAL(msym) \
 487   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 488 #define MSYMBOL_SIZE(msym) \
 489   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 490
 491 /* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */
 492 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 493         { if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \
 494                 MSYMBOL_SET_SPECIAL(msym); }
 495
 496 #define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \
 497  { if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); }
 498
 499 /* The first 0x20 bytes are the trap vectors.  */
 500 #define LOWEST_PC       0x20
 501
 502 /* Function to determine whether MEMADDR is in a Thumb function.  */
 503 extern int arm_pc_is_thumb (bfd_vma memaddr);
 504
 505 /* Function to determine whether MEMADDR is in a call dummy called from
 506    a Thumb function.  */
 507 extern int arm_pc_is_thumb_dummy (bfd_vma memaddr);
 508
 509 #endif /* TM_ARM_H */