gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7 This file is part of GDB.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef TM_MIPS_H
  24 #define TM_MIPS_H 1
  25
  26 #ifdef __STDC__
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31 #endif
  32
  33 #include <bfd.h>
  34 #include "coff/sym.h"           /* Needed for PDR below.  */
  35 #include "coff/symconst.h"
  36
  37 #if !defined (TARGET_BYTE_ORDER)
  38 #define TARGET_BYTE_ORDER LITTLE_ENDIAN
  39 #endif
  40
  41 #if !defined (GDB_TARGET_IS_MIPS64)
  42 #define GDB_TARGET_IS_MIPS64 0
  43 #endif
  44
  45 #if !defined (TARGET_MONITOR_PROMPT)
  46 #define TARGET_MONITOR_PROMPT "<IDT>"
  47 #endif
  48
  49 /* Floating point is IEEE compliant */
  50 #define IEEE_FLOAT
  51
  52 /* Some MIPS boards are provided both with and without a floating
  53    point coprocessor.  The MIPS R4650 chip has only single precision
  54    floating point.  We provide a user settable variable to tell gdb
  55    what type of floating point to use.  */
  56
  57 enum mips_fpu_type
  58 {
  59   MIPS_FPU_DOUBLE,      /* Full double precision floating point.  */
  60   MIPS_FPU_SINGLE,      /* Single precision floating point (R4650).  */
  61   MIPS_FPU_NONE         /* No floating point.  */
  62 };
  63
  64 extern enum mips_fpu_type mips_fpu;
  65
  66 /* The name of the usual type of MIPS processor that is in the target
  67    system.  */
  68
  69 #define DEFAULT_MIPS_TYPE "generic"
  70
  71 /* Offset from address of function to start of its code.
  72    Zero on most machines.  */
  73
  74 #define FUNCTION_START_OFFSET 0
  75
  76 /* Advance PC across any function entry prologue instructions
  77    to reach some "real" code.  */
  78
  79 #define SKIP_PROLOGUE(pc)       pc = mips_skip_prologue (pc, 0)
  80 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
  81
  82 /* Return non-zero if PC points to an instruction which will cause a step
  83    to execute both the instruction at PC and an instruction at PC+4.  */
  84 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  85 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
  86
  87 /* Immediately after a function call, return the saved pc.
  88    Can't always go through the frames for this because on some machines
  89    the new frame is not set up until the new function executes
  90    some instructions.  */
  91
  92 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
  93
  94 /* Are we currently handling a signal */
  95
  96 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
  97 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  98
  99 /* Stack grows downward.  */
 100
 101 #define INNER_THAN <
 102
 103 #define BIG_ENDIAN 4321
 104 #if TARGET_BYTE_ORDER == BIG_ENDIAN
 105 #define BREAKPOINT {0, 0x5, 0, 0xd}
 106 #else
 107 #define BREAKPOINT {0xd, 0, 0x5, 0}
 108 #endif
 109
 110 /* Amount PC must be decremented by after a breakpoint.
 111    This is often the number of bytes in BREAKPOINT
 112    but not always.  */
 113
 114 #define DECR_PC_AFTER_BREAK 0
 115
 116 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
 117
 118 #define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
 119
 120 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 121    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 122    real way to know how big a register is.  */
 123
 124 #define REGISTER_SIZE 4
 125
 126 /* The size of a register.  This is predefined in tm-mips64.h.  We
 127    can't use REGISTER_SIZE because that is used for various other
 128    things.  */
 129
 130 #ifndef MIPS_REGSIZE
 131 #define MIPS_REGSIZE 4
 132 #endif
 133
 134 /* Number of machine registers */
 135
 136 #define NUM_REGS 90
 137
 138 /* Initializer for an array of names of registers.
 139    There should be NUM_REGS strings in this initializer.  */
 140
 141 #define REGISTER_NAMES  \
 142     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 143         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 144         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 145         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 146         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 147         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 148         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 149         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 150         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 151         "fsr",  "fir",  "fp",   "", \
 152         "",     "",     "",     "",     "",     "",     "",     "", \
 153         "",     "",     "",     "",     "",     "",     "",     "", \
 154     }
 155
 156 /* Register numbers of various important registers.
 157    Note that some of these values are "real" register numbers,
 158    and correspond to the general registers of the machine,
 159    and some are "phony" register numbers which are too large
 160    to be actual register numbers as far as the user is concerned
 161    but do serve to get the desired values when passed to read_register.  */
 162
 163 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 164 #define V0_REGNUM 2             /* Function integer return value */
 165 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 166 #if MIPS_EABI
 167   #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 168   #define MIPS_NUM_ARG_REGS 8
 169 #else
 170   #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 171   #define MIPS_NUM_ARG_REGS 4
 172 #endif
 173 #define SP_REGNUM 29            /* Contains address of top of stack */
 174 #define RA_REGNUM 31            /* Contains return address value */
 175 #define PS_REGNUM 32            /* Contains processor status */
 176 #define HI_REGNUM 34            /* Multiple/divide temp */
 177 #define LO_REGNUM 33            /* ... */
 178 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 179 #define CAUSE_REGNUM 36         /* describes last exception */
 180 #define PC_REGNUM 37            /* Contains program counter */
 181 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 182 #define FCRCS_REGNUM 70         /* FP control/status */
 183 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 184 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 185 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 186 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 187 #define PRID_REGNUM 89          /* Processor ID */
 188 #define LAST_EMBED_REGNUM 89    /* Last one */
 189
 190 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 191    of register dumps. */
 192
 193 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 194 extern void mips_do_registers_info PARAMS ((int, int));
 195
 196 /* Total amount of space needed to store our copies of the machine's
 197    register state, the array `registers'.  */
 198
 199 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 200
 201 /* Index within `registers' of the first byte of the space for
 202    register N.  */
 203
 204 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 205
 206 /* Number of bytes of storage in the actual machine representation
 207    for register N.  On mips, all regs are the same size.  */
 208
 209 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
 210
 211 /* Number of bytes of storage in the program's representation
 212    for register N.  On mips, all regs are the same size.  */
 213
 214 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
 215
 216 /* Largest value REGISTER_RAW_SIZE can have.  */
 217
 218 #define MAX_REGISTER_RAW_SIZE 8
 219
 220 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 221
 222 #define MAX_REGISTER_VIRTUAL_SIZE 8
 223
 224 /* Return the GDB type object for the "standard" data type
 225    of data in register N.  */
 226
 227 #ifndef REGISTER_VIRTUAL_TYPE
 228 #define REGISTER_VIRTUAL_TYPE(N) \
 229         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32)  \
 230          ? builtin_type_float : builtin_type_int)
 231 #endif
 232
 233 #if HOST_BYTE_ORDER == BIG_ENDIAN
 234 /* All mips targets store doubles in a register pair with the least
 235    significant register in the lower numbered register.
 236    If the host is big endian, double register values need conversion between
 237    memory and register formats.  */
 238
 239 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 240   do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 &&                 \
 241           TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
 242         char __temp[4];                                                 \
 243         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 244         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 245         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 246
 247 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 248   do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 &&                 \
 249           TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
 250         char __temp[4];                                                 \
 251         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 252         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 253         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 254 #endif
 255
 256 /* Store the address of the place in which to copy the structure the
 257    subroutine will return.  Handled by mips_push_arguments.  */
 258
 259 #define STORE_STRUCT_RETURN(addr, sp)   /**/
 260
 261 /* Extract from an array REGBUF containing the (raw) register state
 262    a function return value of type TYPE, and copy that, in virtual format,
 263    into VALBUF.  XXX floats */
 264
 265 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 266   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 267 extern void
 268 mips_extract_return_value PARAMS ((struct type *, char [], char *));
 269
 270 /* Write into appropriate registers a function return value
 271    of type TYPE, given in virtual format.  */
 272
 273 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 274   mips_store_return_value(TYPE, VALBUF)
 275 extern void mips_store_return_value PARAMS ((struct type *, char *));
 276
 277 /* Extract from an array REGBUF containing the (raw) register state
 278    the address in which a function should return its structure value,
 279    as a CORE_ADDR (or an expression that can be used as one).  */
 280 /* The address is passed in a0 upon entry to the function, but when
 281    the function exits, the compiler has copied the value to v0.  This
 282    convention is specified by the System V ABI, so I think we can rely
 283    on it.  */
 284
 285 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 286   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 287                     REGISTER_RAW_SIZE (V0_REGNUM)))
 288
 289 /* Structures are returned by ref in extra arg0 */
 290 #define USE_STRUCT_CONVENTION(gcc_p, type)      1
 291
 292 \f
 293 /* Describe the pointer in each stack frame to the previous stack frame
 294    (its caller).  */
 295
 296 /* FRAME_CHAIN takes a frame's nominal address
 297    and produces the frame's chain-pointer. */
 298
 299 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 300 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 301
 302 /* Define other aspects of the stack frame.  */
 303
 304
 305 /* A macro that tells us whether the function invocation represented
 306    by FI does not have a frame on the stack associated with it.  If it
 307    does not, FRAMELESS is set to 1, else 0.  */
 308 /* We handle this differently for mips, and maybe we should not */
 309
 310 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}
 311
 312 /* Saved Pc.  */
 313
 314 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 315 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 316
 317 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 318
 319 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 320
 321 /* Return number of args passed to a frame.
 322    Can return -1, meaning no way to tell.  */
 323
 324 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
 325 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 326
 327 /* Return number of bytes at start of arglist that are not really args.  */
 328
 329 #define FRAME_ARGS_SKIP 0
 330
 331 /* Put here the code to store, into a struct frame_saved_regs,
 332    the addresses of the saved registers of frame described by FRAME_INFO.
 333    This includes special registers such as pc and fp saved in special
 334    ways in the stack frame.  sp is even more special:
 335    the address we return for it IS the sp for the next frame.  */
 336
 337 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
 338   do { \
 339     if ((frame_info)->saved_regs == NULL) \
 340       mips_find_saved_regs (frame_info); \
 341     (frame_saved_regs) = *(frame_info)->saved_regs; \
 342     (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
 343   } while (0)
 344 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 345
 346 \f
 347 /* Things needed for making the inferior call functions.  */
 348
 349 /* Stack must be aligned on 32-bit boundaries when synthesizing
 350    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 351    handle it. */
 352
 353 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 354     sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))
 355 extern CORE_ADDR
 356 mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 357
 358 /* Push an empty stack frame, to record the current PC, etc.  */
 359
 360 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 361 extern void mips_push_dummy_frame PARAMS ((void));
 362
 363 /* Discard from the stack the innermost frame, restoring all registers.  */
 364
 365 #define POP_FRAME               mips_pop_frame()
 366 extern void mips_pop_frame PARAMS ((void));
 367
 368 #define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
 369 #ifndef OP_LDFPR
 370 #define OP_LDFPR 061    /* lwc1 */
 371 #endif
 372 #ifndef OP_LDGPR
 373 #define OP_LDGPR 043    /* lw */
 374 #endif
 375 #define CALL_DUMMY_SIZE (16*4)
 376 #define Dest_Reg 2
 377 #define CALL_DUMMY {\
 378  MK_OP(0,RA_REGNUM,0,8),        /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
 379  0,                             /* nop    #  ... to stop raw backtrace*/\
 380  0x27bd0000,                    /* addu sp,?0 # Pseudo prologue */\
 381 /* Start here; reload FP regs, then GP regs: */\
 382  MK_OP(OP_LDFPR,SP_REGNUM,12,0             ), /* l[wd]c1 $f12,0(sp) */\
 383  MK_OP(OP_LDFPR,SP_REGNUM,13,  MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
 384  MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
 385  MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
 386  MK_OP(OP_LDGPR,SP_REGNUM, 4,0             ), /* l[wd] $r4,0(sp) */\
 387  MK_OP(OP_LDGPR,SP_REGNUM, 5,  MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
 388  MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
 389  MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 390  (017<<26)| (Dest_Reg << 16),   /* lui $r31,<target upper 16 bits>*/\
 391  MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
 392  (Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\
 393  MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 394  0x5000d,                       /* bpt */\
 395 }
 396
 397 #define CALL_DUMMY_START_OFFSET 12
 398
 399 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
 400
 401 /* Insert the specified number of args and function address
 402    into a call sequence of the above form stored at DUMMYNAME.  */
 403
 404 /* For big endian mips machines we need to switch the order of the
 405    words with a floating-point value (it was already coerced to a double
 406    by mips_push_arguments).  */
 407 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 408   do                                                                    \
 409     {                                                                   \
 410       store_unsigned_integer                                            \
 411         (dummyname + 11 * 4, 4,                                         \
 412          (extract_unsigned_integer (dummyname + 11 * 4, 4)              \
 413           | (((fun) >> 16) & 0xffff)));                                 \
 414       store_unsigned_integer                                            \
 415         (dummyname + 12 * 4, 4,                                         \
 416          (extract_unsigned_integer (dummyname + 12 * 4, 4)              \
 417           | ((fun) & 0xffff)));                                         \
 418       if (mips_fpu == MIPS_FPU_NONE)                                    \
 419         {                                                               \
 420           store_unsigned_integer (dummyname + 3 * 4, 4,                 \
 421                                   (ULONGEST) 0);                        \
 422           store_unsigned_integer (dummyname + 4 * 4, 4,                 \
 423                                   (ULONGEST) 0);                        \
 424           store_unsigned_integer (dummyname + 5 * 4, 4,                 \
 425                                   (ULONGEST) 0);                        \
 426           store_unsigned_integer (dummyname + 6 * 4, 4,                 \
 427                                   (ULONGEST) 0);                        \
 428         }                                                               \
 429       else if (mips_fpu == MIPS_FPU_SINGLE)                             \
 430         {                                                               \
 431           /* This isn't right.  mips_push_arguments will call           \
 432              value_arg_coerce, which will convert all float arguments   \
 433              to doubles.  If the function prototype is float, though,   \
 434              it will be expecting a float argument in a float           \
 435              register.  */                                              \
 436           store_unsigned_integer (dummyname + 4 * 4, 4,                 \
 437                                   (ULONGEST) 0);                        \
 438           store_unsigned_integer (dummyname + 6 * 4, 4,                 \
 439                                   (ULONGEST) 0);                        \
 440         }                                                               \
 441       else if (TARGET_BYTE_ORDER == BIG_ENDIAN                          \
 442                && ! GDB_TARGET_IS_MIPS64)                               \
 443         {                                                               \
 444           if (nargs > 0                                                 \
 445               && TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT)     \
 446             {                                                           \
 447               if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8)               \
 448                 error ("floating point value too large to pass to function");\
 449               store_unsigned_integer                                    \
 450                 (dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
 451               store_unsigned_integer                                    \
 452                 (dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
 453             }                                                           \
 454           if (nargs > 1                                                 \
 455               && TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT)     \
 456             {                                                           \
 457               if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8)               \
 458                 error ("floating point value too large to pass to function");\
 459               store_unsigned_integer                                    \
 460                 (dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
 461               store_unsigned_integer                                    \
 462                 (dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
 463             }                                                           \
 464         }                                                               \
 465     }                                                                   \
 466   while (0)
 467
 468 /* There's a mess in stack frame creation.  See comments in blockframe.c
 469    near reference to INIT_FRAME_PC_FIRST.  */
 470
 471 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
 472
 473 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 474   (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
 475               (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
 476
 477 /* Special symbol found in blocks associated with routines.  We can hang
 478    mips_extra_func_info_t's off of this.  */
 479
 480 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 481 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 482
 483 /* Specific information about a procedure.
 484    This overlays the MIPS's PDR records,
 485    mipsread.c (ab)uses this to save memory */
 486
 487 typedef struct mips_extra_func_info {
 488         long    numargs;        /* number of args to procedure (was iopt) */
 489         bfd_vma high_addr;      /* upper address bound */
 490         PDR     pdr;            /* Procedure descriptor record */
 491 } *mips_extra_func_info_t;
 492
 493 #define EXTRA_FRAME_INFO \
 494   mips_extra_func_info_t proc_desc; \
 495   int num_args;\
 496   struct frame_saved_regs *saved_regs;
 497
 498 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
 499 extern void init_extra_frame_info PARAMS ((struct frame_info *));
 500
 501 #define PRINT_EXTRA_FRAME_INFO(fi) \
 502   { \
 503     if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
 504       printf_filtered (" frame pointer is at %s+%d\n", \
 505                        reg_names[fi->proc_desc->pdr.framereg], \
 506                                  fi->proc_desc->pdr.frameoffset); \
 507   }
 508
 509 /* It takes two values to specify a frame on the MIPS.
 510
 511    In fact, the *PC* is the primary value that sets up a frame.  The
 512    PC is looked up to see what function it's in; symbol information
 513    from that function tells us which register is the frame pointer
 514    base, and what offset from there is the "virtual frame pointer".
 515    (This is usually an offset from SP.)  On most non-MIPS machines,
 516    the primary value is the SP, and the PC, if needed, disambiguates
 517    multiple functions with the same SP.  But on the MIPS we can't do
 518    that since the PC is not stored in the same part of the frame every
 519    time.  This does not seem to be a very clever way to set up frames,
 520    but there is nothing we can do about that).  */
 521
 522 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 523 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 524
 525 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 526
 527 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 528
 529 /* Convert a ecoff register number to a gdb REGNUM */
 530
 531 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 532
 533 /* If the current gcc for for this target does not produce correct debugging
 534    information for float parameters, both prototyped and unprototyped, then
 535    define this macro.  This forces gdb to  always assume that floats are
 536    passed as doubles and then converted in the callee.
 537
 538    For the mips chip, it appears that the debug info marks the parameters as
 539    floats regardless of whether the function is prototyped, but the actual
 540    values are passed as doubles for the non-prototyped case and floats for
 541    the prototyped case.  Thus we choose to make the non-prototyped case work
 542    for C and break the prototyped case, since the non-prototyped case is
 543    probably much more common.  (FIXME). */
 544
 545 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 546
 547 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 548 extern CORE_ADDR sigtramp_address, sigtramp_end;
 549 extern void fixup_sigtramp PARAMS ((void));
 550
 551 /* Defined in mips-tdep.c and used in remote-mips.c */
 552 extern char *mips_read_processor_type PARAMS ((void));
 553
 554 #ifndef TARGET_MIPS
 555 #define TARGET_MIPS
 556 #endif
 557
 558 #endif  /* TM_MIPS_H */