gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2
   3    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
   4    1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   5
   6    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   7    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   8
   9    This file is part of GDB.
  10
  11    This program is free software; you can redistribute it and/or modify
  12    it under the terms of the GNU General Public License as published by
  13    the Free Software Foundation; either version 2 of the License, or
  14    (at your option) any later version.
  15
  16    This program is distributed in the hope that it will be useful,
  17    but WITHOUT ANY WARRANTY; without even the implied warranty of
  18    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19    GNU General Public License for more details.
  20
  21    You should have received a copy of the GNU General Public License
  22    along with this program; if not, write to the Free Software
  23    Foundation, Inc., 59 Temple Place - Suite 330,
  24    Boston, MA 02111-1307, USA.  */
  25
  26 #ifndef TM_MIPS_H
  27 #define TM_MIPS_H 1
  28
  29 #define GDB_MULTI_ARCH 1
  30
  31 #include "regcache.h"
  32
  33 struct frame_info;
  34 struct symbol;
  35 struct type;
  36 struct value;
  37
  38 #include <bfd.h>
  39 #include "coff/sym.h"           /* Needed for PDR below.  */
  40 #include "coff/symconst.h"
  41
  42 /* PC should be masked to remove possible MIPS16 flag */
  43 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  44 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  45 #endif
  46 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  47 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  48 #endif
  49
  50 /* Return non-zero if PC points to an instruction which will cause a step
  51    to execute both the instruction at PC and an instruction at PC+4.  */
  52 extern int mips_step_skips_delay (CORE_ADDR);
  53 #define STEP_SKIPS_DELAY_P (1)
  54 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  55
  56 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  57    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  58    real way to know how big a register is.  */
  59
  60 #define REGISTER_SIZE 4
  61
  62 /* The size of a register.  This is predefined in tm-mips64.h.  We
  63    can't use REGISTER_SIZE because that is used for various other
  64    things.  */
  65
  66 #ifndef MIPS_REGSIZE
  67 #define MIPS_REGSIZE 4
  68 #endif
  69
  70 /* Number of machine registers */
  71
  72 #ifndef NUM_REGS
  73 #define NUM_REGS 90
  74 #endif
  75
  76 /* Initializer for an array of names of registers.
  77    There should be NUM_REGS strings in this initializer.  */
  78
  79 #ifndef MIPS_REGISTER_NAMES
  80 #define MIPS_REGISTER_NAMES     \
  81     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
  82         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
  83         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
  84         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
  85         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
  86         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
  87         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
  88         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
  89         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
  90         "fsr",  "fir",  ""/*"fp"*/,     "", \
  91         "",     "",     "",     "",     "",     "",     "",     "", \
  92         "",     "",     "",     "",     "",     "",     "",     "", \
  93     }
  94 #endif
  95
  96 /* Register numbers of various important registers.
  97    Note that some of these values are "real" register numbers,
  98    and correspond to the general registers of the machine,
  99    and some are "phony" register numbers which are too large
 100    to be actual register numbers as far as the user is concerned
 101    but do serve to get the desired values when passed to read_register.  */
 102
 103 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 104 #define V0_REGNUM 2             /* Function integer return value */
 105 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 106 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 107 #define SP_REGNUM 29            /* Contains address of top of stack */
 108 #define RA_REGNUM 31            /* Contains return address value */
 109 #define PS_REGNUM 32            /* Contains processor status */
 110 #define HI_REGNUM 34            /* Multiple/divide temp */
 111 #define LO_REGNUM 33            /* ... */
 112 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 113 #define CAUSE_REGNUM 36         /* describes last exception */
 114 #define PC_REGNUM 37            /* Contains program counter */
 115 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 116 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 117 #define FCRCS_REGNUM 70         /* FP control/status */
 118 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 119 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 120 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 121 #define PRID_REGNUM 89          /* Processor ID */
 122 #define LAST_EMBED_REGNUM 89    /* Last one */
 123
 124 /* Total amount of space needed to store our copies of the machine's
 125    register state, the array `registers'.  */
 126
 127 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 128
 129 /* Index within `registers' of the first byte of the space for
 130    register N.  */
 131
 132 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 133
 134 /* Return the GDB type object for the "standard" data type of data in
 135    register N.  */
 136
 137 #ifndef REGISTER_VIRTUAL_TYPE
 138 #define REGISTER_VIRTUAL_TYPE(N) \
 139         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 140          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 141          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 142          : builtin_type_int)
 143 #endif
 144
 145 /* All mips targets store doubles in a register pair with the least
 146    significant register in the lower numbered register.
 147    If the target is big endian, double register values need conversion
 148    between memory and register formats.  */
 149
 150 extern void mips_register_convert_to_type (int regnum,
 151                                            struct type *type,
 152                                            char *buffer);
 153 extern void mips_register_convert_from_type (int regnum,
 154                                              struct type *type,
 155                                              char *buffer);
 156
 157 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)       \
 158   mips_register_convert_to_type ((n), (type), (buffer))
 159
 160 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)     \
 161   mips_register_convert_from_type ((n), (type), (buffer))
 162
 163 \f
 164 /* Special symbol found in blocks associated with routines.  We can hang
 165    mips_extra_func_info_t's off of this.  */
 166
 167 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 168 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 169
 170 /* Specific information about a procedure.
 171    This overlays the MIPS's PDR records,
 172    mipsread.c (ab)uses this to save memory */
 173
 174 typedef struct mips_extra_func_info
 175   {
 176     long numargs;               /* number of args to procedure (was iopt) */
 177     bfd_vma high_addr;          /* upper address bound */
 178     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 179     PDR pdr;                    /* Procedure descriptor record */
 180   }
 181  *mips_extra_func_info_t;
 182
 183 extern void mips_print_extra_frame_info (struct frame_info *frame);
 184 #define PRINT_EXTRA_FRAME_INFO(fi) \
 185   mips_print_extra_frame_info (fi)
 186
 187 /* It takes two values to specify a frame on the MIPS.
 188
 189    In fact, the *PC* is the primary value that sets up a frame.  The
 190    PC is looked up to see what function it's in; symbol information
 191    from that function tells us which register is the frame pointer
 192    base, and what offset from there is the "virtual frame pointer".
 193    (This is usually an offset from SP.)  On most non-MIPS machines,
 194    the primary value is the SP, and the PC, if needed, disambiguates
 195    multiple functions with the same SP.  But on the MIPS we can't do
 196    that since the PC is not stored in the same part of the frame every
 197    time.  This does not seem to be a very clever way to set up frames,
 198    but there is nothing we can do about that.  */
 199
 200 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 201 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 202
 203 /* Select the default mips disassembler */
 204
 205 #define TM_PRINT_INSN_MACH 0
 206
 207 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 208 extern CORE_ADDR sigtramp_address, sigtramp_end;
 209 extern void fixup_sigtramp (void);
 210
 211 /* Defined in mips-tdep.c and used in remote-mips.c */
 212 extern char *mips_read_processor_type (void);
 213
 214 /* Functions for dealing with MIPS16 call and return stubs.  */
 215 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 216 extern int mips_ignore_helper (CORE_ADDR pc);
 217
 218 #ifndef TARGET_MIPS
 219 #define TARGET_MIPS
 220 #endif
 221
 222 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 223 #define MIPS_INSTLEN 4          /* Length of an instruction */
 224 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 225 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 226 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 227
 228 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 229    macros to test, set, or clear bit 0 of addresses.  */
 230 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 231 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 232 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 233
 234 #endif /* TM_MIPS_H */
 235
 236 /* Command to set the processor type. */
 237 extern void mips_set_processor_type_command (char *, int);
 238
 239 /* Single step based on where the current instruction will take us.  */
 240 extern void mips_software_single_step (enum target_signal, int);