gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000
   4    Free Software Foundation, Inc.
   5    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   6    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330,
  23    Boston, MA 02111-1307, USA.  */
  24
  25 #ifndef TM_MIPS_H
  26 #define TM_MIPS_H 1
  27
  28 #define GDB_MULTI_ARCH 1
  29
  30 #include "regcache.h"
  31
  32 struct frame_info;
  33 struct symbol;
  34 struct type;
  35 struct value;
  36
  37 #include <bfd.h>
  38 #include "coff/sym.h"           /* Needed for PDR below.  */
  39 #include "coff/symconst.h"
  40
  41 /* PC should be masked to remove possible MIPS16 flag */
  42 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  43 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  44 #endif
  45 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  46 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  47 #endif
  48
  49 /* The name of the usual type of MIPS processor that is in the target
  50    system.  */
  51
  52 #define DEFAULT_MIPS_TYPE "generic"
  53
  54 /* Remove useless bits from the stack pointer.  */
  55
  56 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  57
  58 /* Offset from address of function to start of its code.
  59    Zero on most machines.  */
  60
  61 #define FUNCTION_START_OFFSET 0
  62
  63 /* Return non-zero if PC points to an instruction which will cause a step
  64    to execute both the instruction at PC and an instruction at PC+4.  */
  65 extern int mips_step_skips_delay (CORE_ADDR);
  66 #define STEP_SKIPS_DELAY_P (1)
  67 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  68
  69 /* Are we currently handling a signal */
  70
  71 extern int in_sigtramp (CORE_ADDR, char *);
  72 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  73
  74 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  75    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  76    real way to know how big a register is.  */
  77
  78 #define REGISTER_SIZE 4
  79
  80 /* The size of a register.  This is predefined in tm-mips64.h.  We
  81    can't use REGISTER_SIZE because that is used for various other
  82    things.  */
  83
  84 #ifndef MIPS_REGSIZE
  85 #define MIPS_REGSIZE 4
  86 #endif
  87
  88 /* Number of machine registers */
  89
  90 #ifndef NUM_REGS
  91 #define NUM_REGS 90
  92 #endif
  93
  94 /* Given the register index, return the name of the corresponding
  95    register. */
  96 extern const char *mips_register_name (int regnr);
  97 #define REGISTER_NAME(i) mips_register_name (i)
  98
  99 /* Initializer for an array of names of registers.
 100    There should be NUM_REGS strings in this initializer.  */
 101
 102 #ifndef MIPS_REGISTER_NAMES
 103 #define MIPS_REGISTER_NAMES     \
 104     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 105         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 106         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 107         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 108         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 109         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 110         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 111         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 112         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 113         "fsr",  "fir",  "fp",   "", \
 114         "",     "",     "",     "",     "",     "",     "",     "", \
 115         "",     "",     "",     "",     "",     "",     "",     "", \
 116     }
 117 #endif
 118
 119 /* Register numbers of various important registers.
 120    Note that some of these values are "real" register numbers,
 121    and correspond to the general registers of the machine,
 122    and some are "phony" register numbers which are too large
 123    to be actual register numbers as far as the user is concerned
 124    but do serve to get the desired values when passed to read_register.  */
 125
 126 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 127 #define V0_REGNUM 2             /* Function integer return value */
 128 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 129 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 130 #define SP_REGNUM 29            /* Contains address of top of stack */
 131 #define RA_REGNUM 31            /* Contains return address value */
 132 #define PS_REGNUM 32            /* Contains processor status */
 133 #define HI_REGNUM 34            /* Multiple/divide temp */
 134 #define LO_REGNUM 33            /* ... */
 135 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 136 #define CAUSE_REGNUM 36         /* describes last exception */
 137 #define PC_REGNUM 37            /* Contains program counter */
 138 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 139 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 140 #define FCRCS_REGNUM 70         /* FP control/status */
 141 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 142 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 143 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 144 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 145 #define PRID_REGNUM 89          /* Processor ID */
 146 #define LAST_EMBED_REGNUM 89    /* Last one */
 147
 148 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 149    of register dumps. */
 150
 151 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 152 extern void mips_do_registers_info (int, int);
 153
 154 /* Total amount of space needed to store our copies of the machine's
 155    register state, the array `registers'.  */
 156
 157 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 158
 159 /* Index within `registers' of the first byte of the space for
 160    register N.  */
 161
 162 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 163
 164 /* Covert between the RAW and VIRTUAL registers.
 165
 166    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 167    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 168    protocol which transfers 64 bits for 32 bit registers. */
 169
 170 extern int mips_register_convertible (int reg_nr);
 171 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 172
 173
 174 void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type,
 175                                        char *raw_buf, char *virt_buf);
 176 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 177   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 178
 179 void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr,
 180                                    char *virt_buf, char *raw_buf);
 181 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 182   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 183
 184 /* Number of bytes of storage in the program's representation
 185    for register N. */
 186
 187 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 188
 189 /* Largest value REGISTER_RAW_SIZE can have.  */
 190
 191 #define MAX_REGISTER_RAW_SIZE 8
 192
 193 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 194
 195 #define MAX_REGISTER_VIRTUAL_SIZE 8
 196
 197 /* Return the GDB type object for the "standard" data type of data in
 198    register N.  */
 199
 200 #ifndef REGISTER_VIRTUAL_TYPE
 201 #define REGISTER_VIRTUAL_TYPE(N) \
 202         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 203          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 204          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 205          : builtin_type_int)
 206 #endif
 207
 208 /* All mips targets store doubles in a register pair with the least
 209    significant register in the lower numbered register.
 210    If the target is big endian, double register values need conversion
 211    between memory and register formats.  */
 212
 213 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 214   do {if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG                           \
 215           && REGISTER_RAW_SIZE (n) == 4                                 \
 216           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 217           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 218           && TYPE_LENGTH(type) == 8) {                                  \
 219         char __temp[4];                                                 \
 220         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 221         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 222         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 223
 224 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 225   do {if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG                           \
 226           && REGISTER_RAW_SIZE (n) == 4                                 \
 227           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 228           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 229           && TYPE_LENGTH(type) == 8) {                                  \
 230         char __temp[4];                                                 \
 231         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 232         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 233         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 234
 235 /* Store the address of the place in which to copy the structure the
 236    subroutine will return.  Handled by mips_push_arguments.  */
 237
 238 #define STORE_STRUCT_RETURN(addr, sp)
 239 /**/
 240
 241 /* Extract from an array REGBUF containing the (raw) register state
 242    a function return value of type TYPE, and copy that, in virtual format,
 243    into VALBUF.  XXX floats */
 244
 245 #define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 246   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 247 extern void mips_extract_return_value (struct type *, char[], char *);
 248
 249 /* Write into appropriate registers a function return value
 250    of type TYPE, given in virtual format.  */
 251
 252 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 253   mips_store_return_value(TYPE, VALBUF)
 254 extern void mips_store_return_value (struct type *, char *);
 255
 256 /* Extract from an array REGBUF containing the (raw) register state
 257    the address in which a function should return its structure value,
 258    as a CORE_ADDR (or an expression that can be used as one).  */
 259 /* The address is passed in a0 upon entry to the function, but when
 260    the function exits, the compiler has copied the value to v0.  This
 261    convention is specified by the System V ABI, so I think we can rely
 262    on it.  */
 263
 264 #define DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 265   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 266                     REGISTER_RAW_SIZE (V0_REGNUM)))
 267
 268 \f
 269 /* Describe the pointer in each stack frame to the previous stack frame
 270    (its caller).  */
 271
 272 /* FRAME_CHAIN takes a frame's nominal address
 273    and produces the frame's chain-pointer. */
 274
 275 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 276 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 277
 278 /* Define other aspects of the stack frame.  */
 279
 280
 281 /* A macro that tells us whether the function invocation represented
 282    by FI does not have a frame on the stack associated with it.  If it
 283    does not, FRAMELESS is set to 1, else 0.  */
 284 /* We handle this differently for mips, and maybe we should not */
 285
 286 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 287
 288 /* Saved Pc.  */
 289
 290 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 291 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 292
 293 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 294
 295 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 296
 297 /* Return number of args passed to a frame.
 298    Can return -1, meaning no way to tell.  */
 299
 300 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 301 extern int mips_frame_num_args (struct frame_info *);
 302
 303 /* Return number of bytes at start of arglist that are not really args.  */
 304
 305 #define FRAME_ARGS_SKIP 0
 306
 307 \f
 308
 309 /* Things needed for making the inferior call functions.  */
 310
 311 /* Stack must be aligned on 32-bit boundaries when synthesizing
 312    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 313    handle it. */
 314
 315 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 316 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 317
 318 /* Push an empty stack frame, to record the current PC, etc.  */
 319
 320 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 321 extern void mips_push_dummy_frame (void);
 322
 323 /* Discard from the stack the innermost frame, restoring all registers.  */
 324
 325 #define POP_FRAME               mips_pop_frame()
 326 extern void mips_pop_frame (void);
 327
 328 #define CALL_DUMMY_START_OFFSET (0)
 329
 330 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 331
 332 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 333    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 334    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 335    will be ignored.  */
 336 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 337     write_register(T9_REGNUM, fun)
 338
 339 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 340 extern CORE_ADDR mips_call_dummy_address (void);
 341
 342 /* Special symbol found in blocks associated with routines.  We can hang
 343    mips_extra_func_info_t's off of this.  */
 344
 345 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 346 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 347
 348 /* Specific information about a procedure.
 349    This overlays the MIPS's PDR records,
 350    mipsread.c (ab)uses this to save memory */
 351
 352 typedef struct mips_extra_func_info
 353   {
 354     long numargs;               /* number of args to procedure (was iopt) */
 355     bfd_vma high_addr;          /* upper address bound */
 356     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 357     PDR pdr;                    /* Procedure descriptor record */
 358   }
 359  *mips_extra_func_info_t;
 360
 361 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 362 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 363   mips_init_extra_frame_info(fromleaf, fci)
 364
 365 extern void mips_print_extra_frame_info (struct frame_info *frame);
 366 #define PRINT_EXTRA_FRAME_INFO(fi) \
 367   mips_print_extra_frame_info (fi)
 368
 369 /* It takes two values to specify a frame on the MIPS.
 370
 371    In fact, the *PC* is the primary value that sets up a frame.  The
 372    PC is looked up to see what function it's in; symbol information
 373    from that function tells us which register is the frame pointer
 374    base, and what offset from there is the "virtual frame pointer".
 375    (This is usually an offset from SP.)  On most non-MIPS machines,
 376    the primary value is the SP, and the PC, if needed, disambiguates
 377    multiple functions with the same SP.  But on the MIPS we can't do
 378    that since the PC is not stored in the same part of the frame every
 379    time.  This does not seem to be a very clever way to set up frames,
 380    but there is nothing we can do about that.  */
 381
 382 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 383 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 384
 385 /* Select the default mips disassembler */
 386
 387 #define TM_PRINT_INSN_MACH 0
 388
 389
 390 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 391 extern CORE_ADDR sigtramp_address, sigtramp_end;
 392 extern void fixup_sigtramp (void);
 393
 394 /* Defined in mips-tdep.c and used in remote-mips.c */
 395 extern char *mips_read_processor_type (void);
 396
 397 /* Functions for dealing with MIPS16 call and return stubs.  */
 398 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 399 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 400 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 401 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 402 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 403 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 404 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 405 extern int mips_ignore_helper (CORE_ADDR pc);
 406
 407 #ifndef TARGET_MIPS
 408 #define TARGET_MIPS
 409 #endif
 410
 411 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 412 #define MIPS_INSTLEN 4          /* Length of an instruction */
 413 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 414 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 415 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 416
 417 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 418    macros to test, set, or clear bit 0 of addresses.  */
 419 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 420 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 421 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 422
 423 #endif /* TM_MIPS_H */
 424
 425 /* Macros for setting and testing a bit in a minimal symbol that
 426    marks it as 16-bit function.  The MSB of the minimal symbol's
 427    "info" field is used for this purpose. This field is already
 428    being used to store the symbol size, so the assumption is
 429    that the symbol size cannot exceed 2^31.
 430
 431    ELF_MAKE_MSYMBOL_SPECIAL
 432    tests whether an ELF symbol is "special", i.e. refers
 433    to a 16-bit function, and sets a "special" bit in a
 434    minimal symbol to mark it as a 16-bit function
 435    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 436    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 437    the "info" field with the "special" bit masked out
 438  */
 439
 440 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 441  { \
 442   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 443     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 444     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 445   } \
 446  }
 447
 448 #define MSYMBOL_IS_SPECIAL(msym) \
 449   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 450 #define MSYMBOL_SIZE(msym) \
 451   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 452
 453
 454 /* Command to set the processor type. */
 455 extern void mips_set_processor_type_command (char *, int);
 456
 457
 458 /* Single step based on where the current instruction will take us.  */
 459 extern void mips_software_single_step (enum target_signal, int);