gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #ifndef TM_MIPS_H
  25 #define TM_MIPS_H 1
  26
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31
  32 #include <bfd.h>
  33 #include "coff/sym.h"           /* Needed for PDR below.  */
  34 #include "coff/symconst.h"
  35
  36 #if !defined (GDB_TARGET_IS_MIPS64)
  37 #define GDB_TARGET_IS_MIPS64 0
  38 #endif
  39
  40 #if !defined (MIPS_EABI)
  41 #define MIPS_EABI 0
  42 #endif
  43
  44 /* PC should be masked to remove possible MIPS16 flag */
  45 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  46 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  47 #endif
  48 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  49 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  50 #endif
  51
  52 /* Floating point is IEEE compliant */
  53 #define IEEE_FLOAT (1)
  54
  55 /* The name of the usual type of MIPS processor that is in the target
  56    system.  */
  57
  58 #define DEFAULT_MIPS_TYPE "generic"
  59
  60 /* Remove useless bits from an instruction address.  */
  61
  62 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  63 CORE_ADDR mips_addr_bits_remove (CORE_ADDR addr);
  64
  65 /* Remove useless bits from the stack pointer.  */
  66
  67 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  68
  69 /* Offset from address of function to start of its code.
  70    Zero on most machines.  */
  71
  72 #define FUNCTION_START_OFFSET 0
  73
  74 /* Advance PC across any function entry prologue instructions
  75    to reach some "real" code.  */
  76
  77 #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
  78 extern CORE_ADDR mips_skip_prologue (CORE_ADDR addr, int lenient);
  79
  80 /* Return non-zero if PC points to an instruction which will cause a step
  81    to execute both the instruction at PC and an instruction at PC+4.  */
  82 extern int mips_step_skips_delay (CORE_ADDR);
  83 #define STEP_SKIPS_DELAY_P (1)
  84 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  85
  86 /* Immediately after a function call, return the saved pc.
  87    Can't always go through the frames for this because on some machines
  88    the new frame is not set up until the new function executes
  89    some instructions.  */
  90
  91 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
  92
  93 /* Are we currently handling a signal */
  94
  95 extern int in_sigtramp (CORE_ADDR, char *);
  96 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  97
  98 /* Stack grows downward.  */
  99
 100 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 101
 102 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 103    16- or 32-bit breakpoint should be used.  It returns a pointer
 104    to a string of bytes that encode a breakpoint instruction, stores
 105    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 106    point to the actual memory location where the breakpoint should be
 107    inserted.  */
 108
 109 extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
 110 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 111
 112 /* Amount PC must be decremented by after a breakpoint.
 113    This is often the number of bytes in BREAKPOINT
 114    but not always.  */
 115
 116 #define DECR_PC_AFTER_BREAK 0
 117
 118 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 119    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 120    real way to know how big a register is.  */
 121
 122 #define REGISTER_SIZE 4
 123
 124 /* The size of a register.  This is predefined in tm-mips64.h.  We
 125    can't use REGISTER_SIZE because that is used for various other
 126    things.  */
 127
 128 #ifndef MIPS_REGSIZE
 129 #define MIPS_REGSIZE 4
 130 #endif
 131
 132 /* The sizes of floating point registers.  */
 133
 134 #define MIPS_FPU_SINGLE_REGSIZE 4
 135 #define MIPS_FPU_DOUBLE_REGSIZE 8
 136
 137 /* Number of machine registers */
 138
 139 #ifndef NUM_REGS
 140 #define NUM_REGS 90
 141 #endif
 142
 143 /* Given the register index, return the name of the corresponding
 144    register. */
 145 extern char *mips_register_name (int regnr);
 146 #define REGISTER_NAME(i) mips_register_name (i)
 147
 148 /* Initializer for an array of names of registers.
 149    There should be NUM_REGS strings in this initializer.  */
 150
 151 #ifndef MIPS_REGISTER_NAMES
 152 #define MIPS_REGISTER_NAMES     \
 153     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 154         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 155         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 156         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 157         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 158         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 159         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 160         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 161         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 162         "fsr",  "fir",  "fp",   "", \
 163         "",     "",     "",     "",     "",     "",     "",     "", \
 164         "",     "",     "",     "",     "",     "",     "",     "", \
 165     }
 166 #endif
 167
 168 /* Register numbers of various important registers.
 169    Note that some of these values are "real" register numbers,
 170    and correspond to the general registers of the machine,
 171    and some are "phony" register numbers which are too large
 172    to be actual register numbers as far as the user is concerned
 173    but do serve to get the desired values when passed to read_register.  */
 174
 175 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 176 #define V0_REGNUM 2             /* Function integer return value */
 177 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 178 #if MIPS_EABI
 179 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 180 #else
 181 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 182 #endif
 183 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 184 #define SP_REGNUM 29            /* Contains address of top of stack */
 185 #define RA_REGNUM 31            /* Contains return address value */
 186 #define PS_REGNUM 32            /* Contains processor status */
 187 #define HI_REGNUM 34            /* Multiple/divide temp */
 188 #define LO_REGNUM 33            /* ... */
 189 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 190 #define CAUSE_REGNUM 36         /* describes last exception */
 191 #define PC_REGNUM 37            /* Contains program counter */
 192 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 193 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 194 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 195 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 196 #else /* old ABI uses F12 through F15 for args */
 197 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 198 #endif
 199 #define FCRCS_REGNUM 70         /* FP control/status */
 200 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 201 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 202 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 203 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 204 #define PRID_REGNUM 89          /* Processor ID */
 205 #define LAST_EMBED_REGNUM 89    /* Last one */
 206
 207 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 208    of register dumps. */
 209
 210 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 211 extern void mips_do_registers_info (int, int);
 212
 213 /* Total amount of space needed to store our copies of the machine's
 214    register state, the array `registers'.  */
 215
 216 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 217
 218 /* Index within `registers' of the first byte of the space for
 219    register N.  */
 220
 221 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 222
 223 /* Number of bytes of storage in the actual machine representation for
 224    register N.  NOTE: This indirectly defines the register size
 225    transfered by the GDB protocol. */
 226
 227 extern int mips_register_raw_size (int reg_nr);
 228 #define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N)))
 229
 230
 231 /* Covert between the RAW and VIRTUAL registers.
 232
 233    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 234    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 235    protocol which transfers 64 bits for 32 bit registers. */
 236
 237 extern int mips_register_convertible (int reg_nr);
 238 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 239
 240
 241 void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type,
 242                                        char *raw_buf, char *virt_buf);
 243 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 244   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 245
 246 void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr,
 247                                    char *virt_buf, char *raw_buf);
 248 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 249   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 250
 251 /* Number of bytes of storage in the program's representation
 252    for register N. */
 253
 254 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 255
 256 /* Largest value REGISTER_RAW_SIZE can have.  */
 257
 258 #define MAX_REGISTER_RAW_SIZE 8
 259
 260 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 261
 262 #define MAX_REGISTER_VIRTUAL_SIZE 8
 263
 264 /* Return the GDB type object for the "standard" data type of data in
 265    register N.  */
 266
 267 #ifndef REGISTER_VIRTUAL_TYPE
 268 #define REGISTER_VIRTUAL_TYPE(N) \
 269         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 270          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 271          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 272          : builtin_type_int)
 273 #endif
 274
 275 /* All mips targets store doubles in a register pair with the least
 276    significant register in the lower numbered register.
 277    If the target is big endian, double register values need conversion
 278    between memory and register formats.  */
 279
 280 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 281   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 282           && REGISTER_RAW_SIZE (n) == 4                                 \
 283           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 284           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 285           && TYPE_LENGTH(type) == 8) {                                  \
 286         char __temp[4];                                                 \
 287         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 288         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 289         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 290
 291 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 292   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 293           && REGISTER_RAW_SIZE (n) == 4                                 \
 294           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 295           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 296           && TYPE_LENGTH(type) == 8) {                                  \
 297         char __temp[4];                                                 \
 298         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 299         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 300         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 301
 302 /* Store the address of the place in which to copy the structure the
 303    subroutine will return.  Handled by mips_push_arguments.  */
 304
 305 #define STORE_STRUCT_RETURN(addr, sp)
 306 /**/
 307
 308 /* Extract from an array REGBUF containing the (raw) register state
 309    a function return value of type TYPE, and copy that, in virtual format,
 310    into VALBUF.  XXX floats */
 311
 312 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 313   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 314 extern void mips_extract_return_value (struct type *, char[], char *);
 315
 316 /* Write into appropriate registers a function return value
 317    of type TYPE, given in virtual format.  */
 318
 319 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 320   mips_store_return_value(TYPE, VALBUF)
 321 extern void mips_store_return_value (struct type *, char *);
 322
 323 /* Extract from an array REGBUF containing the (raw) register state
 324    the address in which a function should return its structure value,
 325    as a CORE_ADDR (or an expression that can be used as one).  */
 326 /* The address is passed in a0 upon entry to the function, but when
 327    the function exits, the compiler has copied the value to v0.  This
 328    convention is specified by the System V ABI, so I think we can rely
 329    on it.  */
 330
 331 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 332   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 333                     REGISTER_RAW_SIZE (V0_REGNUM)))
 334
 335 extern use_struct_convention_fn mips_use_struct_convention;
 336 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 337 \f
 338 /* Describe the pointer in each stack frame to the previous stack frame
 339    (its caller).  */
 340
 341 /* FRAME_CHAIN takes a frame's nominal address
 342    and produces the frame's chain-pointer. */
 343
 344 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 345 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 346
 347 /* Define other aspects of the stack frame.  */
 348
 349
 350 /* A macro that tells us whether the function invocation represented
 351    by FI does not have a frame on the stack associated with it.  If it
 352    does not, FRAMELESS is set to 1, else 0.  */
 353 /* We handle this differently for mips, and maybe we should not */
 354
 355 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 356
 357 /* Saved Pc.  */
 358
 359 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 360 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 361
 362 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 363
 364 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 365
 366 /* Return number of args passed to a frame.
 367    Can return -1, meaning no way to tell.  */
 368
 369 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 370 extern int mips_frame_num_args (struct frame_info *);
 371
 372 /* Return number of bytes at start of arglist that are not really args.  */
 373
 374 #define FRAME_ARGS_SKIP 0
 375
 376 /* Put here the code to store, into a struct frame_saved_regs,
 377    the addresses of the saved registers of frame described by FRAME_INFO.
 378    This includes special registers such as pc and fp saved in special
 379    ways in the stack frame.  sp is even more special:
 380    the address we return for it IS the sp for the next frame.  */
 381
 382 #define FRAME_INIT_SAVED_REGS(frame_info) \
 383   do { \
 384     if ((frame_info)->saved_regs == NULL) \
 385       mips_find_saved_regs (frame_info); \
 386     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 387   } while (0)
 388 extern void mips_find_saved_regs (struct frame_info *);
 389 \f
 390
 391 /* Things needed for making the inferior call functions.  */
 392
 393 /* Stack must be aligned on 32-bit boundaries when synthesizing
 394    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 395    handle it. */
 396
 397 extern CORE_ADDR mips_push_arguments (int, struct value **, CORE_ADDR, int,
 398                                       CORE_ADDR);
 399 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 400   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 401
 402 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 403 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 404
 405 /* Push an empty stack frame, to record the current PC, etc.  */
 406
 407 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 408 extern void mips_push_dummy_frame (void);
 409
 410 /* Discard from the stack the innermost frame, restoring all registers.  */
 411
 412 #define POP_FRAME               mips_pop_frame()
 413 extern void mips_pop_frame (void);
 414
 415 #if !GDB_MULTI_ARCH
 416 #define CALL_DUMMY { 0 }
 417 #endif
 418
 419 #define CALL_DUMMY_START_OFFSET (0)
 420
 421 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 422
 423 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 424    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 425    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 426    will be ignored.  */
 427 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 428     write_register(T9_REGNUM, fun)
 429
 430 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 431
 432 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 433 extern CORE_ADDR mips_call_dummy_address (void);
 434
 435 /* There's a mess in stack frame creation.  See comments in blockframe.c
 436    near reference to INIT_FRAME_PC_FIRST.  */
 437
 438 #define INIT_FRAME_PC(fromleaf, prev)   /* nada */
 439
 440 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 441    mips_init_frame_pc_first(fromleaf, prev)
 442 extern void mips_init_frame_pc_first (int, struct frame_info *);
 443
 444 /* Special symbol found in blocks associated with routines.  We can hang
 445    mips_extra_func_info_t's off of this.  */
 446
 447 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 448 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 449
 450 /* Specific information about a procedure.
 451    This overlays the MIPS's PDR records,
 452    mipsread.c (ab)uses this to save memory */
 453
 454 typedef struct mips_extra_func_info
 455   {
 456     long numargs;               /* number of args to procedure (was iopt) */
 457     bfd_vma high_addr;          /* upper address bound */
 458     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 459     PDR pdr;                    /* Procedure descriptor record */
 460   }
 461  *mips_extra_func_info_t;
 462
 463 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 464 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 465   mips_init_extra_frame_info(fromleaf, fci)
 466
 467 extern void mips_print_extra_frame_info (struct frame_info *frame);
 468 #define PRINT_EXTRA_FRAME_INFO(fi) \
 469   mips_print_extra_frame_info (fi)
 470
 471 /* It takes two values to specify a frame on the MIPS.
 472
 473    In fact, the *PC* is the primary value that sets up a frame.  The
 474    PC is looked up to see what function it's in; symbol information
 475    from that function tells us which register is the frame pointer
 476    base, and what offset from there is the "virtual frame pointer".
 477    (This is usually an offset from SP.)  On most non-MIPS machines,
 478    the primary value is the SP, and the PC, if needed, disambiguates
 479    multiple functions with the same SP.  But on the MIPS we can't do
 480    that since the PC is not stored in the same part of the frame every
 481    time.  This does not seem to be a very clever way to set up frames,
 482    but there is nothing we can do about that).  */
 483
 484 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 485 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 486
 487 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 488
 489 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 490
 491 /* Convert a ecoff register number to a gdb REGNUM */
 492
 493 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 494
 495 #if !GDB_MULTI_ARCH
 496 /* If the current gcc for for this target does not produce correct debugging
 497    information for float parameters, both prototyped and unprototyped, then
 498    define this macro.  This forces gdb to  always assume that floats are
 499    passed as doubles and then converted in the callee.
 500
 501    For the mips chip, it appears that the debug info marks the parameters as
 502    floats regardless of whether the function is prototyped, but the actual
 503    values are passed as doubles for the non-prototyped case and floats for
 504    the prototyped case.  Thus we choose to make the non-prototyped case work
 505    for C and break the prototyped case, since the non-prototyped case is
 506    probably much more common.  (FIXME). */
 507
 508 #define COERCE_FLOAT_TO_DOUBLE(formal, actual) (current_language -> la_language == language_c)
 509 #endif
 510
 511 /* Select the default mips disassembler */
 512
 513 #define TM_PRINT_INSN_MACH 0
 514
 515
 516 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 517 extern CORE_ADDR sigtramp_address, sigtramp_end;
 518 extern void fixup_sigtramp (void);
 519
 520 /* Defined in mips-tdep.c and used in remote-mips.c */
 521 extern char *mips_read_processor_type (void);
 522
 523 /* Functions for dealing with MIPS16 call and return stubs.  */
 524 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 525 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 526 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 527 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 528 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 529 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 530 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 531 extern int mips_ignore_helper (CORE_ADDR pc);
 532
 533 #ifndef TARGET_MIPS
 534 #define TARGET_MIPS
 535 #endif
 536
 537 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 538 #define MIPS_INSTLEN 4          /* Length of an instruction */
 539 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 540 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 541 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 542
 543 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 544    macros to test, set, or clear bit 0 of addresses.  */
 545 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 546 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 547 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 548
 549 #endif /* TM_MIPS_H */
 550
 551 /* Macros for setting and testing a bit in a minimal symbol that
 552    marks it as 16-bit function.  The MSB of the minimal symbol's
 553    "info" field is used for this purpose. This field is already
 554    being used to store the symbol size, so the assumption is
 555    that the symbol size cannot exceed 2^31.
 556
 557    ELF_MAKE_MSYMBOL_SPECIAL
 558    tests whether an ELF symbol is "special", i.e. refers
 559    to a 16-bit function, and sets a "special" bit in a
 560    minimal symbol to mark it as a 16-bit function
 561    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 562    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 563    the "info" field with the "special" bit masked out
 564  */
 565
 566 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 567  { \
 568   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 569     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 570     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 571   } \
 572  }
 573
 574 #define MSYMBOL_IS_SPECIAL(msym) \
 575   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 576 #define MSYMBOL_SIZE(msym) \
 577   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 578
 579
 580 /* Command to set the processor type. */
 581 extern void mips_set_processor_type_command (char *, int);
 582
 583
 584 /* MIPS sign extends addresses */
 585 #define POINTER_TO_ADDRESS(TYPE,BUF) (signed_pointer_to_address (TYPE, BUF))
 586 #define ADDRESS_TO_POINTER(TYPE,BUF,ADDR) (address_to_signed_pointer (TYPE, BUF, ADDR))
 587
 588
 589 /* MIPS is always bi-endian */
 590 #if !GDB_MULTI_ARCH
 591 #define TARGET_BYTE_ORDER_SELECTABLE_P 1
 592 #endif