gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #ifndef TM_MIPS_H
  25 #define TM_MIPS_H 1
  26
  27 #define GDB_MULTI_ARCH 1
  28
  29 struct frame_info;
  30 struct symbol;
  31 struct type;
  32 struct value;
  33
  34 #include <bfd.h>
  35 #include "coff/sym.h"           /* Needed for PDR below.  */
  36 #include "coff/symconst.h"
  37
  38 #if !defined (MIPS_EABI)
  39 #define MIPS_EABI 0
  40 #endif
  41
  42 /* PC should be masked to remove possible MIPS16 flag */
  43 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  44 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  45 #endif
  46 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  47 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  48 #endif
  49
  50 /* Floating point is IEEE compliant */
  51 #define IEEE_FLOAT (1)
  52
  53 /* The name of the usual type of MIPS processor that is in the target
  54    system.  */
  55
  56 #define DEFAULT_MIPS_TYPE "generic"
  57
  58 /* Remove useless bits from an instruction address.  */
  59
  60 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  61 CORE_ADDR mips_addr_bits_remove (CORE_ADDR addr);
  62
  63 /* Remove useless bits from the stack pointer.  */
  64
  65 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  66
  67 /* Offset from address of function to start of its code.
  68    Zero on most machines.  */
  69
  70 #define FUNCTION_START_OFFSET 0
  71
  72 /* Advance PC across any function entry prologue instructions
  73    to reach some "real" code.  */
  74
  75 #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
  76 extern CORE_ADDR mips_skip_prologue (CORE_ADDR addr, int lenient);
  77
  78 /* Return non-zero if PC points to an instruction which will cause a step
  79    to execute both the instruction at PC and an instruction at PC+4.  */
  80 extern int mips_step_skips_delay (CORE_ADDR);
  81 #define STEP_SKIPS_DELAY_P (1)
  82 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  83
  84 /* Immediately after a function call, return the saved pc.
  85    Can't always go through the frames for this because on some machines
  86    the new frame is not set up until the new function executes
  87    some instructions.  */
  88
  89 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
  90
  91 /* Are we currently handling a signal */
  92
  93 extern int in_sigtramp (CORE_ADDR, char *);
  94 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  95
  96 /* Stack grows downward.  */
  97
  98 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
  99
 100 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 101    16- or 32-bit breakpoint should be used.  It returns a pointer
 102    to a string of bytes that encode a breakpoint instruction, stores
 103    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 104    point to the actual memory location where the breakpoint should be
 105    inserted.  */
 106
 107 extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
 108 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 109
 110 /* Amount PC must be decremented by after a breakpoint.
 111    This is often the number of bytes in BREAKPOINT
 112    but not always.  */
 113
 114 #define DECR_PC_AFTER_BREAK 0
 115
 116 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 117    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 118    real way to know how big a register is.  */
 119
 120 #define REGISTER_SIZE 4
 121
 122 /* The size of a register.  This is predefined in tm-mips64.h.  We
 123    can't use REGISTER_SIZE because that is used for various other
 124    things.  */
 125
 126 #ifndef MIPS_REGSIZE
 127 #define MIPS_REGSIZE 4
 128 #endif
 129
 130 /* Number of machine registers */
 131
 132 #ifndef NUM_REGS
 133 #define NUM_REGS 90
 134 #endif
 135
 136 /* Given the register index, return the name of the corresponding
 137    register. */
 138 extern char *mips_register_name (int regnr);
 139 #define REGISTER_NAME(i) mips_register_name (i)
 140
 141 /* Initializer for an array of names of registers.
 142    There should be NUM_REGS strings in this initializer.  */
 143
 144 #ifndef MIPS_REGISTER_NAMES
 145 #define MIPS_REGISTER_NAMES     \
 146     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 147         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 148         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 149         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 150         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 151         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 152         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 153         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 154         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 155         "fsr",  "fir",  "fp",   "", \
 156         "",     "",     "",     "",     "",     "",     "",     "", \
 157         "",     "",     "",     "",     "",     "",     "",     "", \
 158     }
 159 #endif
 160
 161 /* Register numbers of various important registers.
 162    Note that some of these values are "real" register numbers,
 163    and correspond to the general registers of the machine,
 164    and some are "phony" register numbers which are too large
 165    to be actual register numbers as far as the user is concerned
 166    but do serve to get the desired values when passed to read_register.  */
 167
 168 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 169 #define V0_REGNUM 2             /* Function integer return value */
 170 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 171 #if MIPS_EABI
 172 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 173 #else
 174 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 175 #endif
 176 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 177 #define SP_REGNUM 29            /* Contains address of top of stack */
 178 #define RA_REGNUM 31            /* Contains return address value */
 179 #define PS_REGNUM 32            /* Contains processor status */
 180 #define HI_REGNUM 34            /* Multiple/divide temp */
 181 #define LO_REGNUM 33            /* ... */
 182 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 183 #define CAUSE_REGNUM 36         /* describes last exception */
 184 #define PC_REGNUM 37            /* Contains program counter */
 185 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 186 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 187 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 188 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 189 #else /* old ABI uses F12 through F15 for args */
 190 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 191 #endif
 192 #define FCRCS_REGNUM 70         /* FP control/status */
 193 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 194 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 195 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 196 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 197 #define PRID_REGNUM 89          /* Processor ID */
 198 #define LAST_EMBED_REGNUM 89    /* Last one */
 199
 200 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 201    of register dumps. */
 202
 203 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 204 extern void mips_do_registers_info (int, int);
 205
 206 /* Total amount of space needed to store our copies of the machine's
 207    register state, the array `registers'.  */
 208
 209 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 210
 211 /* Index within `registers' of the first byte of the space for
 212    register N.  */
 213
 214 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 215
 216 /* Number of bytes of storage in the actual machine representation for
 217    register N.  NOTE: This indirectly defines the register size
 218    transfered by the GDB protocol. */
 219
 220 extern int mips_register_raw_size (int reg_nr);
 221 #define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N)))
 222
 223
 224 /* Covert between the RAW and VIRTUAL registers.
 225
 226    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 227    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 228    protocol which transfers 64 bits for 32 bit registers. */
 229
 230 extern int mips_register_convertible (int reg_nr);
 231 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 232
 233
 234 void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type,
 235                                        char *raw_buf, char *virt_buf);
 236 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 237   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 238
 239 void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr,
 240                                    char *virt_buf, char *raw_buf);
 241 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 242   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 243
 244 /* Number of bytes of storage in the program's representation
 245    for register N. */
 246
 247 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 248
 249 /* Largest value REGISTER_RAW_SIZE can have.  */
 250
 251 #define MAX_REGISTER_RAW_SIZE 8
 252
 253 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 254
 255 #define MAX_REGISTER_VIRTUAL_SIZE 8
 256
 257 /* Return the GDB type object for the "standard" data type of data in
 258    register N.  */
 259
 260 #ifndef REGISTER_VIRTUAL_TYPE
 261 #define REGISTER_VIRTUAL_TYPE(N) \
 262         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 263          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 264          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 265          : builtin_type_int)
 266 #endif
 267
 268 /* All mips targets store doubles in a register pair with the least
 269    significant register in the lower numbered register.
 270    If the target is big endian, double register values need conversion
 271    between memory and register formats.  */
 272
 273 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 274   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 275           && REGISTER_RAW_SIZE (n) == 4                                 \
 276           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 277           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 278           && TYPE_LENGTH(type) == 8) {                                  \
 279         char __temp[4];                                                 \
 280         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 281         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 282         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 283
 284 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 285   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 286           && REGISTER_RAW_SIZE (n) == 4                                 \
 287           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 288           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 289           && TYPE_LENGTH(type) == 8) {                                  \
 290         char __temp[4];                                                 \
 291         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 292         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 293         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 294
 295 /* Store the address of the place in which to copy the structure the
 296    subroutine will return.  Handled by mips_push_arguments.  */
 297
 298 #define STORE_STRUCT_RETURN(addr, sp)
 299 /**/
 300
 301 /* Extract from an array REGBUF containing the (raw) register state
 302    a function return value of type TYPE, and copy that, in virtual format,
 303    into VALBUF.  XXX floats */
 304
 305 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 306   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 307 extern void mips_extract_return_value (struct type *, char[], char *);
 308
 309 /* Write into appropriate registers a function return value
 310    of type TYPE, given in virtual format.  */
 311
 312 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 313   mips_store_return_value(TYPE, VALBUF)
 314 extern void mips_store_return_value (struct type *, char *);
 315
 316 /* Extract from an array REGBUF containing the (raw) register state
 317    the address in which a function should return its structure value,
 318    as a CORE_ADDR (or an expression that can be used as one).  */
 319 /* The address is passed in a0 upon entry to the function, but when
 320    the function exits, the compiler has copied the value to v0.  This
 321    convention is specified by the System V ABI, so I think we can rely
 322    on it.  */
 323
 324 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 325   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 326                     REGISTER_RAW_SIZE (V0_REGNUM)))
 327
 328 extern use_struct_convention_fn mips_use_struct_convention;
 329 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 330 \f
 331 /* Describe the pointer in each stack frame to the previous stack frame
 332    (its caller).  */
 333
 334 /* FRAME_CHAIN takes a frame's nominal address
 335    and produces the frame's chain-pointer. */
 336
 337 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 338 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 339
 340 /* Define other aspects of the stack frame.  */
 341
 342
 343 /* A macro that tells us whether the function invocation represented
 344    by FI does not have a frame on the stack associated with it.  If it
 345    does not, FRAMELESS is set to 1, else 0.  */
 346 /* We handle this differently for mips, and maybe we should not */
 347
 348 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 349
 350 /* Saved Pc.  */
 351
 352 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 353 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 354
 355 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 356
 357 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 358
 359 /* Return number of args passed to a frame.
 360    Can return -1, meaning no way to tell.  */
 361
 362 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 363 extern int mips_frame_num_args (struct frame_info *);
 364
 365 /* Return number of bytes at start of arglist that are not really args.  */
 366
 367 #define FRAME_ARGS_SKIP 0
 368
 369 /* Put here the code to store, into a struct frame_saved_regs,
 370    the addresses of the saved registers of frame described by FRAME_INFO.
 371    This includes special registers such as pc and fp saved in special
 372    ways in the stack frame.  sp is even more special:
 373    the address we return for it IS the sp for the next frame.  */
 374
 375 #define FRAME_INIT_SAVED_REGS(frame_info) \
 376   do { \
 377     if ((frame_info)->saved_regs == NULL) \
 378       mips_find_saved_regs (frame_info); \
 379     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 380   } while (0)
 381 extern void mips_find_saved_regs (struct frame_info *);
 382 \f
 383
 384 /* Things needed for making the inferior call functions.  */
 385
 386 /* Stack must be aligned on 32-bit boundaries when synthesizing
 387    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 388    handle it. */
 389
 390 extern CORE_ADDR mips_push_arguments (int, struct value **, CORE_ADDR, int,
 391                                       CORE_ADDR);
 392 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 393   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 394
 395 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 396 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 397
 398 /* Push an empty stack frame, to record the current PC, etc.  */
 399
 400 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 401 extern void mips_push_dummy_frame (void);
 402
 403 /* Discard from the stack the innermost frame, restoring all registers.  */
 404
 405 #define POP_FRAME               mips_pop_frame()
 406 extern void mips_pop_frame (void);
 407
 408 #define CALL_DUMMY_START_OFFSET (0)
 409
 410 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 411
 412 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 413    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 414    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 415    will be ignored.  */
 416 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 417     write_register(T9_REGNUM, fun)
 418
 419 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 420
 421 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 422 extern CORE_ADDR mips_call_dummy_address (void);
 423
 424 /* There's a mess in stack frame creation.  See comments in blockframe.c
 425    near reference to INIT_FRAME_PC_FIRST.  */
 426
 427 #define INIT_FRAME_PC(fromleaf, prev)   /* nada */
 428
 429 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 430    mips_init_frame_pc_first(fromleaf, prev)
 431 extern void mips_init_frame_pc_first (int, struct frame_info *);
 432
 433 /* Special symbol found in blocks associated with routines.  We can hang
 434    mips_extra_func_info_t's off of this.  */
 435
 436 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 437 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 438
 439 /* Specific information about a procedure.
 440    This overlays the MIPS's PDR records,
 441    mipsread.c (ab)uses this to save memory */
 442
 443 typedef struct mips_extra_func_info
 444   {
 445     long numargs;               /* number of args to procedure (was iopt) */
 446     bfd_vma high_addr;          /* upper address bound */
 447     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 448     PDR pdr;                    /* Procedure descriptor record */
 449   }
 450  *mips_extra_func_info_t;
 451
 452 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 453 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 454   mips_init_extra_frame_info(fromleaf, fci)
 455
 456 extern void mips_print_extra_frame_info (struct frame_info *frame);
 457 #define PRINT_EXTRA_FRAME_INFO(fi) \
 458   mips_print_extra_frame_info (fi)
 459
 460 /* It takes two values to specify a frame on the MIPS.
 461
 462    In fact, the *PC* is the primary value that sets up a frame.  The
 463    PC is looked up to see what function it's in; symbol information
 464    from that function tells us which register is the frame pointer
 465    base, and what offset from there is the "virtual frame pointer".
 466    (This is usually an offset from SP.)  On most non-MIPS machines,
 467    the primary value is the SP, and the PC, if needed, disambiguates
 468    multiple functions with the same SP.  But on the MIPS we can't do
 469    that since the PC is not stored in the same part of the frame every
 470    time.  This does not seem to be a very clever way to set up frames,
 471    but there is nothing we can do about that).  */
 472
 473 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 474 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 475
 476 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 477
 478 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 479
 480 /* Convert a ecoff register number to a gdb REGNUM */
 481
 482 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 483
 484 /* Select the default mips disassembler */
 485
 486 #define TM_PRINT_INSN_MACH 0
 487
 488
 489 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 490 extern CORE_ADDR sigtramp_address, sigtramp_end;
 491 extern void fixup_sigtramp (void);
 492
 493 /* Defined in mips-tdep.c and used in remote-mips.c */
 494 extern char *mips_read_processor_type (void);
 495
 496 /* Functions for dealing with MIPS16 call and return stubs.  */
 497 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 498 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 499 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 500 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 501 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 502 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 503 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 504 extern int mips_ignore_helper (CORE_ADDR pc);
 505
 506 #ifndef TARGET_MIPS
 507 #define TARGET_MIPS
 508 #endif
 509
 510 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 511 #define MIPS_INSTLEN 4          /* Length of an instruction */
 512 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 513 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 514 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 515
 516 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 517    macros to test, set, or clear bit 0 of addresses.  */
 518 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 519 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 520 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 521
 522 #endif /* TM_MIPS_H */
 523
 524 /* Macros for setting and testing a bit in a minimal symbol that
 525    marks it as 16-bit function.  The MSB of the minimal symbol's
 526    "info" field is used for this purpose. This field is already
 527    being used to store the symbol size, so the assumption is
 528    that the symbol size cannot exceed 2^31.
 529
 530    ELF_MAKE_MSYMBOL_SPECIAL
 531    tests whether an ELF symbol is "special", i.e. refers
 532    to a 16-bit function, and sets a "special" bit in a
 533    minimal symbol to mark it as a 16-bit function
 534    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 535    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 536    the "info" field with the "special" bit masked out
 537  */
 538
 539 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 540  { \
 541   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 542     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 543     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 544   } \
 545  }
 546
 547 #define MSYMBOL_IS_SPECIAL(msym) \
 548   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 549 #define MSYMBOL_SIZE(msym) \
 550   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 551
 552
 553 /* Command to set the processor type. */
 554 extern void mips_set_processor_type_command (char *, int);
 555
 556
 557 /* MIPS sign extends addresses */
 558 #define POINTER_TO_ADDRESS(TYPE,BUF) (signed_pointer_to_address (TYPE, BUF))
 559 #define ADDRESS_TO_POINTER(TYPE,BUF,ADDR) (address_to_signed_pointer (TYPE, BUF, ADDR))