gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000
   4    Free Software Foundation, Inc.
   5    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   6    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330,
  23    Boston, MA 02111-1307, USA.  */
  24
  25 #ifndef TM_MIPS_H
  26 #define TM_MIPS_H 1
  27
  28 #define GDB_MULTI_ARCH 1
  29
  30 #include "regcache.h"
  31
  32 struct frame_info;
  33 struct symbol;
  34 struct type;
  35 struct value;
  36
  37 #include <bfd.h>
  38 #include "coff/sym.h"           /* Needed for PDR below.  */
  39 #include "coff/symconst.h"
  40
  41 /* PC should be masked to remove possible MIPS16 flag */
  42 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  43 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  44 #endif
  45 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  46 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  47 #endif
  48
  49 /* The name of the usual type of MIPS processor that is in the target
  50    system.  */
  51
  52 #define DEFAULT_MIPS_TYPE "generic"
  53
  54 /* Return non-zero if PC points to an instruction which will cause a step
  55    to execute both the instruction at PC and an instruction at PC+4.  */
  56 extern int mips_step_skips_delay (CORE_ADDR);
  57 #define STEP_SKIPS_DELAY_P (1)
  58 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  59
  60 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  61    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  62    real way to know how big a register is.  */
  63
  64 #define REGISTER_SIZE 4
  65
  66 /* The size of a register.  This is predefined in tm-mips64.h.  We
  67    can't use REGISTER_SIZE because that is used for various other
  68    things.  */
  69
  70 #ifndef MIPS_REGSIZE
  71 #define MIPS_REGSIZE 4
  72 #endif
  73
  74 /* Number of machine registers */
  75
  76 #ifndef NUM_REGS
  77 #define NUM_REGS 90
  78 #endif
  79
  80 /* Given the register index, return the name of the corresponding
  81    register. */
  82 extern const char *mips_register_name (int regnr);
  83 #define REGISTER_NAME(i) mips_register_name (i)
  84
  85 /* Initializer for an array of names of registers.
  86    There should be NUM_REGS strings in this initializer.  */
  87
  88 #ifndef MIPS_REGISTER_NAMES
  89 #define MIPS_REGISTER_NAMES     \
  90     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
  91         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
  92         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
  93         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
  94         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
  95         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
  96         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
  97         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
  98         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
  99         "fsr",  "fir",  "fp",   "", \
 100         "",     "",     "",     "",     "",     "",     "",     "", \
 101         "",     "",     "",     "",     "",     "",     "",     "", \
 102     }
 103 #endif
 104
 105 /* Register numbers of various important registers.
 106    Note that some of these values are "real" register numbers,
 107    and correspond to the general registers of the machine,
 108    and some are "phony" register numbers which are too large
 109    to be actual register numbers as far as the user is concerned
 110    but do serve to get the desired values when passed to read_register.  */
 111
 112 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 113 #define V0_REGNUM 2             /* Function integer return value */
 114 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 115 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 116 #define SP_REGNUM 29            /* Contains address of top of stack */
 117 #define RA_REGNUM 31            /* Contains return address value */
 118 #define PS_REGNUM 32            /* Contains processor status */
 119 #define HI_REGNUM 34            /* Multiple/divide temp */
 120 #define LO_REGNUM 33            /* ... */
 121 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 122 #define CAUSE_REGNUM 36         /* describes last exception */
 123 #define PC_REGNUM 37            /* Contains program counter */
 124 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 125 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 126 #define FCRCS_REGNUM 70         /* FP control/status */
 127 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 128 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 129 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 130 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 131 #define PRID_REGNUM 89          /* Processor ID */
 132 #define LAST_EMBED_REGNUM 89    /* Last one */
 133
 134 /* Total amount of space needed to store our copies of the machine's
 135    register state, the array `registers'.  */
 136
 137 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 138
 139 /* Index within `registers' of the first byte of the space for
 140    register N.  */
 141
 142 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 143
 144 /* Return the GDB type object for the "standard" data type of data in
 145    register N.  */
 146
 147 #ifndef REGISTER_VIRTUAL_TYPE
 148 #define REGISTER_VIRTUAL_TYPE(N) \
 149         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 150          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 151          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 152          : builtin_type_int)
 153 #endif
 154
 155 /* All mips targets store doubles in a register pair with the least
 156    significant register in the lower numbered register.
 157    If the target is big endian, double register values need conversion
 158    between memory and register formats.  */
 159
 160 extern void mips_register_convert_to_type (int regnum,
 161                                            struct type *type,
 162                                            char *buffer);
 163 extern void mips_register_convert_from_type (int regnum,
 164                                              struct type *type,
 165                                              char *buffer);
 166
 167 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)       \
 168   mips_register_convert_to_type ((n), (type), (buffer))
 169
 170 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)     \
 171   mips_register_convert_from_type ((n), (type), (buffer))
 172
 173 \f
 174 /* Describe the pointer in each stack frame to the previous stack frame
 175    (its caller).  */
 176
 177 /* FRAME_CHAIN takes a frame's nominal address
 178    and produces the frame's chain-pointer. */
 179
 180 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 181 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 182
 183 /* Define other aspects of the stack frame.  */
 184
 185
 186 /* A macro that tells us whether the function invocation represented
 187    by FI does not have a frame on the stack associated with it.  If it
 188    does not, FRAMELESS is set to 1, else 0.  */
 189 /* We handle this differently for mips, and maybe we should not */
 190
 191 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 192
 193 /* Saved Pc.  */
 194
 195 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 196 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 197
 198 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 199
 200 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 201
 202 /* Return number of args passed to a frame.
 203    Can return -1, meaning no way to tell.  */
 204
 205 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 206 extern int mips_frame_num_args (struct frame_info *);
 207
 208 /* Return number of bytes at start of arglist that are not really args.  */
 209
 210 #define FRAME_ARGS_SKIP 0
 211
 212 \f
 213
 214 /* Things needed for making the inferior call functions.  */
 215
 216 /* Stack must be aligned on 32-bit boundaries when synthesizing
 217    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 218    handle it. */
 219
 220 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 221 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 222
 223 /* Push an empty stack frame, to record the current PC, etc.  */
 224
 225 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 226 extern void mips_push_dummy_frame (void);
 227
 228 /* Discard from the stack the innermost frame, restoring all registers.  */
 229
 230 #define POP_FRAME               mips_pop_frame()
 231 extern void mips_pop_frame (void);
 232
 233 #define CALL_DUMMY_START_OFFSET (0)
 234
 235 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 236
 237 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 238    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 239    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 240    will be ignored.  */
 241 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 242     write_register(T9_REGNUM, fun)
 243
 244 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 245 extern CORE_ADDR mips_call_dummy_address (void);
 246
 247 /* Special symbol found in blocks associated with routines.  We can hang
 248    mips_extra_func_info_t's off of this.  */
 249
 250 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 251 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 252
 253 /* Specific information about a procedure.
 254    This overlays the MIPS's PDR records,
 255    mipsread.c (ab)uses this to save memory */
 256
 257 typedef struct mips_extra_func_info
 258   {
 259     long numargs;               /* number of args to procedure (was iopt) */
 260     bfd_vma high_addr;          /* upper address bound */
 261     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 262     PDR pdr;                    /* Procedure descriptor record */
 263   }
 264  *mips_extra_func_info_t;
 265
 266 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 267 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 268   mips_init_extra_frame_info(fromleaf, fci)
 269
 270 extern void mips_print_extra_frame_info (struct frame_info *frame);
 271 #define PRINT_EXTRA_FRAME_INFO(fi) \
 272   mips_print_extra_frame_info (fi)
 273
 274 /* It takes two values to specify a frame on the MIPS.
 275
 276    In fact, the *PC* is the primary value that sets up a frame.  The
 277    PC is looked up to see what function it's in; symbol information
 278    from that function tells us which register is the frame pointer
 279    base, and what offset from there is the "virtual frame pointer".
 280    (This is usually an offset from SP.)  On most non-MIPS machines,
 281    the primary value is the SP, and the PC, if needed, disambiguates
 282    multiple functions with the same SP.  But on the MIPS we can't do
 283    that since the PC is not stored in the same part of the frame every
 284    time.  This does not seem to be a very clever way to set up frames,
 285    but there is nothing we can do about that.  */
 286
 287 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 288 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 289
 290 /* Select the default mips disassembler */
 291
 292 #define TM_PRINT_INSN_MACH 0
 293
 294
 295 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 296 extern CORE_ADDR sigtramp_address, sigtramp_end;
 297 extern void fixup_sigtramp (void);
 298
 299 /* Defined in mips-tdep.c and used in remote-mips.c */
 300 extern char *mips_read_processor_type (void);
 301
 302 /* Functions for dealing with MIPS16 call and return stubs.  */
 303 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 304 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 305 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 306 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 307 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 308 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 309 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 310 extern int mips_ignore_helper (CORE_ADDR pc);
 311
 312 #ifndef TARGET_MIPS
 313 #define TARGET_MIPS
 314 #endif
 315
 316 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 317 #define MIPS_INSTLEN 4          /* Length of an instruction */
 318 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 319 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 320 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 321
 322 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 323    macros to test, set, or clear bit 0 of addresses.  */
 324 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 325 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 326 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 327
 328 #endif /* TM_MIPS_H */
 329
 330 /* Macros for setting and testing a bit in a minimal symbol that
 331    marks it as 16-bit function.  The MSB of the minimal symbol's
 332    "info" field is used for this purpose. This field is already
 333    being used to store the symbol size, so the assumption is
 334    that the symbol size cannot exceed 2^31.
 335
 336    ELF_MAKE_MSYMBOL_SPECIAL
 337    tests whether an ELF symbol is "special", i.e. refers
 338    to a 16-bit function, and sets a "special" bit in a
 339    minimal symbol to mark it as a 16-bit function
 340    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 341    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 342    the "info" field with the "special" bit masked out
 343  */
 344
 345 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 346  { \
 347   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 348     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 349     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 350   } \
 351  }
 352
 353 #define MSYMBOL_IS_SPECIAL(msym) \
 354   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 355 #define MSYMBOL_SIZE(msym) \
 356   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 357
 358
 359 /* Command to set the processor type. */
 360 extern void mips_set_processor_type_command (char *, int);
 361
 362
 363 /* Single step based on where the current instruction will take us.  */
 364 extern void mips_software_single_step (enum target_signal, int);