gdb/config/mn10300/tm-mn10300.h

   1 /* Parameters for execution on a Matsushita mn10300 processor.
   2    Copyright 1996, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4
   5    Contributed by Geoffrey Noer <noer@cygnus.com>
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #define GDB_MULTI_ARCH 1
  25
  26 /* The mn10300 is little endian.  */
  27 #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
  28
  29 /* All registers are 32bits (phew!).  */
  30 #if !GDB_MULTI_ARCH
  31 #define REGISTER_SIZE 4
  32 #define MAX_REGISTER_RAW_SIZE 4
  33 #define NUM_REGS 32
  34 #endif
  35
  36 #if !GDB_MULTI_ARCH
  37 #define REGISTER_VIRTUAL_TYPE(REG) builtin_type_int
  38 #endif
  39
  40 #if !GDB_MULTI_ARCH
  41 #define REGISTER_BYTE(REG) ((REG) * 4)
  42 #define REGISTER_VIRTUAL_SIZE(REG) 4
  43 #define REGISTER_RAW_SIZE(REG) 4
  44 #endif
  45
  46 #define D0_REGNUM 0
  47 #define D2_REGNUM 2
  48 #define D3_REGNUM 3
  49 #define A0_REGNUM 4
  50 #define A2_REGNUM 6
  51 #define A3_REGNUM 7
  52 #define SP_REGNUM 8
  53 #define PC_REGNUM 9
  54 #define MDR_REGNUM 10
  55 #define PSW_REGNUM 11
  56 #define LIR_REGNUM 12
  57 #define LAR_REGNUM 13
  58 #define MDRQ_REGNUM 14
  59 #define E0_REGNUM 15
  60 #define MCRH_REGNUM 26
  61 #define MCRL_REGNUM 27
  62 #define MCVF_REGNUM 28
  63
  64 enum movm_register_bits {
  65   movm_exother_bit = 0x01,
  66   movm_exreg1_bit  = 0x02,
  67   movm_exreg0_bit  = 0x04,
  68   movm_other_bit   = 0x08,
  69   movm_a3_bit      = 0x10,
  70   movm_a2_bit      = 0x20,
  71   movm_d3_bit      = 0x40,
  72   movm_d2_bit      = 0x80
  73 };