gdb/config/pa/nm-hppab.h

   1 /* HPPA PA-RISC machine native support for BSD, for GDB.
   2    Copyright 1991, 1992 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
  19
  20 #define U_REGS_OFFSET 0
  21
  22 #define KERNEL_U_ADDR 0
  23
  24 /* What a coincidence! */
  25 #define REGISTER_U_ADDR(addr, blockend, regno)                          \
  26 { addr = (int)(blockend) + REGISTER_BYTE (regno);}
  27
  28 /* 3rd argument to ptrace is supposed to be a caddr_t.  */
  29
  30 #define PTRACE_ARG3_TYPE caddr_t
  31
  32 /* HPUX 8.0, in its infinite wisdom, has chosen to prototype ptrace
  33    with five arguments, so programs written for normal ptrace lose.  */
  34 #define FIVE_ARG_PTRACE
  35
  36
  37 /* This macro defines the register numbers (from REGISTER_NAMES) that
  38    are effectively unavailable to the user through ptrace().  It allows
  39    us to include the whole register set in REGISTER_NAMES (inorder to
  40    better support remote debugging).  If it is used in
  41    fetch/store_inferior_registers() gdb will not complain about I/O errors
  42    on fetching these registers.  If all registers in REGISTER_NAMES
  43    are available, then return false (0).  */
  44
  45 #define CANNOT_STORE_REGISTER(regno)            \
  46                    ((regno) == 0) ||     \
  47                    ((regno) == PCSQ_HEAD_REGNUM) || \
  48                    ((regno) >= PCSQ_TAIL_REGNUM && (regno) < IPSW_REGNUM) ||  \
  49                    ((regno) > IPSW_REGNUM && (regno) < FP4_REGNUM)
  50
  51 /* fetch_inferior_registers is in hppab-nat.c.  */
  52 #define FETCH_INFERIOR_REGISTERS
  53
  54 /* attach/detach works to some extent under BSD and HPUX.  So long
  55    as the process you're attaching to isn't blocked waiting on io,
  56    blocked waiting on a signal, or in a system call things work
  57    fine.  (The problems in those cases are related to the fact that
  58    the kernel can't provide complete register information for the
  59    target process...  Which really pisses off GDB.)  */
  60
  61 #define ATTACH_DETACH
  62
  63 /* The PA-BSD kernel has support for using the data memory break bit
  64    to implement fast watchpoints.
  65
  66    Watchpoints on the PA act much like traditional page protection
  67    schemes, but with some notable differences.
  68
  69    First, a special bit in the page table entry is used to cause
  70    a trap when a specific page is written to.  This avoids having
  71    to overload watchpoints on the page protection bits.  This makes
  72    it possible for the kernel to easily decide if a trap was caused
  73    by a watchpoint or by the user writing to protected memory and can
  74    signal the user program differently in each case.
  75
  76    Second, the PA has a bit in the processor status word which causes
  77    data memory breakpoints (aka watchpoints) to be disabled for a single
  78    instruction.  This bit can be used to avoid the overhead of unprotecting
  79    and reprotecting pages when it becomes necessary to step over a watchpoint.
  80
  81
  82    When the kernel receives a trap indicating a write to a page which
  83    is being watched, the kernel performs a couple of simple actions.  First
  84    is sets the magic "disable memory breakpoint" bit in the processor
  85    status word, it then sends a SIGTRAP to the process which caused the
  86    trap.
  87
  88    GDB will take control and catch the signal for the inferior.  GDB then
  89    examines the PSW-X bit to determine if the SIGTRAP was caused by a
  90    watchpoint firing.  If so GDB single steps the inferior over the
  91    instruction which caused the watchpoint to trigger (note because the
  92    kernel disabled the data memory break bit for one instruction no trap
  93    will be taken!).  GDB will then determines the appropriate action to
  94    take.  (this may include restarting the inferior if the watchpoint
  95    fired because of a write to an address on the same page as a watchpoint,
  96    but no write to the watched address occured).  */
  97
  98 /* The PA can watch any number of locations, there's no need for it to reject
  99    anything (generic routines already check that all intermediates are
 100    in memory).  */
 101 #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
 102         ((type) == bp_hardware_watchpoint)
 103
 104 /* When a hardware watchpoint fires off the PC will be left at the
 105    instruction which caused the watchpoint.  It will be necessary for
 106    GDB to step over the watchpoint.
 107
 108    On a PA running BSD, it is trivial to identify when it will be
 109    necessary to step over a hardware watchpoint as we can examine
 110    the PSW-X bit.  If the bit is on, then we trapped because of a
 111    watchpoint, else we trapped for some other reason.  */
 112 #define STOPPED_BY_WATCHPOINT(W) \
 113   ((W).kind == TARGET_WAITKIND_STOPPED \
 114    && (W).value.sig == TARGET_SIGNAL_TRAP \
 115    && ((int) read_register (IPSW_REGNUM) & 0x00100000))
 116
 117 /* The PA can single step over a watchpoint if the kernel has set the
 118    "X" bit in the processor status word (disable data memory breakpoint
 119    for one instruction).
 120
 121    The kernel will always set this bit before notifying the inferior
 122    that it hit a watchpoint.  Thus, the inferior can single step over
 123    the instruction which caused the watchpoint to fire.  This avoids
 124    the traditional need to disable the watchpoint, step the inferior,
 125    then enable the watchpoint again.  */
 126 #define HAVE_STEPPABLE_WATCHPOINT
 127
 128 /* Use these macros for watchpoint insertion/deletion.  */
 129 /* type can be 0: write watch, 1: read watch, 2: access watch (read/write) */
 130 #define target_insert_watchpoint(addr, len, type) hppa_set_watchpoint (addr, len, 1)
 131 #define target_remove_watchpoint(addr, len, type) hppa_set_watchpoint (addr, len, 0)