1 /* Parameters for execution on an HP PA-RISC machine running OSF1, for GDB.
2 Contributed by the Center for Software Science at the
3 University of Utah (pa-gdb-bugs@cs.utah.edu). */
5 /* Define offsets to access CPROC stack when it does not have
8 #define MACHINE_CPROC_SP_OFFSET 20
9 #define MACHINE_CPROC_PC_OFFSET 16
10 #define MACHINE_CPROC_FP_OFFSET 12
13 * Software defined PSW masks.
15 #define PSW_SS 0x10000000 /* Kernel managed single step */
17 /* Thread flavors used in re-setting the T bit.
18 * @@ this is also bad for cross debugging.
20 #define TRACE_FLAVOR HP800_THREAD_STATE
21 #define TRACE_FLAVOR_SIZE HP800_THREAD_STATE_COUNT
22 #define TRACE_SET(x,state) \
23 ((struct hp800_thread_state *)state)->cr22 |= PSW_SS
24 #define TRACE_CLEAR(x,state) \
25 ((((struct hp800_thread_state *)state)->cr22 &= ~PSW_SS), 1)
27 /* For OSF1 (Should be close if not identical to BSD, but I haven't
30 The signal context structure pointer is always saved at the base
33 We get the PC & SP directly from the sigcontext structure itself.
34 For other registers we have to dive in a little deeper:
36 The hardware save state pointer is at offset 0x10 within the
37 signal context structure.
39 Within the hardware save state, registers are found in the same order
40 as the register numbers in GDB. */
42 #define FRAME_SAVED_PC_IN_SIGTRAMP(FRAME, TMP) \
44 *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \
45 *(TMP) = read_memory_integer (*(TMP) + 0x18, 4); \
48 #define FRAME_BASE_BEFORE_SIGTRAMP(FRAME, TMP) \
50 *(TMP) = read_memory_integer ((FRAME)->frame + 0x4, 4); \
51 *(TMP) = read_memory_integer (*(TMP) + 0x8, 4); \
54 #define FRAME_FIND_SAVED_REGS_IN_SIGTRAMP(FRAME, FSR) \
58 TMP = read_memory_integer ((FRAME)->frame + 0x4, 4); \
59 TMP = read_memory_integer (TMP + 0x10, 4); \
60 for (i = 0; i < NUM_REGS; i++) \
63 (FSR)->regs[SP_REGNUM] = read_memory_integer (TMP + SP_REGNUM * 4, 4); \
65 (FSR)->regs[i] = TMP + i * 4; \
69 /* OSF1 does not need the pc space queue restored. */
70 #define NO_PC_SPACE_QUEUE_RESTORE
72 /* The mach kernel uses the recovery counter to implement single
73 stepping. While this greatly simplifies the kernel support
74 necessary for single stepping, it unfortunately does the wrong
75 thing in the presense of a nullified instruction (gives control
76 back two insns after the nullifed insn). This is an artifact
77 of the HP architecture (recovery counter doesn't tick for
80 Do our best to avoid losing in such situations. */
81 #define INSTRUCTION_NULLIFIED \
83 int ipsw = (int)read_register(IPSW_REGNUM); \
86 int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \
87 write_register(PCOQ_HEAD_REGNUM, pcoqt); \
88 write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \
89 write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \
94 /* It's mostly just the common stuff. */
96 #include "pa/tm-hppa.h"
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