gdb/config/sparc/tm-sp64.h

   1 /* Target machine sub-parameters for SPARC64, for GDB, the GNU debugger.
   2    This is included by other tm-*.h files to define SPARC64 cpu-related info.
   3    Copyright 1994, 1995 Free Software Foundation, Inc.
   4    This is (obviously) based on the SPARC Vn (n<9) port.
   5    Contributed by Doug Evans (dje@cygnus.com).
   6
   7 This file is part of GDB.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #define GDB_TARGET_IS_SPARC64
  24
  25 /* Need to define this so gdb will know what to do with long long's.
  26    Defining FORCE_LONG_LONG is incorrect (as of 940731) because that
  27    doesn't work for BFD64 targets.  */
  28
  29 #define CC_HAS_LONG_LONG
  30
  31 #include "sparc/tm-sparc.h"
  32
  33 /* Stack has strict alignment.  */
  34
  35 #undef  STACK_ALIGN
  36 #define STACK_ALIGN(ADDR) (((ADDR)+15)&-16)
  37
  38 /* Number of machine registers.  */
  39
  40 #undef  NUM_REGS
  41 #define NUM_REGS 125
  42
  43 /* Initializer for an array of names of registers.
  44    There should be NUM_REGS strings in this initializer.  */
  45 /* Some of these registers are only accessible from priviledged mode.
  46    They are here for kernel debuggers, etc.  */
  47 /* FIXME: icc and xcc are currently considered separate registers.
  48    This may have to change and consider them as just one (ccr).
  49    Let's postpone this as long as we can.  It's nice to be able to set
  50    them individually.  */
  51 /* FIXME: fcc0-3 are currently separate, even though they are also part of
  52    fsr.  May have to remove them but let's postpone this as long as
  53    possible.  It's nice to be able to set them individually.  */
  54 /* FIXME: Whether to include f33, f35, etc. here is not clear.
  55    There are advantages and disadvantages.  */
  56
  57 #undef  REGISTER_NAMES
  58 #define REGISTER_NAMES  \
  59 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",       \
  60   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",       \
  61   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",       \
  62   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",       \
  63                                                                 \
  64   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",               \
  65   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",         \
  66   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",       \
  67   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",       \
  68   "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",       \
  69   "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",       \
  70                                                                 \
  71   "pc", "npc", "ccr", "fsr", "fprs", "y", "asi",                \
  72   "ver", "tick", "pil", "pstate",                               \
  73   "tstate", "tba", "tl", "tt", "tpc", "tnpc", "wstate",         \
  74   "cwp", "cansave", "canrestore", "cleanwin", "otherwin",       \
  75   "asr16", "asr17", "asr18", "asr19", "asr20", "asr21",         \
  76   "asr22", "asr23", "asr24", "asr25", "asr26", "asr27",         \
  77   "asr28", "asr29", "asr30", "asr31",                           \
  78   /* These are here at the end to simplify removing them if we have to.  */ \
  79   "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"                  \
  80 }
  81
  82 /* Register numbers of various important registers.
  83    Note that some of these values are "real" register numbers,
  84    and correspond to the general registers of the machine,
  85    and some are "phony" register numbers which are too large
  86    to be actual register numbers as far as the user is concerned
  87    but do serve to get the desired values when passed to read_register.  */
  88
  89 #if 0 /* defined in tm-sparc.h, replicated for doc purposes */
  90 #define G0_REGNUM 0             /* %g0 */
  91 #define G1_REGNUM 1             /* %g1 */
  92 #define O0_REGNUM 8             /* %o0 */
  93 #define SP_REGNUM 14            /* Contains address of top of stack, \
  94                                    which is also the bottom of the frame.  */
  95 #define RP_REGNUM 15            /* Contains return address value, *before* \
  96                                    any windows get switched.  */
  97 #define O7_REGNUM 15            /* Last local reg not saved on stack frame */
  98 #define L0_REGNUM 16            /* First local reg that's saved on stack frame
  99                                    rather than in machine registers */
 100 #define I0_REGNUM 24            /* %i0 */
 101 #define FP_REGNUM 30            /* Contains address of executing stack frame */
 102 #define I7_REGNUM 31            /* Last local reg saved on stack frame */
 103 #define FP0_REGNUM 32           /* Floating point register 0 */
 104 #endif
 105
 106 #define FP_MAX_REGNUM 80        /* 1 + last fp reg number */
 107
 108 /* #undef v8 misc. regs */
 109
 110 #undef Y_REGNUM
 111 #undef PS_REGNUM
 112 #undef WIM_REGNUM
 113 #undef TBR_REGNUM
 114 #undef PC_REGNUM
 115 #undef NPC_REGNUM
 116 #undef FPS_REGNUM
 117 #undef CPS_REGNUM
 118
 119 /* v9 misc. and priv. regs */
 120
 121 #define C0_REGNUM FP_MAX_REGNUM                 /* Start of control registers */
 122 #define PC_REGNUM (C0_REGNUM + 0)               /* Current PC */
 123 #define NPC_REGNUM (C0_REGNUM + 1)              /* Next PC */
 124 #define CCR_REGNUM (C0_REGNUM + 2)              /* Condition Code Register (%xcc,%icc) */
 125 #define FSR_REGNUM (C0_REGNUM + 3)              /* Floating Point State */
 126 #define FPRS_REGNUM (C0_REGNUM + 4)             /* Floating Point Registers State */
 127 #define Y_REGNUM (C0_REGNUM + 5)                /* Temp register for multiplication, etc.  */
 128 #define ASI_REGNUM (C0_REGNUM + 6)              /* Alternate Space Identifier */
 129 #define VER_REGNUM (C0_REGNUM + 7)              /* Version register */
 130 #define TICK_REGNUM (C0_REGNUM + 8)             /* Tick register */
 131 #define PIL_REGNUM (C0_REGNUM + 9)              /* Processor Interrupt Level */
 132 #define PSTATE_REGNUM (C0_REGNUM + 10)          /* Processor State */
 133 #define TSTATE_REGNUM (C0_REGNUM + 11)          /* Trap State */
 134 #define TBA_REGNUM (C0_REGNUM + 12)             /* Trap Base Address */
 135 #define TL_REGNUM (C0_REGNUM + 13)              /* Trap Level */
 136 #define TT_REGNUM (C0_REGNUM + 14)              /* Trap Type */
 137 #define TPC_REGNUM (C0_REGNUM + 15)             /* Trap pc */
 138 #define TNPC_REGNUM (C0_REGNUM + 16)            /* Trap npc */
 139 #define WSTATE_REGNUM (C0_REGNUM + 17)          /* Window State */
 140 #define CWP_REGNUM (C0_REGNUM + 18)             /* Current Window Pointer */
 141 #define CANSAVE_REGNUM (C0_REGNUM + 19)         /* Savable Windows */
 142 #define CANRESTORE_REGNUM (C0_REGNUM + 20)      /* Restorable Windows */
 143 #define CLEANWIN_REGNUM (C0_REGNUM + 21)        /* Clean Windows */
 144 #define OTHERWIN_REGNUM (C0_REGNUM + 22)        /* Other Windows */
 145 #define ASR_REGNUM(n) (C0_REGNUM+(23-16)+(n))   /* Ancillary State Register
 146                                                    (n = 16...31) */
 147 #define ICC_REGNUM (C0_REGNUM + 39)             /* 32 bit condition codes */
 148 #define XCC_REGNUM (C0_REGNUM + 40)             /* 64 bit condition codes */
 149 #define FCC0_REGNUM (C0_REGNUM + 41)            /* fp cc reg 0 */
 150 #define FCC1_REGNUM (C0_REGNUM + 42)            /* fp cc reg 1 */
 151 #define FCC2_REGNUM (C0_REGNUM + 43)            /* fp cc reg 2 */
 152 #define FCC3_REGNUM (C0_REGNUM + 44)            /* fp cc reg 3 */
 153
 154 /* Total amount of space needed to store our copies of the machine's
 155    register state, the array `registers'.
 156    Some of the registers aren't 64 bits, but it's a lot simpler just to assume
 157    they all are (since most of them are).  */
 158 #undef  REGISTER_BYTES
 159 #define REGISTER_BYTES (32*8+32*8+45*8)
 160
 161 /* Index within `registers' of the first byte of the space for
 162    register N.  */
 163 #undef  REGISTER_BYTE
 164 #define REGISTER_BYTE(N) \
 165   ((N) < 32 ? (N)*8                             \
 166    : (N) < 64 ? 32*8 + ((N)-32)*4               \
 167    : (N) < C0_REGNUM ? 32*8 + 32*4 + ((N)-64)*8 \
 168    : 64*8 + ((N)-C0_REGNUM)*8)
 169
 170 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 171    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 172    real way to know how big a register is.  */
 173
 174 #undef  REGISTER_SIZE
 175 #define REGISTER_SIZE 8
 176
 177 /* Number of bytes of storage in the actual machine representation
 178    for register N.  */
 179 /* ??? It's not clear whether we want to return 4 or 8 for fp regs.  */
 180
 181 #undef  REGISTER_RAW_SIZE
 182 #define REGISTER_RAW_SIZE(N) 8
 183
 184 /* Number of bytes of storage in the program's representation
 185    for register N.  */
 186
 187 #undef  REGISTER_VIRTUAL_SIZE
 188 #define REGISTER_VIRTUAL_SIZE(N) 8
 189
 190 /* Largest value REGISTER_RAW_SIZE can have.  */
 191 /* tm-sparc.h defines this as 8, but play it safe.  */
 192
 193 #undef  MAX_REGISTER_RAW_SIZE
 194 #define MAX_REGISTER_RAW_SIZE 8
 195
 196 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 197 /* tm-sparc.h defines this as 8, but play it safe.  */
 198
 199 #undef  MAX_REGISTER_VIRTUAL_SIZE
 200 #define MAX_REGISTER_VIRTUAL_SIZE 8
 201
 202 /* Return the GDB type object for the "standard" data type
 203    of data in register N.  */
 204
 205 #undef  REGISTER_VIRTUAL_TYPE
 206 #define REGISTER_VIRTUAL_TYPE(N) \
 207  ((N) < 32 ? builtin_type_long_long : (N) < 80 ? builtin_type_float : \
 208   builtin_type_long_long)
 209
 210 /* We use to support both 32 bit and 64 bit pointers.
 211    We can't anymore because TARGET_PTR_BIT must now be a constant.  */
 212 #undef  TARGET_PTR_BIT
 213 #define TARGET_PTR_BIT 64
 214
 215 /* Does the specified function use the "struct returning" convention
 216    or the "value returning" convention?  The "value returning" convention
 217    almost invariably returns the entire value in registers.  The
 218    "struct returning" convention often returns the entire value in
 219    memory, and passes a pointer (out of or into the function) saying
 220    where the value (is or should go).
 221
 222    Since this sometimes depends on whether it was compiled with GCC,
 223    this is also an argument.  This is used in call_function to build a
 224    stack, and in value_being_returned to print return values.
 225
 226    On sparc64, all structs are returned via a pointer.  */
 227
 228 #undef  USE_STRUCT_CONVENTION
 229 #define USE_STRUCT_CONVENTION(gcc_p, type) 1
 230
 231 /* Store the address of the place in which to copy the structure the
 232    subroutine will return.  This is called from call_function. */
 233 /* FIXME: V9 uses %o0 for this.  */
 234
 235 #undef  STORE_STRUCT_RETURN
 236 #define STORE_STRUCT_RETURN(ADDR, SP) \
 237   { target_write_memory ((SP)+(16*8), (char *)&(ADDR), 8); }
 238
 239 /* Return number of bytes at start of arglist that are not really args.  */
 240
 241 #undef  FRAME_ARGS_SKIP
 242 #define FRAME_ARGS_SKIP 136
 243 \f
 244 /* We need two arguments (in general) to the "info frame" command.
 245    Note that the definition of this macro implies that there exists a
 246    function "setup_arbitrary_frame" in sparc-tdep.c */
 247
 248 #undef  SETUP_ARBITRARY_FRAME           /*FIXME*/
 249 #undef  FRAME_SPECIFICATION_DYADIC
 250 #define FRAME_SPECIFICATION_DYADIC
 251
 252 /* To print every pair of float registers as a double, we use this hook.
 253    We also print the condition code registers in a readable format
 254    (FIXME: can expand this to all control regs).  */
 255
 256 #undef  PRINT_REGISTER_HOOK
 257 #define PRINT_REGISTER_HOOK(regno)      \
 258   sparc_print_register_hook (regno)
 259
 260 /* Offsets into jmp_buf.
 261    FIXME: This was borrowed from the v8 stuff and will probably have to change
 262    for v9.  */
 263
 264 #define JB_ELEMENT_SIZE 8       /* Size of each element in jmp_buf */
 265
 266 #define JB_ONSSTACK 0
 267 #define JB_SIGMASK 1
 268 #define JB_SP 2
 269 #define JB_PC 3
 270 #define JB_NPC 4
 271 #define JB_PSR 5
 272 #define JB_G1 6
 273 #define JB_O0 7
 274 #define JB_WBCNT 8
 275
 276 /* Figure out where the longjmp will land.  We expect that we have just entered
 277    longjmp and haven't yet setup the stack frame, so the args are still in the
 278    output regs.  %o0 (O0_REGNUM) points at the jmp_buf structure from which we
 279    extract the pc (JB_PC) that we will land at.  The pc is copied into ADDR.
 280    This routine returns true on success */
 281
 282 extern int
 283 get_longjmp_target PARAMS ((CORE_ADDR *));
 284
 285 #define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)