gdb/config/sparc/tm-sparclite.h

   1 /* Macro definitions for GDB for a Fujitsu SPARClite.
   2    Copyright 1993 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #define TARGET_SPARCLITE 1
  21
  22 #include "sparc/tm-sparc.h"
  23
  24 /* Amount PC must be decremented by after a hardware instruction breakpoint.
  25    This is often the number of bytes in BREAKPOINT
  26    but not always.  */
  27
  28 #define DECR_PC_AFTER_HW_BREAK 4
  29
  30 #define FRAME_CHAIN_VALID_ALTERNATE
  31
  32 #undef NUM_REGS
  33 #define NUM_REGS 80
  34
  35 #undef REGISTER_BYTES
  36 #define REGISTER_BYTES (32*4+32*4+8*4+8*4)
  37
  38 #undef REGISTER_NAMES
  39 #define REGISTER_NAMES  \
  40 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",       \
  41   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",       \
  42   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",       \
  43   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",       \
  44                                                                 \
  45   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",       \
  46   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
  47   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",       \
  48   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",       \
  49                                                                 \
  50   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",        \
  51   "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }
  52
  53 #define DIA1_REGNUM 72          /* debug instr address register 1 */
  54 #define DIA2_REGNUM 73          /* debug instr address register 2 */
  55 #define DDA1_REGNUM 74          /* debug data address register 1 */
  56 #define DDA2_REGNUM 75          /* debug data address register 2 */
  57 #define DDV1_REGNUM 76          /* debug data value register 1 */
  58 #define DDV2_REGNUM 77          /* debug data value register 2 */
  59 #define DCR_REGNUM 78           /* debug control register */
  60 #define DSR_REGNUM 79           /* debug status regsiter */
  61
  62 #define TARGET_HW_BREAK_LIMIT 2
  63 #define TARGET_HW_WATCH_LIMIT 2
  64
  65 /* Enable watchpoint macro's */
  66
  67 #define TARGET_HAS_HARDWARE_WATCHPOINTS
  68
  69 #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
  70         sparclite_check_watch_resources (type, cnt, ot)
  71
  72 /* When a hardware watchpoint fires off the PC will be left at the
  73    instruction which caused the watchpoint.  It will be necessary for
  74    GDB to step over the watchpoint. ***
  75
  76 #define STOPPED_BY_WATCHPOINT(W) \
  77   ((W).kind == TARGET_WAITKIND_STOPPED \
  78    && (W).value.sig == TARGET_SIGNAL_TRAP \
  79    && ((int) read_register (IPSW_REGNUM) & 0x00100000))
  80 */
  81
  82 /* Use these macros for watchpoint insertion/deletion.  */
  83 #define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
  84 #define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
  85 #define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
  86 #define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
  87 #define target_stopped_data_address() sparclite_stopped_data_address()