gdb/config/sparc/tm-sparclite.h

   1 /* Macro definitions for GDB for a Fujitsu SPARClite.
   2    Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include "regcache.h"
  23
  24 #define TARGET_SPARCLITE 1      /* Still needed for non-multi-arch case */
  25
  26 #include "sparc/tm-sparc.h"
  27
  28 /* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
  29    at this time, because we have not figured out how to detect the
  30    sparclet target from the bfd structure.  */
  31
  32 /* Sparclite regs, for debugging purposes */
  33
  34 enum {
  35   DIA1_REGNUM = 72,             /* debug instr address register 1 */
  36   DIA2_REGNUM = 73,             /* debug instr address register 2 */
  37   DDA1_REGNUM = 74,             /* debug data address register 1 */
  38   DDA2_REGNUM = 75,             /* debug data address register 2 */
  39   DDV1_REGNUM = 76,             /* debug data value register 1 */
  40   DDV2_REGNUM = 77,             /* debug data value register 2 */
  41   DCR_REGNUM  = 78,             /* debug control register */
  42   DSR_REGNUM  = 79              /* debug status regsiter */
  43 };
  44
  45 /* overrides of tm-sparc.h */
  46
  47 #undef TARGET_BYTE_ORDER
  48
  49 /* Select the sparclite disassembler.  Slightly different instruction set from
  50    the V8 sparc.  */
  51
  52 #undef TM_PRINT_INSN_MACH
  53 #define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclite
  54
  55 /* Amount PC must be decremented by after a hardware instruction breakpoint.
  56    This is often the number of bytes in BREAKPOINT
  57    but not always.  */
  58
  59 #define DECR_PC_AFTER_HW_BREAK 4
  60
  61 #if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
  62 /*
  63  * The following defines must go away for MULTI_ARCH.
  64  */
  65
  66 #undef NUM_REGS
  67 #define NUM_REGS 80
  68
  69 #undef REGISTER_BYTES
  70 #define REGISTER_BYTES (32*4+32*4+8*4+8*4)
  71
  72 #undef REGISTER_NAMES
  73 #define REGISTER_NAMES  \
  74 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",       \
  75   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",       \
  76   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",       \
  77   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",       \
  78                                                                 \
  79   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",       \
  80   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
  81   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",       \
  82   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",       \
  83                                                                 \
  84   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",        \
  85   "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }
  86
  87 #define DIA1_REGNUM 72          /* debug instr address register 1 */
  88 #define DIA2_REGNUM 73          /* debug instr address register 2 */
  89 #define DDA1_REGNUM 74          /* debug data address register 1 */
  90 #define DDA2_REGNUM 75          /* debug data address register 2 */
  91 #define DDV1_REGNUM 76          /* debug data value register 1 */
  92 #define DDV2_REGNUM 77          /* debug data value register 2 */
  93 #define DCR_REGNUM 78           /* debug control register */
  94 #define DSR_REGNUM 79           /* debug status regsiter */
  95
  96 #endif /* GDB_MULTI_ARCH */
  97
  98 #define TARGET_HW_BREAK_LIMIT 2
  99 #define TARGET_HW_WATCH_LIMIT 2
 100
 101 /* Enable watchpoint macro's */
 102
 103 #define TARGET_HAS_HARDWARE_WATCHPOINTS
 104
 105 #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
 106         sparclite_check_watch_resources (type, cnt, ot)
 107
 108 /* When a hardware watchpoint fires off the PC will be left at the
 109    instruction which caused the watchpoint.  It will be necessary for
 110    GDB to step over the watchpoint. ***
 111
 112    #define STOPPED_BY_WATCHPOINT(W) \
 113    ((W).kind == TARGET_WAITKIND_STOPPED \
 114    && (W).value.sig == TARGET_SIGNAL_TRAP \
 115    && ((int) read_register (IPSW_REGNUM) & 0x00100000))
 116  */
 117
 118 /* Use these macros for watchpoint insertion/deletion.  */
 119 #define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
 120 #define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
 121 #define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
 122 #define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
 123 #define target_stopped_data_address() sparclite_stopped_data_address()