1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
38 #include "arch-utils.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
47 #include "cris-tdep.h"
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
54 /* There are 16 general registers. */
57 /* There are 16 special registers. */
60 /* CRISv32 has a pseudo PC register, not noted here. */
62 /* CRISv32 has 16 support registers. */
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
84 /* ABI related registers. */
92 /* Registers which happen to be common. */
97 /* CRISv10 et al. specific registers. */
109 /* CRISv32 specific registers. */
122 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
124 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
144 extern const struct cris_spec_reg cris_spec_regs
[];
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version
;
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid
= 0;
153 static const char cris_mode_normal
[] = "normal";
154 static const char cris_mode_guru
[] = "guru";
155 static const char *const cris_modes
[] = {
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi
= 1;
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
175 static const unsigned short sigtramp_code
[] =
177 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1
/* break 13 */
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
183 /* Note: same length as normal sigtramp code. */
185 static const unsigned short rt_sigtramp_code
[] =
187 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1
/* break 13 */
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
195 cris_sigtramp_start (struct frame_info
*this_frame
)
197 CORE_ADDR pc
= get_frame_pc (this_frame
);
198 gdb_byte buf
[SIGTRAMP_LEN
];
200 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
203 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
205 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
208 pc
-= SIGTRAMP_OFFSET1
;
209 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
213 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
223 cris_rt_sigtramp_start (struct frame_info
*this_frame
)
225 CORE_ADDR pc
= get_frame_pc (this_frame
);
226 gdb_byte buf
[SIGTRAMP_LEN
];
228 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
231 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
233 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
236 pc
-= SIGTRAMP_OFFSET1
;
237 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
241 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
251 cris_sigcontext_addr (struct frame_info
*this_frame
)
253 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
254 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
259 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
260 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
262 /* Look for normal sigtramp frame first. */
263 pc
= cris_sigtramp_start (this_frame
);
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
272 pc
= cris_rt_sigtramp_start (this_frame
);
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
283 error (_("Couldn't recognize signal trampoline."));
287 struct cris_unwind_cache
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
292 /* The frame's base, optionally used by the high-level debug info. */
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
302 /* From old frame_extra_info struct. */
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg
*saved_regs
;
310 static struct cris_unwind_cache
*
311 cris_sigtramp_frame_unwind_cache (struct frame_info
*this_frame
,
314 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
316 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
317 struct cris_unwind_cache
*info
;
323 return (struct cris_unwind_cache
*) (*this_cache
);
325 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
326 (*this_cache
) = info
;
327 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
329 /* Zero all fields. */
335 info
->uses_frame
= 0;
337 info
->leaf_function
= 0;
339 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
340 info
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
342 addr
= cris_sigcontext_addr (this_frame
);
344 /* Layout of the sigcontext struct:
347 unsigned long oldmask;
351 if (tdep
->cris_version
== 10)
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
355 for (i
= 0; i
<= 13; i
++)
356 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
358 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
359 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
360 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
365 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
366 = info
->saved_regs
[IRP_REGNUM
];
367 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
= addr
+ (24 * 4);
372 /* R0 to R13 are stored in order at offset (1 * 4) in
374 for (i
= 0; i
<= 13; i
++)
375 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
377 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
378 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
379 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
380 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
381 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
382 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
383 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
384 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
385 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
395 = info
->saved_regs
[ERP_REGNUM
];
397 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
405 cris_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
406 struct frame_id
*this_id
)
408 struct cris_unwind_cache
*cache
=
409 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
410 (*this_id
) = frame_id_build (cache
->base
, get_frame_pc (this_frame
));
413 /* Forward declaration. */
415 static struct value
*cris_frame_prev_register (struct frame_info
*this_frame
,
416 void **this_cache
, int regnum
);
417 static struct value
*
418 cris_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
419 void **this_cache
, int regnum
)
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
423 return cris_frame_prev_register (this_frame
, this_cache
, regnum
);
427 cris_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
428 struct frame_info
*this_frame
,
431 if (cris_sigtramp_start (this_frame
)
432 || cris_rt_sigtramp_start (this_frame
))
438 static const struct frame_unwind cris_sigtramp_frame_unwind
=
441 default_frame_unwind_stop_reason
,
442 cris_sigtramp_frame_this_id
,
443 cris_sigtramp_frame_prev_register
,
445 cris_sigtramp_frame_sniffer
449 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
450 struct frame_info
*this_frame
)
452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
456 if (tdep
->cris_mode
== cris_mode_guru
)
457 erp
= get_frame_register_unsigned (this_frame
, NRP_REGNUM
);
459 erp
= get_frame_register_unsigned (this_frame
, ERP_REGNUM
);
463 /* In delay slot - check if there's a breakpoint at the preceding
465 if (breakpoint_here_p (get_frame_address_space (this_frame
), erp
& ~0x1))
471 /* The instruction environment needed to find single-step breakpoints. */
474 struct instruction_environment
476 unsigned long reg
[NUM_GENREGS
];
477 unsigned long preg
[NUM_SPECREGS
];
478 unsigned long branch_break_address
;
479 unsigned long delay_slot_pc
;
480 unsigned long prefix_value
;
485 int delay_slot_pc_active
;
487 int disable_interrupt
;
488 enum bfd_endian byte_order
;
491 /* Machine-dependencies in CRIS for opcodes. */
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
501 /* Addressing modes. */
502 enum cris_addressing_modes
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
512 PREFIX_INDEX_MODE
= 2,
513 PREFIX_ASSIGN_MODE
= 3,
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE
= 2
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
522 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
523 SIGNED_EXTEND_BIT_MASK
= 0x2,
524 SIGNED_BYTE_MASK
= 0x80,
525 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
526 SIGNED_WORD_MASK
= 0x8000,
527 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
528 SIGNED_DWORD_MASK
= 0x80000000,
529 SIGNED_QUICK_VALUE_MASK
= 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
541 cris_get_operand2 (unsigned short insn
)
543 return ((insn
& 0xF000) >> 12);
547 cris_get_mode (unsigned short insn
)
549 return ((insn
& 0x0C00) >> 10);
553 cris_get_opcode (unsigned short insn
)
555 return ((insn
& 0x03C0) >> 6);
559 cris_get_size (unsigned short insn
)
561 return ((insn
& 0x0030) >> 4);
565 cris_get_operand1 (unsigned short insn
)
567 return (insn
& 0x000F);
570 /* Additional functions in order to handle opcodes. */
573 cris_get_quick_value (unsigned short insn
)
575 return (insn
& 0x003F);
579 cris_get_bdap_quick_offset (unsigned short insn
)
581 return (insn
& 0x00FF);
585 cris_get_branch_short_offset (unsigned short insn
)
587 return (insn
& 0x00FF);
591 cris_get_asr_shift_steps (unsigned long value
)
593 return (value
& 0x3F);
597 cris_get_clear_size (unsigned short insn
)
599 return ((insn
) & 0xC000);
603 cris_is_signed_extend_bit_on (unsigned short insn
)
605 return (((insn
) & 0x20) == 0x20);
609 cris_is_xflag_bit_on (unsigned short insn
)
611 return (((insn
) & 0x1000) == 0x1000);
615 cris_set_size_to_dword (unsigned short *insn
)
622 cris_get_signed_offset (unsigned short insn
)
624 return ((signed char) (insn
& 0x00FF));
627 /* Calls an op function given the op-type, working on the insn and the
629 static void cris_gdb_func (struct gdbarch
*, enum cris_op_type
, unsigned short,
632 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
633 struct gdbarch_list
*);
635 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
637 static void set_cris_version (char *ignore_args
, int from_tty
,
638 struct cmd_list_element
*c
);
640 static void set_cris_mode (char *ignore_args
, int from_tty
,
641 struct cmd_list_element
*c
);
643 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
644 struct cmd_list_element
*c
);
646 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
647 struct frame_info
*this_frame
,
648 struct cris_unwind_cache
*info
);
650 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
651 struct frame_info
*this_frame
,
652 struct cris_unwind_cache
*info
);
654 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
655 struct frame_info
*next_frame
);
657 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
658 struct frame_info
*next_frame
);
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
667 struct stack_item
*prev
;
671 static struct stack_item
*
672 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
674 struct stack_item
*si
= XNEW (struct stack_item
);
675 si
->data
= (gdb_byte
*) xmalloc (len
);
678 memcpy (si
->data
, contents
, len
);
682 static struct stack_item
*
683 pop_stack_item (struct stack_item
*si
)
685 struct stack_item
*dead
= si
;
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
698 static struct cris_unwind_cache
*
699 cris_frame_unwind_cache (struct frame_info
*this_frame
,
700 void **this_prologue_cache
)
702 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
703 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
704 struct cris_unwind_cache
*info
;
706 if ((*this_prologue_cache
))
707 return (struct cris_unwind_cache
*) (*this_prologue_cache
);
709 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
710 (*this_prologue_cache
) = info
;
711 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
713 /* Zero all fields. */
719 info
->uses_frame
= 0;
721 info
->leaf_function
= 0;
723 /* Prologue analysis does the rest... */
724 if (tdep
->cris_version
== 32)
725 crisv32_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
727 cris_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
736 cris_frame_this_id (struct frame_info
*this_frame
,
737 void **this_prologue_cache
,
738 struct frame_id
*this_id
)
740 struct cris_unwind_cache
*info
741 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
746 /* The FUNC is easy. */
747 func
= get_frame_func (this_frame
);
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base
= info
->prev_sp
;
756 id
= frame_id_build (base
, func
);
761 static struct value
*
762 cris_frame_prev_register (struct frame_info
*this_frame
,
763 void **this_prologue_cache
, int regnum
)
765 struct cris_unwind_cache
*info
766 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
767 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
774 static struct frame_id
775 cris_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
778 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
779 return frame_id_build (sp
, get_frame_pc (this_frame
));
783 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
791 cris_push_dummy_code (struct gdbarch
*gdbarch
,
792 CORE_ADDR sp
, CORE_ADDR funaddr
,
793 struct value
**args
, int nargs
,
794 struct type
*value_type
,
795 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
796 struct regcache
*regcache
)
798 /* Allocate space sufficient for a breakpoint. */
800 /* Store the address of that breakpoint */
802 /* CRIS always starts the call at the callee's entry point. */
808 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
809 struct regcache
*regcache
, CORE_ADDR bp_addr
,
810 int nargs
, struct value
**args
, CORE_ADDR sp
,
811 int struct_return
, CORE_ADDR struct_addr
)
813 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
817 struct stack_item
*si
= NULL
;
819 /* Push the return address. */
820 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
822 /* Are we returning a value using a structure return or a normal value
823 return? struct_addr is the address of the reserved space for the return
824 structure to be written on the stack. */
827 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
830 /* Now load as many as possible of the first arguments into registers,
831 and push the rest onto the stack. */
832 argreg
= ARG1_REGNUM
;
834 for (argnum
= 0; argnum
< nargs
; argnum
++)
841 len
= TYPE_LENGTH (value_type (args
[argnum
]));
842 val
= value_contents (args
[argnum
]);
844 /* How may registers worth of storage do we need for this argument? */
845 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
847 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
849 /* Data passed by value. Fits in available register(s). */
850 for (i
= 0; i
< reg_demand
; i
++)
852 regcache_cooked_write (regcache
, argreg
, val
);
857 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
859 /* Data passed by value. Does not fit in available register(s).
860 Use the register(s) first, then the stack. */
861 for (i
= 0; i
< reg_demand
; i
++)
863 if (argreg
<= ARG4_REGNUM
)
865 regcache_cooked_write (regcache
, argreg
, val
);
871 /* Push item for later so that pushed arguments
872 come in the right order. */
873 si
= push_stack_item (si
, val
, 4);
878 else if (len
> (2 * 4))
880 /* Data passed by reference. Push copy of data onto stack
881 and pass pointer to this copy as argument. */
882 sp
= (sp
- len
) & ~3;
883 write_memory (sp
, val
, len
);
885 if (argreg
<= ARG4_REGNUM
)
887 regcache_cooked_write_unsigned (regcache
, argreg
, sp
);
893 store_unsigned_integer (buf
, 4, byte_order
, sp
);
894 si
= push_stack_item (si
, buf
, 4);
899 /* Data passed by value. No available registers. Put it on
901 si
= push_stack_item (si
, val
, len
);
907 /* fp_arg must be word-aligned (i.e., don't += len) to match
908 the function prologue. */
909 sp
= (sp
- si
->len
) & ~3;
910 write_memory (sp
, si
->data
, si
->len
);
911 si
= pop_stack_item (si
);
914 /* Finally, update the SP register. */
915 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
920 static const struct frame_unwind cris_frame_unwind
=
923 default_frame_unwind_stop_reason
,
925 cris_frame_prev_register
,
927 default_frame_sniffer
931 cris_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
933 struct cris_unwind_cache
*info
934 = cris_frame_unwind_cache (this_frame
, this_cache
);
938 static const struct frame_base cris_frame_base
=
941 cris_frame_base_address
,
942 cris_frame_base_address
,
943 cris_frame_base_address
946 /* Frames information. The definition of the struct frame_info is
950 enum frame_type type;
954 If the compilation option -fno-omit-frame-pointer is present the
955 variable frame will be set to the content of R8 which is the frame
958 The variable pc contains the address where execution is performed
959 in the present frame. The innermost frame contains the current content
960 of the register PC. All other frames contain the content of the
961 register PC in the next frame.
963 The variable `type' indicates the frame's type: normal, SIGTRAMP
964 (associated with a signal handler), dummy (associated with a dummy
967 The variable return_pc contains the address where execution should be
968 resumed when the present frame has finished, the return address.
970 The variable leaf_function is 1 if the return address is in the register
971 SRP, and 0 if it is on the stack.
973 Prologue instructions C-code.
974 The prologue may consist of (-fno-omit-frame-pointer)
978 move.d sp,r8 move.d sp,r8
980 movem rY,[sp] movem rY,[sp]
981 move.S rZ,[r8-U] move.S rZ,[r8-U]
983 where 1 is a non-terminal function, and 2 is a leaf-function.
985 Note that this assumption is extremely brittle, and will break at the
986 slightest change in GCC's prologue.
988 If local variables are declared or register contents are saved on stack
989 the subq-instruction will be present with X as the number of bytes
990 needed for storage. The reshuffle with respect to r8 may be performed
991 with any size S (b, w, d) and any of the general registers Z={0..13}.
992 The offset U should be representable by a signed 8-bit value in all cases.
993 Thus, the prefix word is assumed to be immediate byte offset mode followed
994 by another word containing the instruction.
1003 Prologue instructions C++-code.
1004 Case 1) and 2) in the C-code may be followed by
1006 move.d r10,rS ; this
1010 move.S [r8+U],rZ ; P4
1012 if any of the call parameters are stored. The host expects these
1013 instructions to be executed in order to get the call parameters right. */
1015 /* Examine the prologue of a function. The variable ip is the address of
1016 the first instruction of the prologue. The variable limit is the address
1017 of the first instruction after the prologue. The variable fi contains the
1018 information in struct frame_info. The variable frameless_p controls whether
1019 the entire prologue is examined (0) or just enough instructions to
1020 determine that it is a prologue (1). */
1023 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1024 struct cris_unwind_cache
*info
)
1026 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1027 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1029 /* Present instruction. */
1030 unsigned short insn
;
1032 /* Next instruction, lookahead. */
1033 unsigned short insn_next
;
1036 /* Number of byte on stack used for local variables and movem. */
1039 /* Highest register number in a movem. */
1042 /* move.d r<source_register>,rS */
1043 short source_register
;
1048 /* This frame is with respect to a leaf until a push srp is found. */
1051 info
->leaf_function
= 1;
1054 /* Assume nothing on stack. */
1058 /* If we were called without a this_frame, that means we were called
1059 from cris_skip_prologue which already tried to find the end of the
1060 prologue through the symbol information. 64 instructions past current
1061 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1062 limit
= this_frame
? get_frame_pc (this_frame
) : pc
+ 64;
1064 /* Find the prologue instructions. */
1065 while (pc
> 0 && pc
< limit
)
1067 insn
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1071 /* push <reg> 32 bit instruction. */
1072 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1074 regno
= cris_get_operand2 (insn_next
);
1077 info
->sp_offset
+= 4;
1079 /* This check, meant to recognize srp, used to be regno ==
1080 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1081 if (insn_next
== 0xBE7E)
1085 info
->leaf_function
= 0;
1088 else if (insn_next
== 0x8FEE)
1093 info
->r8_offset
= info
->sp_offset
;
1097 else if (insn
== 0x866E)
1102 info
->uses_frame
= 1;
1106 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1107 && cris_get_mode (insn
) == 0x0000
1108 && cris_get_opcode (insn
) == 0x000A)
1113 info
->sp_offset
+= cris_get_quick_value (insn
);
1116 else if (cris_get_mode (insn
) == 0x0002
1117 && cris_get_opcode (insn
) == 0x000F
1118 && cris_get_size (insn
) == 0x0003
1119 && cris_get_operand1 (insn
) == gdbarch_sp_regnum (gdbarch
))
1121 /* movem r<regsave>,[sp] */
1122 regsave
= cris_get_operand2 (insn
);
1124 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1125 && ((insn
& 0x0F00) >> 8) == 0x0001
1126 && (cris_get_signed_offset (insn
) < 0))
1128 /* Immediate byte offset addressing prefix word with sp as base
1129 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1130 is between 64 and 128.
1131 movem r<regsave>,[sp=sp-<val>] */
1134 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1136 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1138 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1139 && cris_get_opcode (insn_next
) == 0x000F
1140 && cris_get_size (insn_next
) == 0x0003
1141 && cris_get_operand1 (insn_next
) == gdbarch_sp_regnum
1144 regsave
= cris_get_operand2 (insn_next
);
1148 /* The prologue ended before the limit was reached. */
1153 else if (cris_get_mode (insn
) == 0x0001
1154 && cris_get_opcode (insn
) == 0x0009
1155 && cris_get_size (insn
) == 0x0002)
1157 /* move.d r<10..13>,r<0..15> */
1158 source_register
= cris_get_operand1 (insn
);
1160 /* FIXME? In the glibc solibs, the prologue might contain something
1161 like (this example taken from relocate_doit):
1163 sub.d 0xfffef426,$r0
1164 which isn't covered by the source_register check below. Question
1165 is whether to add a check for this combo, or make better use of
1166 the limit variable instead. */
1167 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1169 /* The prologue ended before the limit was reached. */
1174 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1175 /* The size is a fixed-size. */
1176 && ((insn
& 0x0F00) >> 8) == 0x0001
1177 /* A negative offset. */
1178 && (cris_get_signed_offset (insn
) < 0))
1180 /* move.S rZ,[r8-U] (?) */
1181 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1183 regno
= cris_get_operand2 (insn_next
);
1184 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1185 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1186 && cris_get_opcode (insn_next
) == 0x000F)
1188 /* move.S rZ,[r8-U] */
1193 /* The prologue ended before the limit was reached. */
1198 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1199 /* The size is a fixed-size. */
1200 && ((insn
& 0x0F00) >> 8) == 0x0001
1201 /* A positive offset. */
1202 && (cris_get_signed_offset (insn
) > 0))
1204 /* move.S [r8+U],rZ (?) */
1205 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1207 regno
= cris_get_operand2 (insn_next
);
1208 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1209 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1210 && cris_get_opcode (insn_next
) == 0x0009
1211 && cris_get_operand1 (insn_next
) == regno
)
1213 /* move.S [r8+U],rZ */
1218 /* The prologue ended before the limit was reached. */
1225 /* The prologue ended before the limit was reached. */
1231 /* We only want to know the end of the prologue when this_frame and info
1232 are NULL (called from cris_skip_prologue i.e.). */
1233 if (this_frame
== NULL
&& info
== NULL
)
1238 info
->size
= info
->sp_offset
;
1240 /* Compute the previous frame's stack pointer (which is also the
1241 frame's ID's stack address), and this frame's base pointer. */
1242 if (info
->uses_frame
)
1245 /* The SP was moved to the FP. This indicates that a new frame
1246 was created. Get THIS frame's FP value by unwinding it from
1248 this_base
= get_frame_register_unsigned (this_frame
, CRIS_FP_REGNUM
);
1249 info
->base
= this_base
;
1250 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1252 /* The FP points at the last saved register. Adjust the FP back
1253 to before the first saved register giving the SP. */
1254 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1259 /* Assume that the FP is this frame's SP but with that pushed
1260 stack space added back. */
1261 this_base
= get_frame_register_unsigned (this_frame
,
1262 gdbarch_sp_regnum (gdbarch
));
1263 info
->base
= this_base
;
1264 info
->prev_sp
= info
->base
+ info
->size
;
1267 /* Calculate the addresses for the saved registers on the stack. */
1268 /* FIXME: The address calculation should really be done on the fly while
1269 we're analyzing the prologue (we only hold one regsave value as it is
1271 val
= info
->sp_offset
;
1273 for (regno
= regsave
; regno
>= 0; regno
--)
1275 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1279 /* The previous frame's SP needed to be computed. Save the computed
1281 trad_frame_set_value (info
->saved_regs
,
1282 gdbarch_sp_regnum (gdbarch
), info
->prev_sp
);
1284 if (!info
->leaf_function
)
1286 /* SRP saved on the stack. But where? */
1287 if (info
->r8_offset
== 0)
1289 /* R8 not pushed yet. */
1290 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1294 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1295 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1299 /* The PC is found in SRP (the actual register or located on the stack). */
1300 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1301 = info
->saved_regs
[SRP_REGNUM
];
1307 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1308 struct cris_unwind_cache
*info
)
1310 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1313 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1314 meant to be a full-fledged prologue scanner. It is only needed for
1315 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1317 * PLT stubs (library calls)
1319 * signal trampolines
1321 For those cases, it is assumed that there is no actual prologue; that
1322 the stack pointer is not adjusted, and (as a consequence) the return
1323 address is not pushed onto the stack. */
1325 /* We only want to know the end of the prologue when this_frame and info
1326 are NULL (called from cris_skip_prologue i.e.). */
1327 if (this_frame
== NULL
&& info
== NULL
)
1332 /* The SP is assumed to be unaltered. */
1333 this_base
= get_frame_register_unsigned (this_frame
,
1334 gdbarch_sp_regnum (gdbarch
));
1335 info
->base
= this_base
;
1336 info
->prev_sp
= this_base
;
1338 /* The PC is assumed to be found in SRP. */
1339 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1340 = info
->saved_regs
[SRP_REGNUM
];
1345 /* Advance pc beyond any function entry prologue instructions at pc
1346 to reach some "real" code. */
1348 /* Given a PC value corresponding to the start of a function, return the PC
1349 of the first instruction after the function prologue. */
1352 cris_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1355 CORE_ADDR func_addr
, func_end
;
1356 struct symtab_and_line sal
;
1357 CORE_ADDR pc_after_prologue
;
1359 /* If we have line debugging information, then the end of the prologue
1360 should the first assembly instruction of the first source line. */
1361 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1363 sal
= find_pc_line (func_addr
, 0);
1364 if (sal
.end
> 0 && sal
.end
< func_end
)
1368 if (tdep
->cris_version
== 32)
1369 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1371 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1373 return pc_after_prologue
;
1377 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1380 pc
= frame_unwind_register_unsigned (next_frame
,
1381 gdbarch_pc_regnum (gdbarch
));
1386 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1389 sp
= frame_unwind_register_unsigned (next_frame
,
1390 gdbarch_sp_regnum (gdbarch
));
1394 /* Use the program counter to determine the contents and size of a breakpoint
1395 instruction. It returns a pointer to a string of bytes that encode a
1396 breakpoint instruction, stores the length of the string to *lenptr, and
1397 adjusts pcptr (if necessary) to point to the actual memory location where
1398 the breakpoint should be inserted. */
1400 static const unsigned char *
1401 cris_breakpoint_from_pc (struct gdbarch
*gdbarch
,
1402 CORE_ADDR
*pcptr
, int *lenptr
)
1404 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1405 static unsigned char break8_insn
[] = {0x38, 0xe9};
1406 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1409 if (tdep
->cris_mode
== cris_mode_guru
)
1410 return break15_insn
;
1415 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1419 cris_spec_reg_applicable (struct gdbarch
*gdbarch
,
1420 struct cris_spec_reg spec_reg
)
1422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1423 unsigned int version
= tdep
->cris_version
;
1425 switch (spec_reg
.applicable_version
)
1427 case cris_ver_version_all
:
1429 case cris_ver_warning
:
1430 /* Indeterminate/obsolete. */
1433 return (version
>= 0 && version
<= 3);
1435 return (version
>= 3);
1437 return (version
== 8 || version
== 9);
1439 return (version
>= 8);
1440 case cris_ver_v0_10
:
1441 return (version
>= 0 && version
<= 10);
1442 case cris_ver_v3_10
:
1443 return (version
>= 3 && version
<= 10);
1444 case cris_ver_v8_10
:
1445 return (version
>= 8 && version
<= 10);
1447 return (version
== 10);
1449 return (version
>= 10);
1451 return (version
>= 32);
1453 /* Invalid cris version. */
1458 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1459 register, -1 for an invalid register. */
1462 cris_register_size (struct gdbarch
*gdbarch
, int regno
)
1467 if (regno
>= 0 && regno
< NUM_GENREGS
)
1469 /* General registers (R0 - R15) are 32 bits. */
1472 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1474 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1475 Adjust regno accordingly. */
1476 spec_regno
= regno
- NUM_GENREGS
;
1478 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1480 if (cris_spec_regs
[i
].number
== spec_regno
1481 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1482 /* Go with the first applicable register. */
1483 return cris_spec_regs
[i
].reg_size
;
1485 /* Special register not applicable to this CRIS version. */
1488 else if (regno
>= gdbarch_pc_regnum (gdbarch
)
1489 && regno
< gdbarch_num_regs (gdbarch
))
1491 /* This will apply to CRISv32 only where there are additional registers
1492 after the special registers (pseudo PC and support registers). */
1500 /* Nonzero if regno should not be fetched from the target. This is the case
1501 for unimplemented (size 0) and non-existant registers. */
1504 cris_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1506 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1507 || (cris_register_size (gdbarch
, regno
) == 0));
1510 /* Nonzero if regno should not be written to the target, for various
1514 cris_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1516 /* There are three kinds of registers we refuse to write to.
1517 1. Those that not implemented.
1518 2. Those that are read-only (depends on the processor mode).
1519 3. Those registers to which a write has no effect. */
1522 || regno
>= gdbarch_num_regs (gdbarch
)
1523 || cris_register_size (gdbarch
, regno
) == 0)
1524 /* Not implemented. */
1527 else if (regno
== VR_REGNUM
)
1531 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1532 /* Writing has no effect. */
1535 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1536 agent decide whether they are writable. */
1541 /* Nonzero if regno should not be fetched from the target. This is the case
1542 for unimplemented (size 0) and non-existant registers. */
1545 crisv32_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1547 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1548 || (cris_register_size (gdbarch
, regno
) == 0));
1551 /* Nonzero if regno should not be written to the target, for various
1555 crisv32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1557 /* There are three kinds of registers we refuse to write to.
1558 1. Those that not implemented.
1559 2. Those that are read-only (depends on the processor mode).
1560 3. Those registers to which a write has no effect. */
1563 || regno
>= gdbarch_num_regs (gdbarch
)
1564 || cris_register_size (gdbarch
, regno
) == 0)
1565 /* Not implemented. */
1568 else if (regno
== VR_REGNUM
)
1572 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1573 /* Writing has no effect. */
1576 /* Many special registers are read-only in user mode. Let the debug
1577 agent decide whether they are writable. */
1582 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1583 of data in register regno. */
1585 static struct type
*
1586 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1588 if (regno
== gdbarch_pc_regnum (gdbarch
))
1589 return builtin_type (gdbarch
)->builtin_func_ptr
;
1590 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1591 || regno
== CRIS_FP_REGNUM
)
1592 return builtin_type (gdbarch
)->builtin_data_ptr
;
1593 else if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1594 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1595 /* Note: R8 taken care of previous clause. */
1596 return builtin_type (gdbarch
)->builtin_uint32
;
1597 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1598 return builtin_type (gdbarch
)->builtin_uint16
;
1599 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1600 return builtin_type (gdbarch
)->builtin_uint8
;
1602 /* Invalid (unimplemented) register. */
1603 return builtin_type (gdbarch
)->builtin_int0
;
1606 static struct type
*
1607 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1609 if (regno
== gdbarch_pc_regnum (gdbarch
))
1610 return builtin_type (gdbarch
)->builtin_func_ptr
;
1611 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1612 || regno
== CRIS_FP_REGNUM
)
1613 return builtin_type (gdbarch
)->builtin_data_ptr
;
1614 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1615 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1616 || (regno
== PID_REGNUM
)
1617 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1618 /* Note: R8 and SP taken care of by previous clause. */
1619 return builtin_type (gdbarch
)->builtin_uint32
;
1620 else if (regno
== WZ_REGNUM
)
1621 return builtin_type (gdbarch
)->builtin_uint16
;
1622 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1623 return builtin_type (gdbarch
)->builtin_uint8
;
1626 /* Invalid (unimplemented) register. Should not happen as there are
1627 no unimplemented CRISv32 registers. */
1628 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1629 return builtin_type (gdbarch
)->builtin_int0
;
1633 /* Stores a function return value of type type, where valbuf is the address
1634 of the value to be stored. */
1636 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1639 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1640 const gdb_byte
*valbuf
)
1642 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1643 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1645 int len
= TYPE_LENGTH (type
);
1649 /* Put the return value in R10. */
1650 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1651 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1655 /* Put the return value in R10 and R11. */
1656 val
= extract_unsigned_integer (valbuf
, 4, byte_order
);
1657 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1658 val
= extract_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
);
1659 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1662 error (_("cris_store_return_value: type length too large."));
1665 /* Return the name of register regno as a string. Return NULL for an
1666 invalid or unimplemented register. */
1669 cris_special_register_name (struct gdbarch
*gdbarch
, int regno
)
1674 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1675 Adjust regno accordingly. */
1676 spec_regno
= regno
- NUM_GENREGS
;
1678 /* Assume nothing about the layout of the cris_spec_regs struct
1680 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1682 if (cris_spec_regs
[i
].number
== spec_regno
1683 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1684 /* Go with the first applicable register. */
1685 return cris_spec_regs
[i
].name
;
1687 /* Special register not applicable to this CRIS version. */
1692 cris_register_name (struct gdbarch
*gdbarch
, int regno
)
1694 static char *cris_genreg_names
[] =
1695 { "r0", "r1", "r2", "r3", \
1696 "r4", "r5", "r6", "r7", \
1697 "r8", "r9", "r10", "r11", \
1698 "r12", "r13", "sp", "pc" };
1700 if (regno
>= 0 && regno
< NUM_GENREGS
)
1702 /* General register. */
1703 return cris_genreg_names
[regno
];
1705 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (gdbarch
))
1707 return cris_special_register_name (gdbarch
, regno
);
1711 /* Invalid register. */
1717 crisv32_register_name (struct gdbarch
*gdbarch
, int regno
)
1719 static char *crisv32_genreg_names
[] =
1720 { "r0", "r1", "r2", "r3", \
1721 "r4", "r5", "r6", "r7", \
1722 "r8", "r9", "r10", "r11", \
1723 "r12", "r13", "sp", "acr"
1726 static char *crisv32_sreg_names
[] =
1727 { "s0", "s1", "s2", "s3", \
1728 "s4", "s5", "s6", "s7", \
1729 "s8", "s9", "s10", "s11", \
1730 "s12", "s13", "s14", "s15"
1733 if (regno
>= 0 && regno
< NUM_GENREGS
)
1735 /* General register. */
1736 return crisv32_genreg_names
[regno
];
1738 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1740 return cris_special_register_name (gdbarch
, regno
);
1742 else if (regno
== gdbarch_pc_regnum (gdbarch
))
1746 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1748 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1752 /* Invalid register. */
1757 /* Convert DWARF register number REG to the appropriate register
1758 number used by GDB. */
1761 cris_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1763 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1764 numbering, MOF is 18).
1765 Adapted from gcc/config/cris/cris.h. */
1766 static int cris_dwarf_regmap
[] = {
1778 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1779 regnum
= cris_dwarf_regmap
[reg
];
1784 /* DWARF-2 frame support. */
1787 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1788 struct dwarf2_frame_state_reg
*reg
,
1789 struct frame_info
*this_frame
)
1791 /* The return address column. */
1792 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1793 reg
->how
= DWARF2_FRAME_REG_RA
;
1795 /* The call frame address. */
1796 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1797 reg
->how
= DWARF2_FRAME_REG_CFA
;
1800 /* Extract from an array regbuf containing the raw register state a function
1801 return value of type type, and copy that, in virtual format, into
1804 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1807 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1810 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1811 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1813 int len
= TYPE_LENGTH (type
);
1817 /* Get the return value from R10. */
1818 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1819 store_unsigned_integer (valbuf
, len
, byte_order
, val
);
1823 /* Get the return value from R10 and R11. */
1824 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1825 store_unsigned_integer (valbuf
, 4, byte_order
, val
);
1826 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1827 store_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
, val
);
1830 error (_("cris_extract_return_value: type length too large"));
1833 /* Handle the CRIS return value convention. */
1835 static enum return_value_convention
1836 cris_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1837 struct type
*type
, struct regcache
*regcache
,
1838 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1840 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1841 || TYPE_CODE (type
) == TYPE_CODE_UNION
1842 || TYPE_LENGTH (type
) > 8)
1843 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1844 goes on the stack. */
1845 return RETURN_VALUE_STRUCT_CONVENTION
;
1848 cris_extract_return_value (type
, regcache
, readbuf
);
1850 cris_store_return_value (type
, regcache
, writebuf
);
1852 return RETURN_VALUE_REGISTER_CONVENTION
;
1855 /* Calculates a value that measures how good inst_args constraints an
1856 instruction. It stems from cris_constraint, found in cris-dis.c. */
1859 constraint (unsigned int insn
, const char *inst_args
,
1860 inst_env_type
*inst_env
)
1865 const gdb_byte
*s
= (const gdb_byte
*) inst_args
;
1871 if ((insn
& 0x30) == 0x30)
1876 /* A prefix operand. */
1877 if (inst_env
->prefix_found
)
1883 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1884 valid "push" size. In case of special register, it may be != 4. */
1885 if (inst_env
->prefix_found
)
1891 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1899 tmp
= (insn
>> 0xC) & 0xF;
1901 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1903 /* Since we match four bits, we will give a value of
1904 4 - 1 = 3 in a match. If there is a corresponding
1905 exact match of a special register in another pattern, it
1906 will get a value of 4, which will be higher. This should
1907 be correct in that an exact pattern would match better that
1909 Note that there is a reason for not returning zero; the
1910 pattern for "clear" is partly matched in the bit-pattern
1911 (the two lower bits must be zero), while the bit-pattern
1912 for a move from a special register is matched in the
1913 register constraint.
1914 This also means we will will have a race condition if
1915 there is a partly match in three bits in the bit pattern. */
1916 if (tmp
== cris_spec_regs
[i
].number
)
1923 if (cris_spec_regs
[i
].name
== NULL
)
1930 /* Returns the number of bits set in the variable value. */
1933 number_of_bits (unsigned int value
)
1935 int number_of_bits
= 0;
1939 number_of_bits
+= 1;
1940 value
&= (value
- 1);
1942 return number_of_bits
;
1945 /* Finds the address that should contain the single step breakpoint(s).
1946 It stems from code in cris-dis.c. */
1949 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
1952 int max_level_of_match
= -1;
1953 int max_matched
= -1;
1956 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
1958 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
1959 && ((cris_opcodes
[i
].lose
& insn
) == 0)
1960 /* Only CRISv10 instructions, please. */
1961 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
1963 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
1964 if (level_of_match
>= 0)
1967 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
1968 if (level_of_match
> max_level_of_match
)
1971 max_level_of_match
= level_of_match
;
1972 if (level_of_match
== 16)
1974 /* All bits matched, cannot find better. */
1984 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1985 actually an internal error. */
1988 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
1992 unsigned short insn
;
1993 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1994 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1996 /* Create a local register image and set the initial state. */
1997 for (i
= 0; i
< NUM_GENREGS
; i
++)
2000 (unsigned long) get_frame_register_unsigned (frame
, i
);
2002 offset
= NUM_GENREGS
;
2003 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2006 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2008 inst_env
->branch_found
= 0;
2009 inst_env
->slot_needed
= 0;
2010 inst_env
->delay_slot_pc_active
= 0;
2011 inst_env
->prefix_found
= 0;
2012 inst_env
->invalid
= 0;
2013 inst_env
->xflag_found
= 0;
2014 inst_env
->disable_interrupt
= 0;
2015 inst_env
->byte_order
= byte_order
;
2017 /* Look for a step target. */
2020 /* Read an instruction from the client. */
2021 insn
= read_memory_unsigned_integer
2022 (inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)], 2, byte_order
);
2024 /* If the instruction is not in a delay slot the new content of the
2025 PC is [PC] + 2. If the instruction is in a delay slot it is not
2026 that simple. Since a instruction in a delay slot cannot change
2027 the content of the PC, it does not matter what value PC will have.
2028 Just make sure it is a valid instruction. */
2029 if (!inst_env
->delay_slot_pc_active
)
2031 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)] += 2;
2035 inst_env
->delay_slot_pc_active
= 0;
2036 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)]
2037 = inst_env
->delay_slot_pc
;
2039 /* Analyse the present instruction. */
2040 i
= find_cris_op (insn
, inst_env
);
2043 inst_env
->invalid
= 1;
2047 cris_gdb_func (gdbarch
, cris_opcodes
[i
].op
, insn
, inst_env
);
2049 } while (!inst_env
->invalid
2050 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2051 || inst_env
->slot_needed
));
2055 /* There is no hardware single-step support. The function find_step_target
2056 digs through the opcodes in order to find all possible targets.
2057 Either one ordinary target or two targets for branches may be found. */
2060 cris_software_single_step (struct frame_info
*frame
)
2062 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2063 struct address_space
*aspace
= get_frame_address_space (frame
);
2064 inst_env_type inst_env
;
2066 /* Analyse the present instruction environment and insert
2068 int status
= find_step_target (frame
, &inst_env
);
2071 /* Could not find a target. Things are likely to go downhill
2073 warning (_("CRIS software single step could not find a step target."));
2077 /* Insert at most two breakpoints. One for the next PC content
2078 and possibly another one for a branch, jump, etc. */
2080 = (CORE_ADDR
) inst_env
.reg
[gdbarch_pc_regnum (gdbarch
)];
2081 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2082 if (inst_env
.branch_found
2083 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2085 CORE_ADDR branch_target_address
2086 = (CORE_ADDR
) inst_env
.branch_break_address
;
2087 insert_single_step_breakpoint (gdbarch
,
2088 aspace
, branch_target_address
);
2095 /* Calculates the prefix value for quick offset addressing mode. */
2098 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2100 /* It's invalid to be in a delay slot. You can't have a prefix to this
2101 instruction (not 100% sure). */
2102 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2104 inst_env
->invalid
= 1;
2108 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2109 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2111 /* A prefix doesn't change the xflag_found. But the rest of the flags
2113 inst_env
->slot_needed
= 0;
2114 inst_env
->prefix_found
= 1;
2117 /* Updates the autoincrement register. The size of the increment is derived
2118 from the size of the operation. The PC is always kept aligned on even
2122 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2124 if (size
== INST_BYTE_SIZE
)
2126 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2128 /* The PC must be word aligned, so increase the PC with one
2129 word even if the size is byte. */
2130 if (cris_get_operand1 (inst
) == REG_PC
)
2132 inst_env
->reg
[REG_PC
] += 1;
2135 else if (size
== INST_WORD_SIZE
)
2137 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2139 else if (size
== INST_DWORD_SIZE
)
2141 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2146 inst_env
->invalid
= 1;
2150 /* Just a forward declaration. */
2152 static unsigned long get_data_from_address (unsigned short *inst
,
2154 enum bfd_endian byte_order
);
2156 /* Calculates the prefix value for the general case of offset addressing
2160 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2162 /* It's invalid to be in a delay slot. */
2163 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2165 inst_env
->invalid
= 1;
2169 /* The calculation of prefix_value used to be after process_autoincrement,
2170 but that fails for an instruction such as jsr [$r0+12] which is encoded
2171 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2172 mustn't be incremented until we have read it and what it points at. */
2173 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2175 /* The offset is an indirection of the contents of the operand1 register. */
2176 inst_env
->prefix_value
+=
2177 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)],
2178 inst_env
->byte_order
);
2180 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2182 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2185 /* A prefix doesn't change the xflag_found. But the rest of the flags
2187 inst_env
->slot_needed
= 0;
2188 inst_env
->prefix_found
= 1;
2191 /* Calculates the prefix value for the index addressing mode. */
2194 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2196 /* It's invalid to be in a delay slot. I can't see that it's possible to
2197 have a prefix to this instruction. So I will treat this as invalid. */
2198 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2200 inst_env
->invalid
= 1;
2204 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2206 /* The offset is the operand2 value shifted the size of the instruction
2208 inst_env
->prefix_value
+=
2209 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2211 /* If the PC is operand1 (base) the address used is the address after
2212 the main instruction, i.e. address + 2 (the PC is already compensated
2213 for the prefix operation). */
2214 if (cris_get_operand1 (inst
) == REG_PC
)
2216 inst_env
->prefix_value
+= 2;
2219 /* A prefix doesn't change the xflag_found. But the rest of the flags
2221 inst_env
->slot_needed
= 0;
2222 inst_env
->xflag_found
= 0;
2223 inst_env
->prefix_found
= 1;
2226 /* Calculates the prefix value for the double indirect addressing mode. */
2229 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2234 /* It's invalid to be in a delay slot. */
2235 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2237 inst_env
->invalid
= 1;
2241 /* The prefix value is one dereference of the contents of the operand1
2243 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2244 inst_env
->prefix_value
2245 = read_memory_unsigned_integer (address
, 4, inst_env
->byte_order
);
2247 /* Check if the mode is autoincrement. */
2248 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2250 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2253 /* A prefix doesn't change the xflag_found. But the rest of the flags
2255 inst_env
->slot_needed
= 0;
2256 inst_env
->xflag_found
= 0;
2257 inst_env
->prefix_found
= 1;
2260 /* Finds the destination for a branch with 8-bits offset. */
2263 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2268 /* If we have a prefix or are in a delay slot it's bad. */
2269 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2271 inst_env
->invalid
= 1;
2275 /* We have a branch, find out where the branch will land. */
2276 offset
= cris_get_branch_short_offset (inst
);
2278 /* Check if the offset is signed. */
2279 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2284 /* The offset ends with the sign bit, set it to zero. The address
2285 should always be word aligned. */
2286 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2288 inst_env
->branch_found
= 1;
2289 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2291 inst_env
->slot_needed
= 1;
2292 inst_env
->prefix_found
= 0;
2293 inst_env
->xflag_found
= 0;
2294 inst_env
->disable_interrupt
= 1;
2297 /* Finds the destination for a branch with 16-bits offset. */
2300 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2304 /* If we have a prefix or is in a delay slot it's bad. */
2305 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2307 inst_env
->invalid
= 1;
2311 /* We have a branch, find out the offset for the branch. */
2312 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2,
2313 inst_env
->byte_order
);
2315 /* The instruction is one word longer than normal, so add one word
2317 inst_env
->reg
[REG_PC
] += 2;
2319 inst_env
->branch_found
= 1;
2320 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2323 inst_env
->slot_needed
= 1;
2324 inst_env
->prefix_found
= 0;
2325 inst_env
->xflag_found
= 0;
2326 inst_env
->disable_interrupt
= 1;
2329 /* Handles the ABS instruction. */
2332 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2337 /* ABS can't have a prefix, so it's bad if it does. */
2338 if (inst_env
->prefix_found
)
2340 inst_env
->invalid
= 1;
2344 /* Check if the operation affects the PC. */
2345 if (cris_get_operand2 (inst
) == REG_PC
)
2348 /* It's invalid to change to the PC if we are in a delay slot. */
2349 if (inst_env
->slot_needed
)
2351 inst_env
->invalid
= 1;
2355 value
= (long) inst_env
->reg
[REG_PC
];
2357 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2358 if (value
!= SIGNED_DWORD_MASK
)
2361 inst_env
->reg
[REG_PC
] = (long) value
;
2365 inst_env
->slot_needed
= 0;
2366 inst_env
->prefix_found
= 0;
2367 inst_env
->xflag_found
= 0;
2368 inst_env
->disable_interrupt
= 0;
2371 /* Handles the ADDI instruction. */
2374 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2376 /* It's invalid to have the PC as base register. And ADDI can't have
2378 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2380 inst_env
->invalid
= 1;
2384 inst_env
->slot_needed
= 0;
2385 inst_env
->prefix_found
= 0;
2386 inst_env
->xflag_found
= 0;
2387 inst_env
->disable_interrupt
= 0;
2390 /* Handles the ASR instruction. */
2393 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2396 unsigned long value
;
2397 unsigned long signed_extend_mask
= 0;
2399 /* ASR can't have a prefix, so check that it doesn't. */
2400 if (inst_env
->prefix_found
)
2402 inst_env
->invalid
= 1;
2406 /* Check if the PC is the target register. */
2407 if (cris_get_operand2 (inst
) == REG_PC
)
2409 /* It's invalid to change the PC in a delay slot. */
2410 if (inst_env
->slot_needed
)
2412 inst_env
->invalid
= 1;
2415 /* Get the number of bits to shift. */
2417 = cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2418 value
= inst_env
->reg
[REG_PC
];
2420 /* Find out how many bits the operation should apply to. */
2421 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2423 if (value
& SIGNED_BYTE_MASK
)
2425 signed_extend_mask
= 0xFF;
2426 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2427 signed_extend_mask
= ~signed_extend_mask
;
2429 value
= value
>> shift_steps
;
2430 value
|= signed_extend_mask
;
2432 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2433 inst_env
->reg
[REG_PC
] |= value
;
2435 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2437 if (value
& SIGNED_WORD_MASK
)
2439 signed_extend_mask
= 0xFFFF;
2440 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2441 signed_extend_mask
= ~signed_extend_mask
;
2443 value
= value
>> shift_steps
;
2444 value
|= signed_extend_mask
;
2446 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2447 inst_env
->reg
[REG_PC
] |= value
;
2449 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2451 if (value
& SIGNED_DWORD_MASK
)
2453 signed_extend_mask
= 0xFFFFFFFF;
2454 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2455 signed_extend_mask
= ~signed_extend_mask
;
2457 value
= value
>> shift_steps
;
2458 value
|= signed_extend_mask
;
2459 inst_env
->reg
[REG_PC
] = value
;
2462 inst_env
->slot_needed
= 0;
2463 inst_env
->prefix_found
= 0;
2464 inst_env
->xflag_found
= 0;
2465 inst_env
->disable_interrupt
= 0;
2468 /* Handles the ASRQ instruction. */
2471 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2475 unsigned long value
;
2476 unsigned long signed_extend_mask
= 0;
2478 /* ASRQ can't have a prefix, so check that it doesn't. */
2479 if (inst_env
->prefix_found
)
2481 inst_env
->invalid
= 1;
2485 /* Check if the PC is the target register. */
2486 if (cris_get_operand2 (inst
) == REG_PC
)
2489 /* It's invalid to change the PC in a delay slot. */
2490 if (inst_env
->slot_needed
)
2492 inst_env
->invalid
= 1;
2495 /* The shift size is given as a 5 bit quick value, i.e. we don't
2496 want the sign bit of the quick value. */
2497 shift_steps
= cris_get_asr_shift_steps (inst
);
2498 value
= inst_env
->reg
[REG_PC
];
2499 if (value
& SIGNED_DWORD_MASK
)
2501 signed_extend_mask
= 0xFFFFFFFF;
2502 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2503 signed_extend_mask
= ~signed_extend_mask
;
2505 value
= value
>> shift_steps
;
2506 value
|= signed_extend_mask
;
2507 inst_env
->reg
[REG_PC
] = value
;
2509 inst_env
->slot_needed
= 0;
2510 inst_env
->prefix_found
= 0;
2511 inst_env
->xflag_found
= 0;
2512 inst_env
->disable_interrupt
= 0;
2515 /* Handles the AX, EI and SETF instruction. */
2518 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2520 if (inst_env
->prefix_found
)
2522 inst_env
->invalid
= 1;
2525 /* Check if the instruction is setting the X flag. */
2526 if (cris_is_xflag_bit_on (inst
))
2528 inst_env
->xflag_found
= 1;
2532 inst_env
->xflag_found
= 0;
2534 inst_env
->slot_needed
= 0;
2535 inst_env
->prefix_found
= 0;
2536 inst_env
->disable_interrupt
= 1;
2539 /* Checks if the instruction is in assign mode. If so, it updates the assign
2540 register. Note that check_assign assumes that the caller has checked that
2541 there is a prefix to this instruction. The mode check depends on this. */
2544 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2546 /* Check if it's an assign addressing mode. */
2547 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2549 /* Assign the prefix value to operand 1. */
2550 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2554 /* Handles the 2-operand BOUND instruction. */
2557 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2559 /* It's invalid to have the PC as the index operand. */
2560 if (cris_get_operand2 (inst
) == REG_PC
)
2562 inst_env
->invalid
= 1;
2565 /* Check if we have a prefix. */
2566 if (inst_env
->prefix_found
)
2568 check_assign (inst
, inst_env
);
2570 /* Check if this is an autoincrement mode. */
2571 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2573 /* It's invalid to change the PC in a delay slot. */
2574 if (inst_env
->slot_needed
)
2576 inst_env
->invalid
= 1;
2579 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2581 inst_env
->slot_needed
= 0;
2582 inst_env
->prefix_found
= 0;
2583 inst_env
->xflag_found
= 0;
2584 inst_env
->disable_interrupt
= 0;
2587 /* Handles the 3-operand BOUND instruction. */
2590 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2592 /* It's an error if we haven't got a prefix. And it's also an error
2593 if the PC is the destination register. */
2594 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2596 inst_env
->invalid
= 1;
2599 inst_env
->slot_needed
= 0;
2600 inst_env
->prefix_found
= 0;
2601 inst_env
->xflag_found
= 0;
2602 inst_env
->disable_interrupt
= 0;
2605 /* Clears the status flags in inst_env. */
2608 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2610 /* It's an error if we have got a prefix. */
2611 if (inst_env
->prefix_found
)
2613 inst_env
->invalid
= 1;
2617 inst_env
->slot_needed
= 0;
2618 inst_env
->prefix_found
= 0;
2619 inst_env
->xflag_found
= 0;
2620 inst_env
->disable_interrupt
= 0;
2623 /* Clears the status flags in inst_env. */
2626 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2628 /* It's an error if we have got a prefix. */
2629 if (inst_env
->prefix_found
)
2631 inst_env
->invalid
= 1;
2635 inst_env
->slot_needed
= 0;
2636 inst_env
->prefix_found
= 0;
2637 inst_env
->xflag_found
= 0;
2638 inst_env
->disable_interrupt
= 1;
2641 /* Handles the CLEAR instruction if it's in register mode. */
2644 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2646 /* Check if the target is the PC. */
2647 if (cris_get_operand2 (inst
) == REG_PC
)
2649 /* The instruction will clear the instruction's size bits. */
2650 int clear_size
= cris_get_clear_size (inst
);
2651 if (clear_size
== INST_BYTE_SIZE
)
2653 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2655 if (clear_size
== INST_WORD_SIZE
)
2657 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2659 if (clear_size
== INST_DWORD_SIZE
)
2661 inst_env
->delay_slot_pc
= 0x0;
2663 /* The jump will be delayed with one delay slot. So we need a delay
2665 inst_env
->slot_needed
= 1;
2666 inst_env
->delay_slot_pc_active
= 1;
2670 /* The PC will not change => no delay slot. */
2671 inst_env
->slot_needed
= 0;
2673 inst_env
->prefix_found
= 0;
2674 inst_env
->xflag_found
= 0;
2675 inst_env
->disable_interrupt
= 0;
2678 /* Handles the TEST instruction if it's in register mode. */
2681 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2683 /* It's an error if we have got a prefix. */
2684 if (inst_env
->prefix_found
)
2686 inst_env
->invalid
= 1;
2689 inst_env
->slot_needed
= 0;
2690 inst_env
->prefix_found
= 0;
2691 inst_env
->xflag_found
= 0;
2692 inst_env
->disable_interrupt
= 0;
2696 /* Handles the CLEAR and TEST instruction if the instruction isn't
2697 in register mode. */
2700 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2702 /* Check if we are in a prefix mode. */
2703 if (inst_env
->prefix_found
)
2705 /* The only way the PC can change is if this instruction is in
2706 assign addressing mode. */
2707 check_assign (inst
, inst_env
);
2709 /* Indirect mode can't change the PC so just check if the mode is
2711 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2713 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2715 inst_env
->slot_needed
= 0;
2716 inst_env
->prefix_found
= 0;
2717 inst_env
->xflag_found
= 0;
2718 inst_env
->disable_interrupt
= 0;
2721 /* Checks that the PC isn't the destination register or the instructions has
2725 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2727 /* It's invalid to have the PC as the destination. The instruction can't
2729 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2731 inst_env
->invalid
= 1;
2735 inst_env
->slot_needed
= 0;
2736 inst_env
->prefix_found
= 0;
2737 inst_env
->xflag_found
= 0;
2738 inst_env
->disable_interrupt
= 0;
2741 /* Checks that the instruction doesn't have a prefix. */
2744 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2746 /* The instruction can't have a prefix. */
2747 if (inst_env
->prefix_found
)
2749 inst_env
->invalid
= 1;
2753 inst_env
->slot_needed
= 0;
2754 inst_env
->prefix_found
= 0;
2755 inst_env
->xflag_found
= 0;
2756 inst_env
->disable_interrupt
= 1;
2759 /* Checks that the PC isn't the destination register and that the instruction
2760 doesn't have a prefix. */
2763 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2765 /* It's invalid to have the PC as the destination. The instruction can't
2767 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2769 inst_env
->invalid
= 1;
2773 inst_env
->slot_needed
= 0;
2774 inst_env
->prefix_found
= 0;
2775 inst_env
->xflag_found
= 0;
2776 inst_env
->disable_interrupt
= 1;
2779 /* Handles the register mode JUMP instruction. */
2782 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2784 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2785 you can't have a prefix. */
2786 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2788 inst_env
->invalid
= 1;
2792 /* Just change the PC. */
2793 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2794 inst_env
->slot_needed
= 0;
2795 inst_env
->prefix_found
= 0;
2796 inst_env
->xflag_found
= 0;
2797 inst_env
->disable_interrupt
= 1;
2800 /* Handles the JUMP instruction for all modes except register. */
2803 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2805 unsigned long newpc
;
2808 /* It's invalid to do a JUMP in a delay slot. */
2809 if (inst_env
->slot_needed
)
2811 inst_env
->invalid
= 1;
2815 /* Check if we have a prefix. */
2816 if (inst_env
->prefix_found
)
2818 check_assign (inst
, inst_env
);
2820 /* Get the new value for the PC. */
2822 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2823 4, inst_env
->byte_order
);
2827 /* Get the new value for the PC. */
2828 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2829 newpc
= read_memory_unsigned_integer (address
,
2830 4, inst_env
->byte_order
);
2832 /* Check if we should increment a register. */
2833 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2835 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2838 inst_env
->reg
[REG_PC
] = newpc
;
2840 inst_env
->slot_needed
= 0;
2841 inst_env
->prefix_found
= 0;
2842 inst_env
->xflag_found
= 0;
2843 inst_env
->disable_interrupt
= 1;
2846 /* Handles moves to special registers (aka P-register) for all modes. */
2849 move_to_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2850 inst_env_type
*inst_env
)
2852 if (inst_env
->prefix_found
)
2854 /* The instruction has a prefix that means we are only interested if
2855 the instruction is in assign mode. */
2856 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2858 /* The prefix handles the problem if we are in a delay slot. */
2859 if (cris_get_operand1 (inst
) == REG_PC
)
2861 /* Just take care of the assign. */
2862 check_assign (inst
, inst_env
);
2866 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2868 /* The instruction doesn't have a prefix, the only case left that we
2869 are interested in is the autoincrement mode. */
2870 if (cris_get_operand1 (inst
) == REG_PC
)
2872 /* If the PC is to be incremented it's invalid to be in a
2874 if (inst_env
->slot_needed
)
2876 inst_env
->invalid
= 1;
2880 /* The increment depends on the size of the special register. */
2881 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2883 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2885 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2887 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2891 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2895 inst_env
->slot_needed
= 0;
2896 inst_env
->prefix_found
= 0;
2897 inst_env
->xflag_found
= 0;
2898 inst_env
->disable_interrupt
= 1;
2901 /* Handles moves from special registers (aka P-register) for all modes
2905 none_reg_mode_move_from_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2906 inst_env_type
*inst_env
)
2908 if (inst_env
->prefix_found
)
2910 /* The instruction has a prefix that means we are only interested if
2911 the instruction is in assign mode. */
2912 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2914 /* The prefix handles the problem if we are in a delay slot. */
2915 if (cris_get_operand1 (inst
) == REG_PC
)
2917 /* Just take care of the assign. */
2918 check_assign (inst
, inst_env
);
2922 /* The instruction doesn't have a prefix, the only case left that we
2923 are interested in is the autoincrement mode. */
2924 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2926 if (cris_get_operand1 (inst
) == REG_PC
)
2928 /* If the PC is to be incremented it's invalid to be in a
2930 if (inst_env
->slot_needed
)
2932 inst_env
->invalid
= 1;
2936 /* The increment depends on the size of the special register. */
2937 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2939 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2941 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2943 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2947 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2951 inst_env
->slot_needed
= 0;
2952 inst_env
->prefix_found
= 0;
2953 inst_env
->xflag_found
= 0;
2954 inst_env
->disable_interrupt
= 1;
2957 /* Handles moves from special registers (aka P-register) when the mode
2961 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2963 /* Register mode move from special register can't have a prefix. */
2964 if (inst_env
->prefix_found
)
2966 inst_env
->invalid
= 1;
2970 if (cris_get_operand1 (inst
) == REG_PC
)
2972 /* It's invalid to change the PC in a delay slot. */
2973 if (inst_env
->slot_needed
)
2975 inst_env
->invalid
= 1;
2978 /* The destination is the PC, the jump will have a delay slot. */
2979 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
2980 inst_env
->slot_needed
= 1;
2981 inst_env
->delay_slot_pc_active
= 1;
2985 /* If the destination isn't PC, there will be no jump. */
2986 inst_env
->slot_needed
= 0;
2988 inst_env
->prefix_found
= 0;
2989 inst_env
->xflag_found
= 0;
2990 inst_env
->disable_interrupt
= 1;
2993 /* Handles the MOVEM from memory to general register instruction. */
2996 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2998 if (inst_env
->prefix_found
)
3000 /* The prefix handles the problem if we are in a delay slot. Is the
3001 MOVEM instruction going to change the PC? */
3002 if (cris_get_operand2 (inst
) >= REG_PC
)
3004 inst_env
->reg
[REG_PC
] =
3005 read_memory_unsigned_integer (inst_env
->prefix_value
,
3006 4, inst_env
->byte_order
);
3008 /* The assign value is the value after the increment. Normally, the
3009 assign value is the value before the increment. */
3010 if ((cris_get_operand1 (inst
) == REG_PC
)
3011 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3013 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3014 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3019 /* Is the MOVEM instruction going to change the PC? */
3020 if (cris_get_operand2 (inst
) == REG_PC
)
3022 /* It's invalid to change the PC in a delay slot. */
3023 if (inst_env
->slot_needed
)
3025 inst_env
->invalid
= 1;
3028 inst_env
->reg
[REG_PC
] =
3029 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3030 4, inst_env
->byte_order
);
3032 /* The increment is not depending on the size, instead it's depending
3033 on the number of registers loaded from memory. */
3034 if ((cris_get_operand1 (inst
) == REG_PC
)
3035 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3037 /* It's invalid to change the PC in a delay slot. */
3038 if (inst_env
->slot_needed
)
3040 inst_env
->invalid
= 1;
3043 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3046 inst_env
->slot_needed
= 0;
3047 inst_env
->prefix_found
= 0;
3048 inst_env
->xflag_found
= 0;
3049 inst_env
->disable_interrupt
= 0;
3052 /* Handles the MOVEM to memory from general register instruction. */
3055 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3057 if (inst_env
->prefix_found
)
3059 /* The assign value is the value after the increment. Normally, the
3060 assign value is the value before the increment. */
3061 if ((cris_get_operand1 (inst
) == REG_PC
)
3062 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3064 /* The prefix handles the problem if we are in a delay slot. */
3065 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3066 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3071 /* The increment is not depending on the size, instead it's depending
3072 on the number of registers loaded to memory. */
3073 if ((cris_get_operand1 (inst
) == REG_PC
)
3074 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3076 /* It's invalid to change the PC in a delay slot. */
3077 if (inst_env
->slot_needed
)
3079 inst_env
->invalid
= 1;
3082 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3085 inst_env
->slot_needed
= 0;
3086 inst_env
->prefix_found
= 0;
3087 inst_env
->xflag_found
= 0;
3088 inst_env
->disable_interrupt
= 0;
3091 /* Handles the intructions that's not yet implemented, by setting
3092 inst_env->invalid to true. */
3095 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3097 inst_env
->invalid
= 1;
3100 /* Handles the XOR instruction. */
3103 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3105 /* XOR can't have a prefix. */
3106 if (inst_env
->prefix_found
)
3108 inst_env
->invalid
= 1;
3112 /* Check if the PC is the target. */
3113 if (cris_get_operand2 (inst
) == REG_PC
)
3115 /* It's invalid to change the PC in a delay slot. */
3116 if (inst_env
->slot_needed
)
3118 inst_env
->invalid
= 1;
3121 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3123 inst_env
->slot_needed
= 0;
3124 inst_env
->prefix_found
= 0;
3125 inst_env
->xflag_found
= 0;
3126 inst_env
->disable_interrupt
= 0;
3129 /* Handles the MULS instruction. */
3132 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3134 /* MULS/U can't have a prefix. */
3135 if (inst_env
->prefix_found
)
3137 inst_env
->invalid
= 1;
3141 /* Consider it invalid if the PC is the target. */
3142 if (cris_get_operand2 (inst
) == REG_PC
)
3144 inst_env
->invalid
= 1;
3147 inst_env
->slot_needed
= 0;
3148 inst_env
->prefix_found
= 0;
3149 inst_env
->xflag_found
= 0;
3150 inst_env
->disable_interrupt
= 0;
3153 /* Handles the MULU instruction. */
3156 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3158 /* MULS/U can't have a prefix. */
3159 if (inst_env
->prefix_found
)
3161 inst_env
->invalid
= 1;
3165 /* Consider it invalid if the PC is the target. */
3166 if (cris_get_operand2 (inst
) == REG_PC
)
3168 inst_env
->invalid
= 1;
3171 inst_env
->slot_needed
= 0;
3172 inst_env
->prefix_found
= 0;
3173 inst_env
->xflag_found
= 0;
3174 inst_env
->disable_interrupt
= 0;
3177 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3178 The MOVE instruction is the move from source to register. */
3181 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3182 unsigned long source1
, unsigned long source2
)
3184 unsigned long pc_mask
;
3185 unsigned long operation_mask
;
3187 /* Find out how many bits the operation should apply to. */
3188 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3190 pc_mask
= 0xFFFFFF00;
3191 operation_mask
= 0xFF;
3193 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3195 pc_mask
= 0xFFFF0000;
3196 operation_mask
= 0xFFFF;
3198 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3201 operation_mask
= 0xFFFFFFFF;
3205 /* The size is out of range. */
3206 inst_env
->invalid
= 1;
3210 /* The instruction just works on uw_operation_mask bits. */
3211 source2
&= operation_mask
;
3212 source1
&= operation_mask
;
3214 /* Now calculate the result. The opcode's 3 first bits separates
3215 the different actions. */
3216 switch (cris_get_opcode (inst
) & 7)
3226 case 2: /* subtract */
3230 case 3: /* compare */
3242 inst_env
->invalid
= 1;
3248 /* Make sure that the result doesn't contain more than the instruction
3250 source2
&= operation_mask
;
3252 /* Calculate the new breakpoint address. */
3253 inst_env
->reg
[REG_PC
] &= pc_mask
;
3254 inst_env
->reg
[REG_PC
] |= source1
;
3258 /* Extends the value from either byte or word size to a dword. If the mode
3259 is zero extend then the value is extended with zero. If instead the mode
3260 is signed extend the sign bit of the value is taken into consideration. */
3262 static unsigned long
3263 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3265 /* The size can be either byte or word, check which one it is.
3266 Don't check the highest bit, it's indicating if it's a zero
3268 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3273 /* Check if the instruction is signed extend. If so, check if value has
3275 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3277 value
|= SIGNED_WORD_EXTEND_MASK
;
3285 /* Check if the instruction is signed extend. If so, check if value has
3287 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3289 value
|= SIGNED_BYTE_EXTEND_MASK
;
3292 /* The size should now be dword. */
3293 cris_set_size_to_dword (inst
);
3297 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3298 instruction. The MOVE instruction is the move from source to register. */
3301 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3302 inst_env_type
*inst_env
)
3304 unsigned long operand1
;
3305 unsigned long operand2
;
3307 /* It's invalid to have a prefix to the instruction. This is a register
3308 mode instruction and can't have a prefix. */
3309 if (inst_env
->prefix_found
)
3311 inst_env
->invalid
= 1;
3314 /* Check if the instruction has PC as its target. */
3315 if (cris_get_operand2 (inst
) == REG_PC
)
3317 if (inst_env
->slot_needed
)
3319 inst_env
->invalid
= 1;
3322 /* The instruction has the PC as its target register. */
3323 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3324 operand2
= inst_env
->reg
[REG_PC
];
3326 /* Check if it's a extend, signed or zero instruction. */
3327 if (cris_get_opcode (inst
) < 4)
3329 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3331 /* Calculate the PC value after the instruction, i.e. where the
3332 breakpoint should be. The order of the udw_operands is vital. */
3333 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3335 inst_env
->slot_needed
= 0;
3336 inst_env
->prefix_found
= 0;
3337 inst_env
->xflag_found
= 0;
3338 inst_env
->disable_interrupt
= 0;
3341 /* Returns the data contained at address. The size of the data is derived from
3342 the size of the operation. If the instruction is a zero or signed
3343 extend instruction, the size field is changed in instruction. */
3345 static unsigned long
3346 get_data_from_address (unsigned short *inst
, CORE_ADDR address
,
3347 enum bfd_endian byte_order
)
3349 int size
= cris_get_size (*inst
);
3350 unsigned long value
;
3352 /* If it's an extend instruction we don't want the signed extend bit,
3353 because it influences the size. */
3354 if (cris_get_opcode (*inst
) < 4)
3356 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3358 /* Is there a need for checking the size? Size should contain the number of
3361 value
= read_memory_unsigned_integer (address
, size
, byte_order
);
3363 /* Check if it's an extend, signed or zero instruction. */
3364 if (cris_get_opcode (*inst
) < 4)
3366 value
= do_sign_or_zero_extend (value
, inst
);
3371 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3372 instructions. The MOVE instruction is the move from source to register. */
3375 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3376 inst_env_type
*inst_env
)
3378 unsigned long operand2
;
3379 unsigned long operand3
;
3381 check_assign (inst
, inst_env
);
3382 if (cris_get_operand2 (inst
) == REG_PC
)
3384 operand2
= inst_env
->reg
[REG_PC
];
3386 /* Get the value of the third operand. */
3387 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3388 inst_env
->byte_order
);
3390 /* Calculate the PC value after the instruction, i.e. where the
3391 breakpoint should be. The order of the udw_operands is vital. */
3392 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3394 inst_env
->slot_needed
= 0;
3395 inst_env
->prefix_found
= 0;
3396 inst_env
->xflag_found
= 0;
3397 inst_env
->disable_interrupt
= 0;
3400 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3401 OR instructions. Note that for this to work as expected, the calling
3402 function must have made sure that there is a prefix to this instruction. */
3405 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3406 inst_env_type
*inst_env
)
3408 unsigned long operand2
;
3409 unsigned long operand3
;
3411 if (cris_get_operand1 (inst
) == REG_PC
)
3413 /* The PC will be changed by the instruction. */
3414 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3416 /* Get the value of the third operand. */
3417 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3418 inst_env
->byte_order
);
3420 /* Calculate the PC value after the instruction, i.e. where the
3421 breakpoint should be. */
3422 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3424 inst_env
->slot_needed
= 0;
3425 inst_env
->prefix_found
= 0;
3426 inst_env
->xflag_found
= 0;
3427 inst_env
->disable_interrupt
= 0;
3430 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3431 instructions. The MOVE instruction is the move from source to register. */
3434 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3435 inst_env_type
*inst_env
)
3437 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3439 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3440 SUB, AND or OR something weird is going on (if everything works these
3441 instructions should end up in the three operand version). */
3442 inst_env
->invalid
= 1;
3447 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3449 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3451 inst_env
->slot_needed
= 0;
3452 inst_env
->prefix_found
= 0;
3453 inst_env
->xflag_found
= 0;
3454 inst_env
->disable_interrupt
= 0;
3457 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3458 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3459 source to register. */
3462 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3463 inst_env_type
*inst_env
)
3465 unsigned long operand1
;
3466 unsigned long operand2
;
3467 unsigned long operand3
;
3470 /* The instruction is either an indirect or autoincrement addressing mode.
3471 Check if the destination register is the PC. */
3472 if (cris_get_operand2 (inst
) == REG_PC
)
3474 /* Must be done here, get_data_from_address may change the size
3476 size
= cris_get_size (inst
);
3477 operand2
= inst_env
->reg
[REG_PC
];
3479 /* Get the value of the third operand, i.e. the indirect operand. */
3480 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3481 operand3
= get_data_from_address (&inst
, operand1
, inst_env
->byte_order
);
3483 /* Calculate the PC value after the instruction, i.e. where the
3484 breakpoint should be. The order of the udw_operands is vital. */
3485 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3487 /* If this is an autoincrement addressing mode, check if the increment
3489 if ((cris_get_operand1 (inst
) == REG_PC
)
3490 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3492 /* Get the size field. */
3493 size
= cris_get_size (inst
);
3495 /* If it's an extend instruction we don't want the signed extend bit,
3496 because it influences the size. */
3497 if (cris_get_opcode (inst
) < 4)
3499 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3501 process_autoincrement (size
, inst
, inst_env
);
3503 inst_env
->slot_needed
= 0;
3504 inst_env
->prefix_found
= 0;
3505 inst_env
->xflag_found
= 0;
3506 inst_env
->disable_interrupt
= 0;
3509 /* Handles the two-operand addressing mode, all modes except register, for
3510 the ADD, SUB CMP, AND and OR instruction. */
3513 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3514 inst_env_type
*inst_env
)
3516 if (inst_env
->prefix_found
)
3518 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3520 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3522 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3524 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3528 /* The mode is invalid for a prefixed base instruction. */
3529 inst_env
->invalid
= 1;
3535 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3539 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3542 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3544 unsigned long operand1
;
3545 unsigned long operand2
;
3547 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3548 instruction and can't have a prefix. */
3549 if (inst_env
->prefix_found
)
3551 inst_env
->invalid
= 1;
3555 /* Check if the instruction has PC as its target. */
3556 if (cris_get_operand2 (inst
) == REG_PC
)
3558 if (inst_env
->slot_needed
)
3560 inst_env
->invalid
= 1;
3563 operand1
= cris_get_quick_value (inst
);
3564 operand2
= inst_env
->reg
[REG_PC
];
3566 /* The size should now be dword. */
3567 cris_set_size_to_dword (&inst
);
3569 /* Calculate the PC value after the instruction, i.e. where the
3570 breakpoint should be. */
3571 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3573 inst_env
->slot_needed
= 0;
3574 inst_env
->prefix_found
= 0;
3575 inst_env
->xflag_found
= 0;
3576 inst_env
->disable_interrupt
= 0;
3579 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3582 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3584 unsigned long operand1
;
3585 unsigned long operand2
;
3587 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3588 instruction and can't have a prefix. */
3589 if (inst_env
->prefix_found
)
3591 inst_env
->invalid
= 1;
3594 /* Check if the instruction has PC as its target. */
3595 if (cris_get_operand2 (inst
) == REG_PC
)
3597 if (inst_env
->slot_needed
)
3599 inst_env
->invalid
= 1;
3602 /* The instruction has the PC as its target register. */
3603 operand1
= cris_get_quick_value (inst
);
3604 operand2
= inst_env
->reg
[REG_PC
];
3606 /* The quick value is signed, so check if we must do a signed extend. */
3607 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3610 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3612 /* The size should now be dword. */
3613 cris_set_size_to_dword (&inst
);
3615 /* Calculate the PC value after the instruction, i.e. where the
3616 breakpoint should be. */
3617 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3619 inst_env
->slot_needed
= 0;
3620 inst_env
->prefix_found
= 0;
3621 inst_env
->xflag_found
= 0;
3622 inst_env
->disable_interrupt
= 0;
3625 /* Translate op_type to a function and call it. */
3628 cris_gdb_func (struct gdbarch
*gdbarch
, enum cris_op_type op_type
,
3629 unsigned short inst
, inst_env_type
*inst_env
)
3633 case cris_not_implemented_op
:
3634 not_implemented_op (inst
, inst_env
);
3638 abs_op (inst
, inst_env
);
3642 addi_op (inst
, inst_env
);
3646 asr_op (inst
, inst_env
);
3650 asrq_op (inst
, inst_env
);
3653 case cris_ax_ei_setf_op
:
3654 ax_ei_setf_op (inst
, inst_env
);
3657 case cris_bdap_prefix
:
3658 bdap_prefix (inst
, inst_env
);
3661 case cris_biap_prefix
:
3662 biap_prefix (inst
, inst_env
);
3666 break_op (inst
, inst_env
);
3669 case cris_btst_nop_op
:
3670 btst_nop_op (inst
, inst_env
);
3673 case cris_clearf_di_op
:
3674 clearf_di_op (inst
, inst_env
);
3677 case cris_dip_prefix
:
3678 dip_prefix (inst
, inst_env
);
3681 case cris_dstep_logshift_mstep_neg_not_op
:
3682 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3685 case cris_eight_bit_offset_branch_op
:
3686 eight_bit_offset_branch_op (inst
, inst_env
);
3689 case cris_move_mem_to_reg_movem_op
:
3690 move_mem_to_reg_movem_op (inst
, inst_env
);
3693 case cris_move_reg_to_mem_movem_op
:
3694 move_reg_to_mem_movem_op (inst
, inst_env
);
3697 case cris_move_to_preg_op
:
3698 move_to_preg_op (gdbarch
, inst
, inst_env
);
3702 muls_op (inst
, inst_env
);
3706 mulu_op (inst
, inst_env
);
3709 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3710 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3713 case cris_none_reg_mode_clear_test_op
:
3714 none_reg_mode_clear_test_op (inst
, inst_env
);
3717 case cris_none_reg_mode_jump_op
:
3718 none_reg_mode_jump_op (inst
, inst_env
);
3721 case cris_none_reg_mode_move_from_preg_op
:
3722 none_reg_mode_move_from_preg_op (gdbarch
, inst
, inst_env
);
3725 case cris_quick_mode_add_sub_op
:
3726 quick_mode_add_sub_op (inst
, inst_env
);
3729 case cris_quick_mode_and_cmp_move_or_op
:
3730 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3733 case cris_quick_mode_bdap_prefix
:
3734 quick_mode_bdap_prefix (inst
, inst_env
);
3737 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3738 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3741 case cris_reg_mode_clear_op
:
3742 reg_mode_clear_op (inst
, inst_env
);
3745 case cris_reg_mode_jump_op
:
3746 reg_mode_jump_op (inst
, inst_env
);
3749 case cris_reg_mode_move_from_preg_op
:
3750 reg_mode_move_from_preg_op (inst
, inst_env
);
3753 case cris_reg_mode_test_op
:
3754 reg_mode_test_op (inst
, inst_env
);
3758 scc_op (inst
, inst_env
);
3761 case cris_sixteen_bit_offset_branch_op
:
3762 sixteen_bit_offset_branch_op (inst
, inst_env
);
3765 case cris_three_operand_add_sub_cmp_and_or_op
:
3766 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3769 case cris_three_operand_bound_op
:
3770 three_operand_bound_op (inst
, inst_env
);
3773 case cris_two_operand_bound_op
:
3774 two_operand_bound_op (inst
, inst_env
);
3778 xor_op (inst
, inst_env
);
3783 /* This wrapper is to avoid cris_get_assembler being called before
3784 exec_bfd has been set. */
3787 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3789 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3790 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3791 disassembler, even when there is no BFD. Does something like
3792 "gdb; target remote; disassmeble *0x123" work? */
3793 gdb_assert (exec_bfd
!= NULL
);
3794 print_insn
= cris_get_disassembler (exec_bfd
);
3795 gdb_assert (print_insn
!= NULL
);
3796 return print_insn (addr
, info
);
3799 /* Originally from <asm/elf.h>. */
3800 typedef unsigned char cris_elf_greg_t
[4];
3802 /* Same as user_regs_struct struct in <asm/user.h>. */
3803 #define CRISV10_ELF_NGREG 35
3804 typedef cris_elf_greg_t cris_elf_gregset_t
[CRISV10_ELF_NGREG
];
3806 #define CRISV32_ELF_NGREG 32
3807 typedef cris_elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3809 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3812 cris_supply_gregset (struct regcache
*regcache
, cris_elf_gregset_t
*gregsetp
)
3814 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3817 cris_elf_greg_t
*regp
= *gregsetp
;
3819 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3820 knows about the actual size of each register so that's no problem. */
3821 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3823 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3826 if (tdep
->cris_version
== 32)
3828 /* Needed to set pseudo-register PC for CRISv32. */
3829 /* FIXME: If ERP is in a delay slot at this point then the PC will
3830 be wrong. Issue a warning to alert the user. */
3831 regcache_raw_supply (regcache
, gdbarch_pc_regnum (gdbarch
),
3832 (char *)®p
[ERP_REGNUM
]);
3834 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3835 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3839 /* Use a local version of this function to get the correct types for
3840 regsets, until multi-arch core support is ready. */
3843 fetch_core_registers (struct regcache
*regcache
,
3844 char *core_reg_sect
, unsigned core_reg_size
,
3845 int which
, CORE_ADDR reg_addr
)
3847 cris_elf_gregset_t gregset
;
3852 if (core_reg_size
!= sizeof (cris_elf_gregset_t
)
3853 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3855 warning (_("wrong size gregset struct in core file"));
3859 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3860 cris_supply_gregset (regcache
, &gregset
);
3864 /* We've covered all the kinds of registers we know about here,
3865 so this must be something we wouldn't know what to do with
3866 anyway. Just ignore it. */
3871 static struct core_fns cris_elf_core_fns
=
3873 bfd_target_elf_flavour
, /* core_flavour */
3874 default_check_format
, /* check_format */
3875 default_core_sniffer
, /* core_sniffer */
3876 fetch_core_registers
, /* core_read_registers */
3880 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3883 _initialize_cris_tdep (void)
3885 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3887 /* CRIS-specific user-commands. */
3888 add_setshow_zuinteger_cmd ("cris-version", class_support
,
3889 &usr_cmd_cris_version
,
3890 _("Set the current CRIS version."),
3891 _("Show the current CRIS version."),
3893 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3896 NULL
, /* FIXME: i18n: Current CRIS version
3898 &setlist
, &showlist
);
3900 add_setshow_enum_cmd ("cris-mode", class_support
,
3901 cris_modes
, &usr_cmd_cris_mode
,
3902 _("Set the current CRIS mode."),
3903 _("Show the current CRIS mode."),
3905 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3906 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3908 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3909 &setlist
, &showlist
);
3911 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3912 &usr_cmd_cris_dwarf2_cfi
,
3913 _("Set the usage of Dwarf-2 CFI for CRIS."),
3914 _("Show the usage of Dwarf-2 CFI for CRIS."),
3915 _("Set this to \"off\" if using gcc-cris < R59."),
3916 set_cris_dwarf2_cfi
,
3917 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI
3919 &setlist
, &showlist
);
3921 deprecated_add_core_fns (&cris_elf_core_fns
);
3924 /* Prints out all target specific values. */
3927 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3932 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3933 tdep
->cris_version
);
3934 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3936 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3937 tdep
->cris_dwarf2_cfi
);
3942 set_cris_version (char *ignore_args
, int from_tty
,
3943 struct cmd_list_element
*c
)
3945 struct gdbarch_info info
;
3947 usr_cmd_cris_version_valid
= 1;
3949 /* Update the current architecture, if needed. */
3950 gdbarch_info_init (&info
);
3951 if (!gdbarch_update_p (info
))
3952 internal_error (__FILE__
, __LINE__
,
3953 _("cris_gdbarch_update: failed to update architecture."));
3957 set_cris_mode (char *ignore_args
, int from_tty
,
3958 struct cmd_list_element
*c
)
3960 struct gdbarch_info info
;
3962 /* Update the current architecture, if needed. */
3963 gdbarch_info_init (&info
);
3964 if (!gdbarch_update_p (info
))
3965 internal_error (__FILE__
, __LINE__
,
3966 "cris_gdbarch_update: failed to update architecture.");
3970 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
3971 struct cmd_list_element
*c
)
3973 struct gdbarch_info info
;
3975 /* Update the current architecture, if needed. */
3976 gdbarch_info_init (&info
);
3977 if (!gdbarch_update_p (info
))
3978 internal_error (__FILE__
, __LINE__
,
3979 _("cris_gdbarch_update: failed to update architecture."));
3982 static struct gdbarch
*
3983 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3985 struct gdbarch
*gdbarch
;
3986 struct gdbarch_tdep
*tdep
;
3987 unsigned int cris_version
;
3989 if (usr_cmd_cris_version_valid
)
3991 /* Trust the user's CRIS version setting. */
3992 cris_version
= usr_cmd_cris_version
;
3994 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4000 /* Assume it's CRIS version 10. */
4004 /* Make the current settings visible to the user. */
4005 usr_cmd_cris_version
= cris_version
;
4007 /* Find a candidate among the list of pre-declared architectures. */
4008 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4010 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4012 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4013 == usr_cmd_cris_version
)
4014 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4015 == usr_cmd_cris_mode
)
4016 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4017 == usr_cmd_cris_dwarf2_cfi
))
4018 return arches
->gdbarch
;
4021 /* No matching architecture was found. Create a new one. */
4022 tdep
= XNEW (struct gdbarch_tdep
);
4023 gdbarch
= gdbarch_alloc (&info
, tdep
);
4025 tdep
->cris_version
= usr_cmd_cris_version
;
4026 tdep
->cris_mode
= usr_cmd_cris_mode
;
4027 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4029 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4030 switch (info
.byte_order
)
4032 case BFD_ENDIAN_LITTLE
:
4036 case BFD_ENDIAN_BIG
:
4037 /* Cris is always little endian, but the user could have forced
4038 big endian with "set endian". */
4042 internal_error (__FILE__
, __LINE__
,
4043 _("cris_gdbarch_init: unknown byte order in info"));
4046 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4048 set_gdbarch_sp_regnum (gdbarch
, 14);
4050 /* Length of ordinary registers used in push_word and a few other
4051 places. register_size() is the real way to know how big a
4054 set_gdbarch_double_bit (gdbarch
, 64);
4055 /* The default definition of a long double is 2 * gdbarch_double_bit,
4056 which means we have to set this explicitly. */
4057 set_gdbarch_long_double_bit (gdbarch
, 64);
4059 /* The total amount of space needed to store (in an array called registers)
4060 GDB's copy of the machine's register state. Note: We can not use
4061 cris_register_size at this point, since it relies on gdbarch
4063 switch (tdep
->cris_version
)
4071 /* Old versions; not supported. */
4076 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4077 P7 (32 bits), and P15 (32 bits) have been implemented. */
4078 set_gdbarch_pc_regnum (gdbarch
, 15);
4079 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4080 /* There are 32 registers (some of which may not be implemented). */
4081 set_gdbarch_num_regs (gdbarch
, 32);
4082 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4083 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4084 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4086 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4090 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4091 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4092 and pseudo-register PC (32 bits). */
4093 set_gdbarch_pc_regnum (gdbarch
, 32);
4094 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4095 /* 32 registers + pseudo-register PC + 16 support registers. */
4096 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4097 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4099 set_gdbarch_cannot_store_register
4100 (gdbarch
, crisv32_cannot_store_register
);
4101 set_gdbarch_cannot_fetch_register
4102 (gdbarch
, crisv32_cannot_fetch_register
);
4104 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4106 set_gdbarch_single_step_through_delay
4107 (gdbarch
, crisv32_single_step_through_delay
);
4112 /* Unknown version. */
4116 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4117 have the same ABI). */
4118 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4119 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4120 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4121 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4123 /* The stack grows downward. */
4124 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4126 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4128 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4129 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4130 set_gdbarch_dummy_id (gdbarch
, cris_dummy_id
);
4132 if (tdep
->cris_dwarf2_cfi
== 1)
4134 /* Hook in the Dwarf-2 frame sniffer. */
4135 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4136 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4137 dwarf2_append_unwinders (gdbarch
);
4140 if (tdep
->cris_mode
!= cris_mode_guru
)
4142 frame_unwind_append_unwinder (gdbarch
, &cris_sigtramp_frame_unwind
);
4145 frame_unwind_append_unwinder (gdbarch
, &cris_frame_unwind
);
4146 frame_base_set_default (gdbarch
, &cris_frame_base
);
4148 /* Hook in ABI-specific overrides, if they have been registered. */
4149 gdbarch_init_osabi (info
, gdbarch
);
4151 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4152 disassembler, even when there is no BFD. Does something like
4153 "gdb; target remote; disassmeble *0x123" work? */
4154 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);