1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h" /* For struct link_map_offsets. */
47 #include "gdb_string.h"
53 /* There are no floating point registers. Used in gdbserver low-linux.c. */
56 /* There are 16 general registers. */
59 /* There are 16 special registers. */
63 /* Register numbers of various important registers.
64 CRIS_FP_REGNUM Contains address of executing stack frame.
65 STR_REGNUM Contains the address of structure return values.
66 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
67 ARG1_REGNUM Contains the first parameter to a function.
68 ARG2_REGNUM Contains the second parameter to a function.
69 ARG3_REGNUM Contains the third parameter to a function.
70 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
71 SP_REGNUM Contains address of top of stack.
72 PC_REGNUM Contains address of next instruction.
73 SRP_REGNUM Subroutine return pointer register.
74 BRP_REGNUM Breakpoint return pointer register. */
78 /* Enums with respect to the general registers, valid for all
88 /* Enums with respect to the special registers, some of which may not be
89 applicable to all CRIS versions. */
107 extern const struct cris_spec_reg cris_spec_regs
[];
109 /* CRIS version, set via the user command 'set cris-version'. Affects
110 register names and sizes.*/
111 static int usr_cmd_cris_version
;
113 /* Indicates whether to trust the above variable. */
114 static int usr_cmd_cris_version_valid
= 0;
116 /* CRIS mode, set via the user command 'set cris-mode'. Affects availability
117 of some registers. */
118 static const char *usr_cmd_cris_mode
;
120 /* Indicates whether to trust the above variable. */
121 static int usr_cmd_cris_mode_valid
= 0;
123 static const char CRIS_MODE_USER
[] = "CRIS_MODE_USER";
124 static const char CRIS_MODE_SUPERVISOR
[] = "CRIS_MODE_SUPERVISOR";
125 static const char *cris_mode_enums
[] =
128 CRIS_MODE_SUPERVISOR
,
132 /* CRIS architecture specific information. */
136 const char *cris_mode
;
139 /* Functions for accessing target dependent data. */
144 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
150 return (gdbarch_tdep (current_gdbarch
)->cris_mode
);
153 struct cris_unwind_cache
155 /* The previous frame's inner most stack address. Used as this
156 frame ID's stack_addr. */
158 /* The frame's base, optionally used by the high-level debug info. */
161 /* How far the SP and r8 (FP) have been offset from the start of
162 the stack frame (as defined by the previous frame's stack
168 /* From old frame_extra_info struct. */
172 /* Table indicating the location of each and every register. */
173 struct trad_frame_saved_reg
*saved_regs
;
176 /* The instruction environment needed to find single-step breakpoints. */
178 struct instruction_environment
180 unsigned long reg
[NUM_GENREGS
];
181 unsigned long preg
[NUM_SPECREGS
];
182 unsigned long branch_break_address
;
183 unsigned long delay_slot_pc
;
184 unsigned long prefix_value
;
189 int delay_slot_pc_active
;
191 int disable_interrupt
;
194 /* Save old breakpoints in order to restore the state before a single_step.
195 At most, two breakpoints will have to be remembered. */
197 char binsn_quantum
[BREAKPOINT_MAX
];
198 static binsn_quantum break_mem
[2];
199 static CORE_ADDR next_pc
= 0;
200 static CORE_ADDR branch_target_address
= 0;
201 static unsigned char branch_break_inserted
= 0;
203 /* Machine-dependencies in CRIS for opcodes. */
205 /* Instruction sizes. */
206 enum cris_instruction_sizes
213 /* Addressing modes. */
214 enum cris_addressing_modes
221 /* Prefix addressing modes. */
222 enum cris_prefix_addressing_modes
224 PREFIX_INDEX_MODE
= 2,
225 PREFIX_ASSIGN_MODE
= 3,
227 /* Handle immediate byte offset addressing mode prefix format. */
228 PREFIX_OFFSET_MODE
= 2
231 /* Masks for opcodes. */
232 enum cris_opcode_masks
234 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
235 SIGNED_EXTEND_BIT_MASK
= 0x2,
236 SIGNED_BYTE_MASK
= 0x80,
237 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
238 SIGNED_WORD_MASK
= 0x8000,
239 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
240 SIGNED_DWORD_MASK
= 0x80000000,
241 SIGNED_QUICK_VALUE_MASK
= 0x20,
242 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
245 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
253 cris_get_operand2 (unsigned short insn
)
255 return ((insn
& 0xF000) >> 12);
259 cris_get_mode (unsigned short insn
)
261 return ((insn
& 0x0C00) >> 10);
265 cris_get_opcode (unsigned short insn
)
267 return ((insn
& 0x03C0) >> 6);
271 cris_get_size (unsigned short insn
)
273 return ((insn
& 0x0030) >> 4);
277 cris_get_operand1 (unsigned short insn
)
279 return (insn
& 0x000F);
282 /* Additional functions in order to handle opcodes. */
285 cris_get_quick_value (unsigned short insn
)
287 return (insn
& 0x003F);
291 cris_get_bdap_quick_offset (unsigned short insn
)
293 return (insn
& 0x00FF);
297 cris_get_branch_short_offset (unsigned short insn
)
299 return (insn
& 0x00FF);
303 cris_get_asr_shift_steps (unsigned long value
)
305 return (value
& 0x3F);
309 cris_get_clear_size (unsigned short insn
)
311 return ((insn
) & 0xC000);
315 cris_is_signed_extend_bit_on (unsigned short insn
)
317 return (((insn
) & 0x20) == 0x20);
321 cris_is_xflag_bit_on (unsigned short insn
)
323 return (((insn
) & 0x1000) == 0x1000);
327 cris_set_size_to_dword (unsigned short *insn
)
334 cris_get_signed_offset (unsigned short insn
)
336 return ((signed char) (insn
& 0x00FF));
339 /* Calls an op function given the op-type, working on the insn and the
341 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
343 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
344 struct gdbarch_list
*);
346 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
348 static void cris_version_update (char *ignore_args
, int from_tty
,
349 struct cmd_list_element
*c
);
351 static void cris_mode_update (char *ignore_args
, int from_tty
,
352 struct cmd_list_element
*c
);
354 static CORE_ADDR
bfd_lookup_symbol (bfd
*, const char *);
356 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
357 struct frame_info
*next_frame
,
358 struct cris_unwind_cache
*info
);
360 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
361 struct frame_info
*next_frame
);
363 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
364 struct frame_info
*next_frame
);
366 /* When arguments must be pushed onto the stack, they go on in reverse
367 order. The below implements a FILO (stack) to do this. */
369 /* Borrowed from d10v-tdep.c. */
374 struct stack_item
*prev
;
378 static struct stack_item
*
379 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
381 struct stack_item
*si
;
382 si
= xmalloc (sizeof (struct stack_item
));
383 si
->data
= xmalloc (len
);
386 memcpy (si
->data
, contents
, len
);
390 static struct stack_item
*
391 pop_stack_item (struct stack_item
*si
)
393 struct stack_item
*dead
= si
;
400 /* Put here the code to store, into fi->saved_regs, the addresses of
401 the saved registers of frame described by FRAME_INFO. This
402 includes special registers such as pc and fp saved in special ways
403 in the stack frame. sp is even more special: the address we return
404 for it IS the sp for the next frame. */
406 struct cris_unwind_cache
*
407 cris_frame_unwind_cache (struct frame_info
*next_frame
,
408 void **this_prologue_cache
)
411 struct cris_unwind_cache
*info
;
414 if ((*this_prologue_cache
))
415 return (*this_prologue_cache
);
417 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
418 (*this_prologue_cache
) = info
;
419 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
421 /* Zero all fields. */
427 info
->uses_frame
= 0;
429 info
->leaf_function
= 0;
431 /* Prologue analysis does the rest... */
432 cris_scan_prologue (frame_func_unwind (next_frame
), next_frame
, info
);
437 /* Given a GDB frame, determine the address of the calling function's
438 frame. This will be used to create a new GDB frame struct. */
441 cris_frame_this_id (struct frame_info
*next_frame
,
442 void **this_prologue_cache
,
443 struct frame_id
*this_id
)
445 struct cris_unwind_cache
*info
446 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
451 /* The FUNC is easy. */
452 func
= frame_func_unwind (next_frame
);
454 /* Hopefully the prologue analysis either correctly determined the
455 frame's base (which is the SP from the previous frame), or set
456 that base to "NULL". */
457 base
= info
->prev_sp
;
461 id
= frame_id_build (base
, func
);
467 cris_frame_prev_register (struct frame_info
*next_frame
,
468 void **this_prologue_cache
,
469 int regnum
, int *optimizedp
,
470 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
471 int *realnump
, void *bufferp
)
473 struct cris_unwind_cache
*info
474 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
475 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
476 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
479 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
480 dummy frame. The frame ID's base needs to match the TOS value
481 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
484 static struct frame_id
485 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
487 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
488 frame_pc_unwind (next_frame
));
492 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
494 /* Align to the size of an instruction (so that they can safely be
495 pushed onto the stack). */
500 cris_push_dummy_code (struct gdbarch
*gdbarch
,
501 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
502 struct value
**args
, int nargs
,
503 struct type
*value_type
,
504 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
506 /* Allocate space sufficient for a breakpoint. */
508 /* Store the address of that breakpoint */
510 /* CRIS always starts the call at the callee's entry point. */
516 cris_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
517 struct regcache
*regcache
, CORE_ADDR bp_addr
,
518 int nargs
, struct value
**args
, CORE_ADDR sp
,
519 int struct_return
, CORE_ADDR struct_addr
)
528 /* The function's arguments and memory allocated by gdb for the arguments to
529 point at reside in separate areas on the stack.
530 Both frame pointers grow toward higher addresses. */
534 struct stack_item
*si
= NULL
;
536 /* Push the return address. */
537 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
539 /* Are we returning a value using a structure return or a normal value
540 return? struct_addr is the address of the reserved space for the return
541 structure to be written on the stack. */
544 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
547 /* Now load as many as possible of the first arguments into registers,
548 and push the rest onto the stack. */
549 argreg
= ARG1_REGNUM
;
552 for (argnum
= 0; argnum
< nargs
; argnum
++)
559 len
= TYPE_LENGTH (VALUE_TYPE (args
[argnum
]));
560 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
562 /* How may registers worth of storage do we need for this argument? */
563 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
565 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
567 /* Data passed by value. Fits in available register(s). */
568 for (i
= 0; i
< reg_demand
; i
++)
570 regcache_cooked_write_unsigned (regcache
, argreg
,
571 *(unsigned long *) val
);
576 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
578 /* Data passed by value. Does not fit in available register(s).
579 Use the register(s) first, then the stack. */
580 for (i
= 0; i
< reg_demand
; i
++)
582 if (argreg
<= ARG4_REGNUM
)
584 regcache_cooked_write_unsigned (regcache
, argreg
,
585 *(unsigned long *) val
);
591 /* Push item for later so that pushed arguments
592 come in the right order. */
593 si
= push_stack_item (si
, val
, 4);
598 else if (len
> (2 * 4))
601 internal_error (__FILE__
, __LINE__
, "We don't do this");
605 /* Data passed by value. No available registers. Put it on
607 si
= push_stack_item (si
, val
, len
);
613 /* fp_arg must be word-aligned (i.e., don't += len) to match
614 the function prologue. */
615 sp
= (sp
- si
->len
) & ~3;
616 write_memory (sp
, si
->data
, si
->len
);
617 si
= pop_stack_item (si
);
620 /* Finally, update the SP register. */
621 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
626 static const struct frame_unwind cris_frame_unwind
= {
629 cris_frame_prev_register
632 const struct frame_unwind
*
633 cris_frame_sniffer (struct frame_info
*next_frame
)
635 return &cris_frame_unwind
;
639 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
641 struct cris_unwind_cache
*info
642 = cris_frame_unwind_cache (next_frame
, this_cache
);
646 static const struct frame_base cris_frame_base
= {
648 cris_frame_base_address
,
649 cris_frame_base_address
,
650 cris_frame_base_address
653 /* Frames information. The definition of the struct frame_info is
657 enum frame_type type;
661 If the compilation option -fno-omit-frame-pointer is present the
662 variable frame will be set to the content of R8 which is the frame
665 The variable pc contains the address where execution is performed
666 in the present frame. The innermost frame contains the current content
667 of the register PC. All other frames contain the content of the
668 register PC in the next frame.
670 The variable `type' indicates the frame's type: normal, SIGTRAMP
671 (associated with a signal handler), dummy (associated with a dummy
674 The variable return_pc contains the address where execution should be
675 resumed when the present frame has finished, the return address.
677 The variable leaf_function is 1 if the return address is in the register
678 SRP, and 0 if it is on the stack.
680 Prologue instructions C-code.
681 The prologue may consist of (-fno-omit-frame-pointer)
685 move.d sp,r8 move.d sp,r8
687 movem rY,[sp] movem rY,[sp]
688 move.S rZ,[r8-U] move.S rZ,[r8-U]
690 where 1 is a non-terminal function, and 2 is a leaf-function.
692 Note that this assumption is extremely brittle, and will break at the
693 slightest change in GCC's prologue.
695 If local variables are declared or register contents are saved on stack
696 the subq-instruction will be present with X as the number of bytes
697 needed for storage. The reshuffle with respect to r8 may be performed
698 with any size S (b, w, d) and any of the general registers Z={0..13}.
699 The offset U should be representable by a signed 8-bit value in all cases.
700 Thus, the prefix word is assumed to be immediate byte offset mode followed
701 by another word containing the instruction.
710 Prologue instructions C++-code.
711 Case 1) and 2) in the C-code may be followed by
717 move.S [r8+U],rZ ; P4
719 if any of the call parameters are stored. The host expects these
720 instructions to be executed in order to get the call parameters right. */
722 /* Examine the prologue of a function. The variable ip is the address of
723 the first instruction of the prologue. The variable limit is the address
724 of the first instruction after the prologue. The variable fi contains the
725 information in struct frame_info. The variable frameless_p controls whether
726 the entire prologue is examined (0) or just enough instructions to
727 determine that it is a prologue (1). */
730 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
731 struct cris_unwind_cache
*info
)
733 /* Present instruction. */
736 /* Next instruction, lookahead. */
737 unsigned short insn_next
;
740 /* Is there a push fp? */
743 /* Number of byte on stack used for local variables and movem. */
746 /* Highest register number in a movem. */
749 /* move.d r<source_register>,rS */
750 short source_register
;
755 /* This frame is with respect to a leaf until a push srp is found. */
758 info
->leaf_function
= 1;
761 /* Assume nothing on stack. */
765 /* If we were called without a next_frame, that means we were called
766 from cris_skip_prologue which already tried to find the end of the
767 prologue through the symbol information. 64 instructions past current
768 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
769 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
771 /* Find the prologue instructions. */
774 insn
= read_memory_unsigned_integer (pc
, 2);
778 /* push <reg> 32 bit instruction */
779 insn_next
= read_memory_unsigned_integer (pc
, 2);
781 regno
= cris_get_operand2 (insn_next
);
784 info
->sp_offset
+= 4;
786 /* This check, meant to recognize srp, used to be regno ==
787 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
788 if (insn_next
== 0xBE7E)
792 info
->leaf_function
= 0;
795 else if (insn_next
== 0x8FEE)
800 info
->r8_offset
= info
->sp_offset
;
804 else if (insn
== 0x866E)
809 info
->uses_frame
= 1;
813 else if (cris_get_operand2 (insn
) == SP_REGNUM
814 && cris_get_mode (insn
) == 0x0000
815 && cris_get_opcode (insn
) == 0x000A)
820 info
->sp_offset
+= cris_get_quick_value (insn
);
823 else if (cris_get_mode (insn
) == 0x0002
824 && cris_get_opcode (insn
) == 0x000F
825 && cris_get_size (insn
) == 0x0003
826 && cris_get_operand1 (insn
) == SP_REGNUM
)
828 /* movem r<regsave>,[sp] */
829 regsave
= cris_get_operand2 (insn
);
831 else if (cris_get_operand2 (insn
) == SP_REGNUM
832 && ((insn
& 0x0F00) >> 8) == 0x0001
833 && (cris_get_signed_offset (insn
) < 0))
835 /* Immediate byte offset addressing prefix word with sp as base
836 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
837 is between 64 and 128.
838 movem r<regsave>,[sp=sp-<val>] */
841 info
->sp_offset
+= -cris_get_signed_offset (insn
);
843 insn_next
= read_memory_unsigned_integer (pc
, 2);
845 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
846 && cris_get_opcode (insn_next
) == 0x000F
847 && cris_get_size (insn_next
) == 0x0003
848 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
850 regsave
= cris_get_operand2 (insn_next
);
854 /* The prologue ended before the limit was reached. */
859 else if (cris_get_mode (insn
) == 0x0001
860 && cris_get_opcode (insn
) == 0x0009
861 && cris_get_size (insn
) == 0x0002)
863 /* move.d r<10..13>,r<0..15> */
864 source_register
= cris_get_operand1 (insn
);
866 /* FIXME? In the glibc solibs, the prologue might contain something
867 like (this example taken from relocate_doit):
870 which isn't covered by the source_register check below. Question
871 is whether to add a check for this combo, or make better use of
872 the limit variable instead. */
873 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
875 /* The prologue ended before the limit was reached. */
880 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
881 /* The size is a fixed-size. */
882 && ((insn
& 0x0F00) >> 8) == 0x0001
883 /* A negative offset. */
884 && (cris_get_signed_offset (insn
) < 0))
886 /* move.S rZ,[r8-U] (?) */
887 insn_next
= read_memory_unsigned_integer (pc
, 2);
889 regno
= cris_get_operand2 (insn_next
);
890 if ((regno
>= 0 && regno
< SP_REGNUM
)
891 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
892 && cris_get_opcode (insn_next
) == 0x000F)
894 /* move.S rZ,[r8-U] */
899 /* The prologue ended before the limit was reached. */
904 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
905 /* The size is a fixed-size. */
906 && ((insn
& 0x0F00) >> 8) == 0x0001
907 /* A positive offset. */
908 && (cris_get_signed_offset (insn
) > 0))
910 /* move.S [r8+U],rZ (?) */
911 insn_next
= read_memory_unsigned_integer (pc
, 2);
913 regno
= cris_get_operand2 (insn_next
);
914 if ((regno
>= 0 && regno
< SP_REGNUM
)
915 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
916 && cris_get_opcode (insn_next
) == 0x0009
917 && cris_get_operand1 (insn_next
) == regno
)
919 /* move.S [r8+U],rZ */
924 /* The prologue ended before the limit was reached. */
931 /* The prologue ended before the limit was reached. */
937 /* We only want to know the end of the prologue when next_frame and info
938 are NULL (called from cris_skip_prologue i.e.). */
939 if (next_frame
== NULL
&& info
== NULL
)
944 info
->size
= info
->sp_offset
;
946 /* Compute the previous frame's stack pointer (which is also the
947 frame's ID's stack address), and this frame's base pointer. */
948 if (info
->uses_frame
)
951 /* The SP was moved to the FP. This indicates that a new frame
952 was created. Get THIS frame's FP value by unwinding it from
954 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
956 info
->base
= this_base
;
957 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
959 /* The FP points at the last saved register. Adjust the FP back
960 to before the first saved register giving the SP. */
961 info
->prev_sp
= info
->base
+ info
->r8_offset
;
966 /* Assume that the FP is this frame's SP but with that pushed
967 stack space added back. */
968 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
969 info
->base
= this_base
;
970 info
->prev_sp
= info
->base
+ info
->size
;
973 /* Calculate the addresses for the saved registers on the stack. */
974 /* FIXME: The address calculation should really be done on the fly while
975 we're analyzing the prologue (we only hold one regsave value as it is
977 val
= info
->sp_offset
;
979 for (regno
= regsave
; regno
>= 0; regno
--)
981 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
985 /* The previous frame's SP needed to be computed. Save the computed
987 trad_frame_set_value (info
->saved_regs
, SP_REGNUM
, info
->prev_sp
);
989 if (!info
->leaf_function
)
991 /* SRP saved on the stack. But where? */
992 if (info
->r8_offset
== 0)
994 /* R8 not pushed yet. */
995 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
999 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1000 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1004 /* The PC is found in SRP (the actual register or located on the stack). */
1005 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1010 /* Advance pc beyond any function entry prologue instructions at pc
1011 to reach some "real" code. */
1013 /* Given a PC value corresponding to the start of a function, return the PC
1014 of the first instruction after the function prologue. */
1017 cris_skip_prologue (CORE_ADDR pc
)
1019 CORE_ADDR func_addr
, func_end
;
1020 struct symtab_and_line sal
;
1021 CORE_ADDR pc_after_prologue
;
1023 /* If we have line debugging information, then the end of the prologue
1024 should the first assembly instruction of the first source line. */
1025 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1027 sal
= find_pc_line (func_addr
, 0);
1028 if (sal
.end
> 0 && sal
.end
< func_end
)
1032 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1033 return pc_after_prologue
;
1037 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1040 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1045 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1048 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &sp
);
1052 /* Use the program counter to determine the contents and size of a breakpoint
1053 instruction. It returns a pointer to a string of bytes that encode a
1054 breakpoint instruction, stores the length of the string to *lenptr, and
1055 adjusts pcptr (if necessary) to point to the actual memory location where
1056 the breakpoint should be inserted. */
1058 static const unsigned char *
1059 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1061 static unsigned char break_insn
[] = {0x38, 0xe9};
1067 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1071 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1073 int version
= cris_version ();
1075 switch (spec_reg
.applicable_version
)
1077 case cris_ver_version_all
:
1079 case cris_ver_warning
:
1080 /* Indeterminate/obsolete. */
1083 /* Simulator only. */
1086 return (version
>= 0 && version
<= 3);
1088 return (version
>= 3);
1090 return (version
== 8 || version
== 9);
1092 return (version
>= 8);
1094 return (version
>= 10);
1096 /* Invalid cris version. */
1101 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1102 register, -1 for an invalid register. */
1105 cris_register_size (int regno
)
1110 if (regno
>= 0 && regno
< NUM_GENREGS
)
1112 /* General registers (R0 - R15) are 32 bits. */
1115 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1117 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1118 Adjust regno accordingly. */
1119 spec_regno
= regno
- NUM_GENREGS
;
1121 /* The entries in cris_spec_regs are stored in register number order,
1122 which means we can shortcut into the array when searching it. */
1123 for (i
= spec_regno
; cris_spec_regs
[i
].name
!= NULL
; i
++)
1125 if (cris_spec_regs
[i
].number
== spec_regno
1126 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1127 /* Go with the first applicable register. */
1128 return cris_spec_regs
[i
].reg_size
;
1130 /* Special register not applicable to this CRIS version. */
1135 /* Invalid register. */
1140 /* Nonzero if regno should not be fetched from the target. This is the case
1141 for unimplemented (size 0) and non-existant registers. */
1144 cris_cannot_fetch_register (int regno
)
1146 return ((regno
< 0 || regno
>= NUM_REGS
)
1147 || (cris_register_size (regno
) == 0));
1150 /* Nonzero if regno should not be written to the target, for various
1154 cris_cannot_store_register (int regno
)
1156 /* There are three kinds of registers we refuse to write to.
1157 1. Those that not implemented.
1158 2. Those that are read-only (depends on the processor mode).
1159 3. Those registers to which a write has no effect.
1162 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1163 /* Not implemented. */
1166 else if (regno
== VR_REGNUM
)
1170 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1171 /* Writing has no effect. */
1174 else if (cris_mode () == CRIS_MODE_USER
)
1176 if (regno
== IBR_REGNUM
|| regno
== BAR_REGNUM
|| regno
== BRP_REGNUM
1177 || regno
== IRP_REGNUM
)
1178 /* Read-only in user mode. */
1185 /* Returns the register offset for the first byte of register regno's space
1186 in the saved register state. Returns -1 for an invalid or unimplemented
1190 cris_register_offset (int regno
)
1196 if (regno
>= 0 && regno
< NUM_REGS
)
1198 /* FIXME: The offsets should be cached and calculated only once,
1199 when the architecture being debugged has changed. */
1200 for (i
= 0; i
< regno
; i
++)
1201 offset
+= cris_register_size (i
);
1207 /* Invalid register. */
1212 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1213 of data in register regno. */
1215 static struct type
*
1216 cris_register_virtual_type (int regno
)
1218 if (regno
== SP_REGNUM
|| regno
== PC_REGNUM
1219 || (regno
> P8_REGNUM
&& regno
< USP_REGNUM
))
1221 /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */
1222 return lookup_pointer_type (builtin_type_void
);
1224 else if (regno
== P8_REGNUM
|| regno
== USP_REGNUM
1225 || (regno
>= 0 && regno
< SP_REGNUM
))
1227 /* R0 - R13, P8, P15 */
1228 return builtin_type_unsigned_long
;
1230 else if (regno
> P3_REGNUM
&& regno
< P8_REGNUM
)
1232 /* P4, CCR, DCR0, DCR1 */
1233 return builtin_type_unsigned_short
;
1235 else if (regno
> PC_REGNUM
&& regno
< P4_REGNUM
)
1237 /* P0, P1, P2, P3 */
1238 return builtin_type_unsigned_char
;
1242 /* Invalid register. */
1243 return builtin_type_void
;
1247 /* Stores a function return value of type type, where valbuf is the address
1248 of the value to be stored. */
1250 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1253 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1257 int len
= TYPE_LENGTH (type
);
1261 /* Put the return value in R10. */
1262 val
= extract_unsigned_integer (valbuf
, len
);
1263 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1267 /* Put the return value in R10 and R11. */
1268 val
= extract_unsigned_integer (valbuf
, 4);
1269 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1270 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1271 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1274 error ("cris_store_return_value: type length too large.");
1277 /* Return the name of register regno as a string. Return NULL for an invalid or
1278 unimplemented register. */
1281 cris_register_name (int regno
)
1283 static char *cris_genreg_names
[] =
1284 { "r0", "r1", "r2", "r3", \
1285 "r4", "r5", "r6", "r7", \
1286 "r8", "r9", "r10", "r11", \
1287 "r12", "r13", "sp", "pc" };
1292 if (regno
>= 0 && regno
< NUM_GENREGS
)
1294 /* General register. */
1295 return cris_genreg_names
[regno
];
1297 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1299 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1300 Adjust regno accordingly. */
1301 spec_regno
= regno
- NUM_GENREGS
;
1303 /* The entries in cris_spec_regs are stored in register number order,
1304 which means we can shortcut into the array when searching it. */
1305 for (i
= spec_regno
; cris_spec_regs
[i
].name
!= NULL
; i
++)
1307 if (cris_spec_regs
[i
].number
== spec_regno
1308 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1309 /* Go with the first applicable register. */
1310 return cris_spec_regs
[i
].name
;
1312 /* Special register not applicable to this CRIS version. */
1317 /* Invalid register. */
1323 cris_register_bytes_ok (long bytes
)
1325 return (bytes
== DEPRECATED_REGISTER_BYTES
);
1328 /* Extract from an array regbuf containing the raw register state a function
1329 return value of type type, and copy that, in virtual format, into
1332 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1335 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1339 int len
= TYPE_LENGTH (type
);
1343 /* Get the return value from R10. */
1344 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1345 store_unsigned_integer (valbuf
, len
, val
);
1349 /* Get the return value from R10 and R11. */
1350 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1351 store_unsigned_integer (valbuf
, 4, val
);
1352 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1353 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1356 error ("cris_extract_return_value: type length too large");
1359 /* Handle the CRIS return value convention. */
1361 static enum return_value_convention
1362 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1363 struct regcache
*regcache
, void *readbuf
,
1364 const void *writebuf
)
1366 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1367 || TYPE_CODE (type
) == TYPE_CODE_UNION
1368 || TYPE_LENGTH (type
) > 8)
1369 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1370 goes on the stack. */
1371 return RETURN_VALUE_STRUCT_CONVENTION
;
1374 cris_extract_return_value (type
, regcache
, readbuf
);
1376 cris_store_return_value (type
, regcache
, writebuf
);
1378 return RETURN_VALUE_REGISTER_CONVENTION
;
1381 /* Returns 1 if the given type will be passed by pointer rather than
1384 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1388 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1390 return (TYPE_LENGTH (type
) > 8);
1393 /* Calculates a value that measures how good inst_args constraints an
1394 instruction. It stems from cris_constraint, found in cris-dis.c. */
1397 constraint (unsigned int insn
, const signed char *inst_args
,
1398 inst_env_type
*inst_env
)
1403 const char *s
= inst_args
;
1409 if ((insn
& 0x30) == 0x30)
1414 /* A prefix operand. */
1415 if (inst_env
->prefix_found
)
1421 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1422 valid "push" size. In case of special register, it may be != 4. */
1423 if (inst_env
->prefix_found
)
1429 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1437 tmp
= (insn
>> 0xC) & 0xF;
1439 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1441 /* Since we match four bits, we will give a value of
1442 4 - 1 = 3 in a match. If there is a corresponding
1443 exact match of a special register in another pattern, it
1444 will get a value of 4, which will be higher. This should
1445 be correct in that an exact pattern would match better that
1447 Note that there is a reason for not returning zero; the
1448 pattern for "clear" is partly matched in the bit-pattern
1449 (the two lower bits must be zero), while the bit-pattern
1450 for a move from a special register is matched in the
1451 register constraint.
1452 This also means we will will have a race condition if
1453 there is a partly match in three bits in the bit pattern. */
1454 if (tmp
== cris_spec_regs
[i
].number
)
1461 if (cris_spec_regs
[i
].name
== NULL
)
1468 /* Returns the number of bits set in the variable value. */
1471 number_of_bits (unsigned int value
)
1473 int number_of_bits
= 0;
1477 number_of_bits
+= 1;
1478 value
&= (value
- 1);
1480 return number_of_bits
;
1483 /* Finds the address that should contain the single step breakpoint(s).
1484 It stems from code in cris-dis.c. */
1487 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
1490 int max_level_of_match
= -1;
1491 int max_matched
= -1;
1494 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
1496 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
1497 && ((cris_opcodes
[i
].lose
& insn
) == 0))
1499 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
1500 if (level_of_match
>= 0)
1503 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
1504 if (level_of_match
> max_level_of_match
)
1507 max_level_of_match
= level_of_match
;
1508 if (level_of_match
== 16)
1510 /* All bits matched, cannot find better. */
1520 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1521 actually an internal error. */
1524 find_step_target (inst_env_type
*inst_env
)
1528 unsigned short insn
;
1530 /* Create a local register image and set the initial state. */
1531 for (i
= 0; i
< NUM_GENREGS
; i
++)
1533 inst_env
->reg
[i
] = (unsigned long) read_register (i
);
1535 offset
= NUM_GENREGS
;
1536 for (i
= 0; i
< NUM_SPECREGS
; i
++)
1538 inst_env
->preg
[i
] = (unsigned long) read_register (offset
+ i
);
1540 inst_env
->branch_found
= 0;
1541 inst_env
->slot_needed
= 0;
1542 inst_env
->delay_slot_pc_active
= 0;
1543 inst_env
->prefix_found
= 0;
1544 inst_env
->invalid
= 0;
1545 inst_env
->xflag_found
= 0;
1546 inst_env
->disable_interrupt
= 0;
1548 /* Look for a step target. */
1551 /* Read an instruction from the client. */
1552 insn
= read_memory_unsigned_integer (inst_env
->reg
[PC_REGNUM
], 2);
1554 /* If the instruction is not in a delay slot the new content of the
1555 PC is [PC] + 2. If the instruction is in a delay slot it is not
1556 that simple. Since a instruction in a delay slot cannot change
1557 the content of the PC, it does not matter what value PC will have.
1558 Just make sure it is a valid instruction. */
1559 if (!inst_env
->delay_slot_pc_active
)
1561 inst_env
->reg
[PC_REGNUM
] += 2;
1565 inst_env
->delay_slot_pc_active
= 0;
1566 inst_env
->reg
[PC_REGNUM
] = inst_env
->delay_slot_pc
;
1568 /* Analyse the present instruction. */
1569 i
= find_cris_op (insn
, inst_env
);
1572 inst_env
->invalid
= 1;
1576 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
1578 } while (!inst_env
->invalid
1579 && (inst_env
->prefix_found
|| inst_env
->xflag_found
1580 || inst_env
->slot_needed
));
1584 /* There is no hardware single-step support. The function find_step_target
1585 digs through the opcodes in order to find all possible targets.
1586 Either one ordinary target or two targets for branches may be found. */
1589 cris_software_single_step (enum target_signal ignore
, int insert_breakpoints
)
1591 inst_env_type inst_env
;
1593 if (insert_breakpoints
)
1595 /* Analyse the present instruction environment and insert
1597 int status
= find_step_target (&inst_env
);
1600 /* Could not find a target. FIXME: Should do something. */
1604 /* Insert at most two breakpoints. One for the next PC content
1605 and possibly another one for a branch, jump, etc. */
1606 next_pc
= (CORE_ADDR
) inst_env
.reg
[PC_REGNUM
];
1607 target_insert_breakpoint (next_pc
, break_mem
[0]);
1608 if (inst_env
.branch_found
1609 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
1611 branch_target_address
=
1612 (CORE_ADDR
) inst_env
.branch_break_address
;
1613 target_insert_breakpoint (branch_target_address
, break_mem
[1]);
1614 branch_break_inserted
= 1;
1620 /* Remove breakpoints. */
1621 target_remove_breakpoint (next_pc
, break_mem
[0]);
1622 if (branch_break_inserted
)
1624 target_remove_breakpoint (branch_target_address
, break_mem
[1]);
1625 branch_break_inserted
= 0;
1630 /* Calculates the prefix value for quick offset addressing mode. */
1633 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1635 /* It's invalid to be in a delay slot. You can't have a prefix to this
1636 instruction (not 100% sure). */
1637 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1639 inst_env
->invalid
= 1;
1643 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
1644 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
1646 /* A prefix doesn't change the xflag_found. But the rest of the flags
1648 inst_env
->slot_needed
= 0;
1649 inst_env
->prefix_found
= 1;
1652 /* Updates the autoincrement register. The size of the increment is derived
1653 from the size of the operation. The PC is always kept aligned on even
1657 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
1659 if (size
== INST_BYTE_SIZE
)
1661 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
1663 /* The PC must be word aligned, so increase the PC with one
1664 word even if the size is byte. */
1665 if (cris_get_operand1 (inst
) == REG_PC
)
1667 inst_env
->reg
[REG_PC
] += 1;
1670 else if (size
== INST_WORD_SIZE
)
1672 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
1674 else if (size
== INST_DWORD_SIZE
)
1676 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
1681 inst_env
->invalid
= 1;
1685 /* Just a forward declaration. */
1687 static unsigned long get_data_from_address (unsigned short *inst
,
1690 /* Calculates the prefix value for the general case of offset addressing
1694 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1699 /* It's invalid to be in a delay slot. */
1700 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1702 inst_env
->invalid
= 1;
1706 /* The calculation of prefix_value used to be after process_autoincrement,
1707 but that fails for an instruction such as jsr [$r0+12] which is encoded
1708 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
1709 mustn't be incremented until we have read it and what it points at. */
1710 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
1712 /* The offset is an indirection of the contents of the operand1 register. */
1713 inst_env
->prefix_value
+=
1714 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
1716 if (cris_get_mode (inst
) == AUTOINC_MODE
)
1718 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
1721 /* A prefix doesn't change the xflag_found. But the rest of the flags
1723 inst_env
->slot_needed
= 0;
1724 inst_env
->prefix_found
= 1;
1727 /* Calculates the prefix value for the index addressing mode. */
1730 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1732 /* It's invalid to be in a delay slot. I can't see that it's possible to
1733 have a prefix to this instruction. So I will treat this as invalid. */
1734 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1736 inst_env
->invalid
= 1;
1740 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
1742 /* The offset is the operand2 value shifted the size of the instruction
1744 inst_env
->prefix_value
+=
1745 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
1747 /* If the PC is operand1 (base) the address used is the address after
1748 the main instruction, i.e. address + 2 (the PC is already compensated
1749 for the prefix operation). */
1750 if (cris_get_operand1 (inst
) == REG_PC
)
1752 inst_env
->prefix_value
+= 2;
1755 /* A prefix doesn't change the xflag_found. But the rest of the flags
1757 inst_env
->slot_needed
= 0;
1758 inst_env
->xflag_found
= 0;
1759 inst_env
->prefix_found
= 1;
1762 /* Calculates the prefix value for the double indirect addressing mode. */
1765 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1770 /* It's invalid to be in a delay slot. */
1771 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1773 inst_env
->invalid
= 1;
1777 /* The prefix value is one dereference of the contents of the operand1
1779 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
1780 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
1782 /* Check if the mode is autoincrement. */
1783 if (cris_get_mode (inst
) == AUTOINC_MODE
)
1785 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
1788 /* A prefix doesn't change the xflag_found. But the rest of the flags
1790 inst_env
->slot_needed
= 0;
1791 inst_env
->xflag_found
= 0;
1792 inst_env
->prefix_found
= 1;
1795 /* Finds the destination for a branch with 8-bits offset. */
1798 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
1803 /* If we have a prefix or are in a delay slot it's bad. */
1804 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1806 inst_env
->invalid
= 1;
1810 /* We have a branch, find out where the branch will land. */
1811 offset
= cris_get_branch_short_offset (inst
);
1813 /* Check if the offset is signed. */
1814 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
1819 /* The offset ends with the sign bit, set it to zero. The address
1820 should always be word aligned. */
1821 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
1823 inst_env
->branch_found
= 1;
1824 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
1826 inst_env
->slot_needed
= 1;
1827 inst_env
->prefix_found
= 0;
1828 inst_env
->xflag_found
= 0;
1829 inst_env
->disable_interrupt
= 1;
1832 /* Finds the destination for a branch with 16-bits offset. */
1835 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
1839 /* If we have a prefix or is in a delay slot it's bad. */
1840 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1842 inst_env
->invalid
= 1;
1846 /* We have a branch, find out the offset for the branch. */
1847 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
1849 /* The instruction is one word longer than normal, so add one word
1851 inst_env
->reg
[REG_PC
] += 2;
1853 inst_env
->branch_found
= 1;
1854 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
1857 inst_env
->slot_needed
= 1;
1858 inst_env
->prefix_found
= 0;
1859 inst_env
->xflag_found
= 0;
1860 inst_env
->disable_interrupt
= 1;
1863 /* Handles the ABS instruction. */
1866 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
1871 /* ABS can't have a prefix, so it's bad if it does. */
1872 if (inst_env
->prefix_found
)
1874 inst_env
->invalid
= 1;
1878 /* Check if the operation affects the PC. */
1879 if (cris_get_operand2 (inst
) == REG_PC
)
1882 /* It's invalid to change to the PC if we are in a delay slot. */
1883 if (inst_env
->slot_needed
)
1885 inst_env
->invalid
= 1;
1889 value
= (long) inst_env
->reg
[REG_PC
];
1891 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
1892 if (value
!= SIGNED_DWORD_MASK
)
1895 inst_env
->reg
[REG_PC
] = (long) value
;
1899 inst_env
->slot_needed
= 0;
1900 inst_env
->prefix_found
= 0;
1901 inst_env
->xflag_found
= 0;
1902 inst_env
->disable_interrupt
= 0;
1905 /* Handles the ADDI instruction. */
1908 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
1910 /* It's invalid to have the PC as base register. And ADDI can't have
1912 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
1914 inst_env
->invalid
= 1;
1918 inst_env
->slot_needed
= 0;
1919 inst_env
->prefix_found
= 0;
1920 inst_env
->xflag_found
= 0;
1921 inst_env
->disable_interrupt
= 0;
1924 /* Handles the ASR instruction. */
1927 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
1930 unsigned long value
;
1931 unsigned long signed_extend_mask
= 0;
1933 /* ASR can't have a prefix, so check that it doesn't. */
1934 if (inst_env
->prefix_found
)
1936 inst_env
->invalid
= 1;
1940 /* Check if the PC is the target register. */
1941 if (cris_get_operand2 (inst
) == REG_PC
)
1943 /* It's invalid to change the PC in a delay slot. */
1944 if (inst_env
->slot_needed
)
1946 inst_env
->invalid
= 1;
1949 /* Get the number of bits to shift. */
1950 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
1951 value
= inst_env
->reg
[REG_PC
];
1953 /* Find out how many bits the operation should apply to. */
1954 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
1956 if (value
& SIGNED_BYTE_MASK
)
1958 signed_extend_mask
= 0xFF;
1959 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
1960 signed_extend_mask
= ~signed_extend_mask
;
1962 value
= value
>> shift_steps
;
1963 value
|= signed_extend_mask
;
1965 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
1966 inst_env
->reg
[REG_PC
] |= value
;
1968 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
1970 if (value
& SIGNED_WORD_MASK
)
1972 signed_extend_mask
= 0xFFFF;
1973 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
1974 signed_extend_mask
= ~signed_extend_mask
;
1976 value
= value
>> shift_steps
;
1977 value
|= signed_extend_mask
;
1979 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
1980 inst_env
->reg
[REG_PC
] |= value
;
1982 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
1984 if (value
& SIGNED_DWORD_MASK
)
1986 signed_extend_mask
= 0xFFFFFFFF;
1987 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
1988 signed_extend_mask
= ~signed_extend_mask
;
1990 value
= value
>> shift_steps
;
1991 value
|= signed_extend_mask
;
1992 inst_env
->reg
[REG_PC
] = value
;
1995 inst_env
->slot_needed
= 0;
1996 inst_env
->prefix_found
= 0;
1997 inst_env
->xflag_found
= 0;
1998 inst_env
->disable_interrupt
= 0;
2001 /* Handles the ASRQ instruction. */
2004 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2008 unsigned long value
;
2009 unsigned long signed_extend_mask
= 0;
2011 /* ASRQ can't have a prefix, so check that it doesn't. */
2012 if (inst_env
->prefix_found
)
2014 inst_env
->invalid
= 1;
2018 /* Check if the PC is the target register. */
2019 if (cris_get_operand2 (inst
) == REG_PC
)
2022 /* It's invalid to change the PC in a delay slot. */
2023 if (inst_env
->slot_needed
)
2025 inst_env
->invalid
= 1;
2028 /* The shift size is given as a 5 bit quick value, i.e. we don't
2029 want the the sign bit of the quick value. */
2030 shift_steps
= cris_get_asr_shift_steps (inst
);
2031 value
= inst_env
->reg
[REG_PC
];
2032 if (value
& SIGNED_DWORD_MASK
)
2034 signed_extend_mask
= 0xFFFFFFFF;
2035 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2036 signed_extend_mask
= ~signed_extend_mask
;
2038 value
= value
>> shift_steps
;
2039 value
|= signed_extend_mask
;
2040 inst_env
->reg
[REG_PC
] = value
;
2042 inst_env
->slot_needed
= 0;
2043 inst_env
->prefix_found
= 0;
2044 inst_env
->xflag_found
= 0;
2045 inst_env
->disable_interrupt
= 0;
2048 /* Handles the AX, EI and SETF instruction. */
2051 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2053 if (inst_env
->prefix_found
)
2055 inst_env
->invalid
= 1;
2058 /* Check if the instruction is setting the X flag. */
2059 if (cris_is_xflag_bit_on (inst
))
2061 inst_env
->xflag_found
= 1;
2065 inst_env
->xflag_found
= 0;
2067 inst_env
->slot_needed
= 0;
2068 inst_env
->prefix_found
= 0;
2069 inst_env
->disable_interrupt
= 1;
2072 /* Checks if the instruction is in assign mode. If so, it updates the assign
2073 register. Note that check_assign assumes that the caller has checked that
2074 there is a prefix to this instruction. The mode check depends on this. */
2077 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2079 /* Check if it's an assign addressing mode. */
2080 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2082 /* Assign the prefix value to operand 1. */
2083 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2087 /* Handles the 2-operand BOUND instruction. */
2090 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2092 /* It's invalid to have the PC as the index operand. */
2093 if (cris_get_operand2 (inst
) == REG_PC
)
2095 inst_env
->invalid
= 1;
2098 /* Check if we have a prefix. */
2099 if (inst_env
->prefix_found
)
2101 check_assign (inst
, inst_env
);
2103 /* Check if this is an autoincrement mode. */
2104 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2106 /* It's invalid to change the PC in a delay slot. */
2107 if (inst_env
->slot_needed
)
2109 inst_env
->invalid
= 1;
2112 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2114 inst_env
->slot_needed
= 0;
2115 inst_env
->prefix_found
= 0;
2116 inst_env
->xflag_found
= 0;
2117 inst_env
->disable_interrupt
= 0;
2120 /* Handles the 3-operand BOUND instruction. */
2123 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2125 /* It's an error if we haven't got a prefix. And it's also an error
2126 if the PC is the destination register. */
2127 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2129 inst_env
->invalid
= 1;
2132 inst_env
->slot_needed
= 0;
2133 inst_env
->prefix_found
= 0;
2134 inst_env
->xflag_found
= 0;
2135 inst_env
->disable_interrupt
= 0;
2138 /* Clears the status flags in inst_env. */
2141 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2143 /* It's an error if we have got a prefix. */
2144 if (inst_env
->prefix_found
)
2146 inst_env
->invalid
= 1;
2150 inst_env
->slot_needed
= 0;
2151 inst_env
->prefix_found
= 0;
2152 inst_env
->xflag_found
= 0;
2153 inst_env
->disable_interrupt
= 0;
2156 /* Clears the status flags in inst_env. */
2159 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2161 /* It's an error if we have got a prefix. */
2162 if (inst_env
->prefix_found
)
2164 inst_env
->invalid
= 1;
2168 inst_env
->slot_needed
= 0;
2169 inst_env
->prefix_found
= 0;
2170 inst_env
->xflag_found
= 0;
2171 inst_env
->disable_interrupt
= 1;
2174 /* Handles the CLEAR instruction if it's in register mode. */
2177 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2179 /* Check if the target is the PC. */
2180 if (cris_get_operand2 (inst
) == REG_PC
)
2182 /* The instruction will clear the instruction's size bits. */
2183 int clear_size
= cris_get_clear_size (inst
);
2184 if (clear_size
== INST_BYTE_SIZE
)
2186 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2188 if (clear_size
== INST_WORD_SIZE
)
2190 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2192 if (clear_size
== INST_DWORD_SIZE
)
2194 inst_env
->delay_slot_pc
= 0x0;
2196 /* The jump will be delayed with one delay slot. So we need a delay
2198 inst_env
->slot_needed
= 1;
2199 inst_env
->delay_slot_pc_active
= 1;
2203 /* The PC will not change => no delay slot. */
2204 inst_env
->slot_needed
= 0;
2206 inst_env
->prefix_found
= 0;
2207 inst_env
->xflag_found
= 0;
2208 inst_env
->disable_interrupt
= 0;
2211 /* Handles the TEST instruction if it's in register mode. */
2214 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2216 /* It's an error if we have got a prefix. */
2217 if (inst_env
->prefix_found
)
2219 inst_env
->invalid
= 1;
2222 inst_env
->slot_needed
= 0;
2223 inst_env
->prefix_found
= 0;
2224 inst_env
->xflag_found
= 0;
2225 inst_env
->disable_interrupt
= 0;
2229 /* Handles the CLEAR and TEST instruction if the instruction isn't
2230 in register mode. */
2233 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2235 /* Check if we are in a prefix mode. */
2236 if (inst_env
->prefix_found
)
2238 /* The only way the PC can change is if this instruction is in
2239 assign addressing mode. */
2240 check_assign (inst
, inst_env
);
2242 /* Indirect mode can't change the PC so just check if the mode is
2244 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2246 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2248 inst_env
->slot_needed
= 0;
2249 inst_env
->prefix_found
= 0;
2250 inst_env
->xflag_found
= 0;
2251 inst_env
->disable_interrupt
= 0;
2254 /* Checks that the PC isn't the destination register or the instructions has
2258 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2260 /* It's invalid to have the PC as the destination. The instruction can't
2262 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2264 inst_env
->invalid
= 1;
2268 inst_env
->slot_needed
= 0;
2269 inst_env
->prefix_found
= 0;
2270 inst_env
->xflag_found
= 0;
2271 inst_env
->disable_interrupt
= 0;
2274 /* Checks that the instruction doesn't have a prefix. */
2277 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2279 /* The instruction can't have a prefix. */
2280 if (inst_env
->prefix_found
)
2282 inst_env
->invalid
= 1;
2286 inst_env
->slot_needed
= 0;
2287 inst_env
->prefix_found
= 0;
2288 inst_env
->xflag_found
= 0;
2289 inst_env
->disable_interrupt
= 1;
2292 /* Checks that the PC isn't the destination register and that the instruction
2293 doesn't have a prefix. */
2296 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2298 /* It's invalid to have the PC as the destination. The instruction can't
2300 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2302 inst_env
->invalid
= 1;
2306 inst_env
->slot_needed
= 0;
2307 inst_env
->prefix_found
= 0;
2308 inst_env
->xflag_found
= 0;
2309 inst_env
->disable_interrupt
= 1;
2312 /* Handles the register mode JUMP instruction. */
2315 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2317 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2318 you can't have a prefix. */
2319 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2321 inst_env
->invalid
= 1;
2325 /* Just change the PC. */
2326 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2327 inst_env
->slot_needed
= 0;
2328 inst_env
->prefix_found
= 0;
2329 inst_env
->xflag_found
= 0;
2330 inst_env
->disable_interrupt
= 1;
2333 /* Handles the JUMP instruction for all modes except register. */
2336 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2338 unsigned long newpc
;
2341 /* It's invalid to do a JUMP in a delay slot. */
2342 if (inst_env
->slot_needed
)
2344 inst_env
->invalid
= 1;
2348 /* Check if we have a prefix. */
2349 if (inst_env
->prefix_found
)
2351 check_assign (inst
, inst_env
);
2353 /* Get the new value for the the PC. */
2355 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2360 /* Get the new value for the PC. */
2361 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2362 newpc
= read_memory_unsigned_integer (address
, 4);
2364 /* Check if we should increment a register. */
2365 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2367 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2370 inst_env
->reg
[REG_PC
] = newpc
;
2372 inst_env
->slot_needed
= 0;
2373 inst_env
->prefix_found
= 0;
2374 inst_env
->xflag_found
= 0;
2375 inst_env
->disable_interrupt
= 1;
2378 /* Handles moves to special registers (aka P-register) for all modes. */
2381 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2383 if (inst_env
->prefix_found
)
2385 /* The instruction has a prefix that means we are only interested if
2386 the instruction is in assign mode. */
2387 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2389 /* The prefix handles the problem if we are in a delay slot. */
2390 if (cris_get_operand1 (inst
) == REG_PC
)
2392 /* Just take care of the assign. */
2393 check_assign (inst
, inst_env
);
2397 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2399 /* The instruction doesn't have a prefix, the only case left that we
2400 are interested in is the autoincrement mode. */
2401 if (cris_get_operand1 (inst
) == REG_PC
)
2403 /* If the PC is to be incremented it's invalid to be in a
2405 if (inst_env
->slot_needed
)
2407 inst_env
->invalid
= 1;
2411 /* The increment depends on the size of the special register. */
2412 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2414 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2416 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2418 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2422 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2426 inst_env
->slot_needed
= 0;
2427 inst_env
->prefix_found
= 0;
2428 inst_env
->xflag_found
= 0;
2429 inst_env
->disable_interrupt
= 1;
2432 /* Handles moves from special registers (aka P-register) for all modes
2436 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2438 if (inst_env
->prefix_found
)
2440 /* The instruction has a prefix that means we are only interested if
2441 the instruction is in assign mode. */
2442 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2444 /* The prefix handles the problem if we are in a delay slot. */
2445 if (cris_get_operand1 (inst
) == REG_PC
)
2447 /* Just take care of the assign. */
2448 check_assign (inst
, inst_env
);
2452 /* The instruction doesn't have a prefix, the only case left that we
2453 are interested in is the autoincrement mode. */
2454 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2456 if (cris_get_operand1 (inst
) == REG_PC
)
2458 /* If the PC is to be incremented it's invalid to be in a
2460 if (inst_env
->slot_needed
)
2462 inst_env
->invalid
= 1;
2466 /* The increment depends on the size of the special register. */
2467 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2469 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2471 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2473 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2477 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2481 inst_env
->slot_needed
= 0;
2482 inst_env
->prefix_found
= 0;
2483 inst_env
->xflag_found
= 0;
2484 inst_env
->disable_interrupt
= 1;
2487 /* Handles moves from special registers (aka P-register) when the mode
2491 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2493 /* Register mode move from special register can't have a prefix. */
2494 if (inst_env
->prefix_found
)
2496 inst_env
->invalid
= 1;
2500 if (cris_get_operand1 (inst
) == REG_PC
)
2502 /* It's invalid to change the PC in a delay slot. */
2503 if (inst_env
->slot_needed
)
2505 inst_env
->invalid
= 1;
2508 /* The destination is the PC, the jump will have a delay slot. */
2509 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
2510 inst_env
->slot_needed
= 1;
2511 inst_env
->delay_slot_pc_active
= 1;
2515 /* If the destination isn't PC, there will be no jump. */
2516 inst_env
->slot_needed
= 0;
2518 inst_env
->prefix_found
= 0;
2519 inst_env
->xflag_found
= 0;
2520 inst_env
->disable_interrupt
= 1;
2523 /* Handles the MOVEM from memory to general register instruction. */
2526 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2528 if (inst_env
->prefix_found
)
2530 /* The prefix handles the problem if we are in a delay slot. Is the
2531 MOVEM instruction going to change the PC? */
2532 if (cris_get_operand2 (inst
) >= REG_PC
)
2534 inst_env
->reg
[REG_PC
] =
2535 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
2537 /* The assign value is the value after the increment. Normally, the
2538 assign value is the value before the increment. */
2539 if ((cris_get_operand1 (inst
) == REG_PC
)
2540 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
2542 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
2543 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2548 /* Is the MOVEM instruction going to change the PC? */
2549 if (cris_get_operand2 (inst
) == REG_PC
)
2551 /* It's invalid to change the PC in a delay slot. */
2552 if (inst_env
->slot_needed
)
2554 inst_env
->invalid
= 1;
2557 inst_env
->reg
[REG_PC
] =
2558 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
2561 /* The increment is not depending on the size, instead it's depending
2562 on the number of registers loaded from memory. */
2563 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
2565 /* It's invalid to change the PC in a delay slot. */
2566 if (inst_env
->slot_needed
)
2568 inst_env
->invalid
= 1;
2571 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2574 inst_env
->slot_needed
= 0;
2575 inst_env
->prefix_found
= 0;
2576 inst_env
->xflag_found
= 0;
2577 inst_env
->disable_interrupt
= 0;
2580 /* Handles the MOVEM to memory from general register instruction. */
2583 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2585 if (inst_env
->prefix_found
)
2587 /* The assign value is the value after the increment. Normally, the
2588 assign value is the value before the increment. */
2589 if ((cris_get_operand1 (inst
) == REG_PC
) &&
2590 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
2592 /* The prefix handles the problem if we are in a delay slot. */
2593 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
2594 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2599 /* The increment is not depending on the size, instead it's depending
2600 on the number of registers loaded to memory. */
2601 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
2603 /* It's invalid to change the PC in a delay slot. */
2604 if (inst_env
->slot_needed
)
2606 inst_env
->invalid
= 1;
2609 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2612 inst_env
->slot_needed
= 0;
2613 inst_env
->prefix_found
= 0;
2614 inst_env
->xflag_found
= 0;
2615 inst_env
->disable_interrupt
= 0;
2618 /* Handles the intructions that's not yet implemented, by setting
2619 inst_env->invalid to true. */
2622 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
2624 inst_env
->invalid
= 1;
2627 /* Handles the XOR instruction. */
2630 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
2632 /* XOR can't have a prefix. */
2633 if (inst_env
->prefix_found
)
2635 inst_env
->invalid
= 1;
2639 /* Check if the PC is the target. */
2640 if (cris_get_operand2 (inst
) == REG_PC
)
2642 /* It's invalid to change the PC in a delay slot. */
2643 if (inst_env
->slot_needed
)
2645 inst_env
->invalid
= 1;
2648 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
2650 inst_env
->slot_needed
= 0;
2651 inst_env
->prefix_found
= 0;
2652 inst_env
->xflag_found
= 0;
2653 inst_env
->disable_interrupt
= 0;
2656 /* Handles the MULS instruction. */
2659 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
2661 /* MULS/U can't have a prefix. */
2662 if (inst_env
->prefix_found
)
2664 inst_env
->invalid
= 1;
2668 /* Consider it invalid if the PC is the target. */
2669 if (cris_get_operand2 (inst
) == REG_PC
)
2671 inst_env
->invalid
= 1;
2674 inst_env
->slot_needed
= 0;
2675 inst_env
->prefix_found
= 0;
2676 inst_env
->xflag_found
= 0;
2677 inst_env
->disable_interrupt
= 0;
2680 /* Handles the MULU instruction. */
2683 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
2685 /* MULS/U can't have a prefix. */
2686 if (inst_env
->prefix_found
)
2688 inst_env
->invalid
= 1;
2692 /* Consider it invalid if the PC is the target. */
2693 if (cris_get_operand2 (inst
) == REG_PC
)
2695 inst_env
->invalid
= 1;
2698 inst_env
->slot_needed
= 0;
2699 inst_env
->prefix_found
= 0;
2700 inst_env
->xflag_found
= 0;
2701 inst_env
->disable_interrupt
= 0;
2704 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
2705 The MOVE instruction is the move from source to register. */
2708 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
2709 unsigned long source1
, unsigned long source2
)
2711 unsigned long pc_mask
;
2712 unsigned long operation_mask
;
2714 /* Find out how many bits the operation should apply to. */
2715 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2717 pc_mask
= 0xFFFFFF00;
2718 operation_mask
= 0xFF;
2720 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2722 pc_mask
= 0xFFFF0000;
2723 operation_mask
= 0xFFFF;
2725 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2728 operation_mask
= 0xFFFFFFFF;
2732 /* The size is out of range. */
2733 inst_env
->invalid
= 1;
2737 /* The instruction just works on uw_operation_mask bits. */
2738 source2
&= operation_mask
;
2739 source1
&= operation_mask
;
2741 /* Now calculate the result. The opcode's 3 first bits separates
2742 the different actions. */
2743 switch (cris_get_opcode (inst
) & 7)
2753 case 2: /* subtract */
2757 case 3: /* compare */
2769 inst_env
->invalid
= 1;
2775 /* Make sure that the result doesn't contain more than the instruction
2777 source2
&= operation_mask
;
2779 /* Calculate the new breakpoint address. */
2780 inst_env
->reg
[REG_PC
] &= pc_mask
;
2781 inst_env
->reg
[REG_PC
] |= source1
;
2785 /* Extends the value from either byte or word size to a dword. If the mode
2786 is zero extend then the value is extended with zero. If instead the mode
2787 is signed extend the sign bit of the value is taken into consideration. */
2789 static unsigned long
2790 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
2792 /* The size can be either byte or word, check which one it is.
2793 Don't check the highest bit, it's indicating if it's a zero
2795 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
2800 /* Check if the instruction is signed extend. If so, check if value has
2802 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
2804 value
|= SIGNED_WORD_EXTEND_MASK
;
2812 /* Check if the instruction is signed extend. If so, check if value has
2814 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
2816 value
|= SIGNED_BYTE_EXTEND_MASK
;
2819 /* The size should now be dword. */
2820 cris_set_size_to_dword (inst
);
2824 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
2825 instruction. The MOVE instruction is the move from source to register. */
2828 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
2829 inst_env_type
*inst_env
)
2831 unsigned long operand1
;
2832 unsigned long operand2
;
2834 /* It's invalid to have a prefix to the instruction. This is a register
2835 mode instruction and can't have a prefix. */
2836 if (inst_env
->prefix_found
)
2838 inst_env
->invalid
= 1;
2841 /* Check if the instruction has PC as its target. */
2842 if (cris_get_operand2 (inst
) == REG_PC
)
2844 if (inst_env
->slot_needed
)
2846 inst_env
->invalid
= 1;
2849 /* The instruction has the PC as its target register. */
2850 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
2851 operand2
= inst_env
->reg
[REG_PC
];
2853 /* Check if it's a extend, signed or zero instruction. */
2854 if (cris_get_opcode (inst
) < 4)
2856 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
2858 /* Calculate the PC value after the instruction, i.e. where the
2859 breakpoint should be. The order of the udw_operands is vital. */
2860 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
2862 inst_env
->slot_needed
= 0;
2863 inst_env
->prefix_found
= 0;
2864 inst_env
->xflag_found
= 0;
2865 inst_env
->disable_interrupt
= 0;
2868 /* Returns the data contained at address. The size of the data is derived from
2869 the size of the operation. If the instruction is a zero or signed
2870 extend instruction, the size field is changed in instruction. */
2872 static unsigned long
2873 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
2875 int size
= cris_get_size (*inst
);
2876 unsigned long value
;
2878 /* If it's an extend instruction we don't want the signed extend bit,
2879 because it influences the size. */
2880 if (cris_get_opcode (*inst
) < 4)
2882 size
&= ~SIGNED_EXTEND_BIT_MASK
;
2884 /* Is there a need for checking the size? Size should contain the number of
2887 value
= read_memory_unsigned_integer (address
, size
);
2889 /* Check if it's an extend, signed or zero instruction. */
2890 if (cris_get_opcode (*inst
) < 4)
2892 value
= do_sign_or_zero_extend (value
, inst
);
2897 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
2898 instructions. The MOVE instruction is the move from source to register. */
2901 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
2902 inst_env_type
*inst_env
)
2904 unsigned long operand2
;
2905 unsigned long operand3
;
2907 check_assign (inst
, inst_env
);
2908 if (cris_get_operand2 (inst
) == REG_PC
)
2910 operand2
= inst_env
->reg
[REG_PC
];
2912 /* Get the value of the third operand. */
2913 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
2915 /* Calculate the PC value after the instruction, i.e. where the
2916 breakpoint should be. The order of the udw_operands is vital. */
2917 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
2919 inst_env
->slot_needed
= 0;
2920 inst_env
->prefix_found
= 0;
2921 inst_env
->xflag_found
= 0;
2922 inst_env
->disable_interrupt
= 0;
2925 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
2926 OR instructions. Note that for this to work as expected, the calling
2927 function must have made sure that there is a prefix to this instruction. */
2930 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
2931 inst_env_type
*inst_env
)
2933 unsigned long operand2
;
2934 unsigned long operand3
;
2936 if (cris_get_operand1 (inst
) == REG_PC
)
2938 /* The PC will be changed by the instruction. */
2939 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
2941 /* Get the value of the third operand. */
2942 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
2944 /* Calculate the PC value after the instruction, i.e. where the
2945 breakpoint should be. */
2946 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
2948 inst_env
->slot_needed
= 0;
2949 inst_env
->prefix_found
= 0;
2950 inst_env
->xflag_found
= 0;
2951 inst_env
->disable_interrupt
= 0;
2954 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
2955 instructions. The MOVE instruction is the move from source to register. */
2958 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
2959 inst_env_type
*inst_env
)
2961 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
2963 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
2964 SUB, AND or OR something weird is going on (if everything works these
2965 instructions should end up in the three operand version). */
2966 inst_env
->invalid
= 1;
2971 /* three_operand_add_sub_cmp_and_or does the same as we should do here
2973 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
2975 inst_env
->slot_needed
= 0;
2976 inst_env
->prefix_found
= 0;
2977 inst_env
->xflag_found
= 0;
2978 inst_env
->disable_interrupt
= 0;
2981 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
2982 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
2983 source to register. */
2986 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
2987 inst_env_type
*inst_env
)
2989 unsigned long operand1
;
2990 unsigned long operand2
;
2991 unsigned long operand3
;
2994 /* The instruction is either an indirect or autoincrement addressing mode.
2995 Check if the destination register is the PC. */
2996 if (cris_get_operand2 (inst
) == REG_PC
)
2998 /* Must be done here, get_data_from_address may change the size
3000 size
= cris_get_size (inst
);
3001 operand2
= inst_env
->reg
[REG_PC
];
3003 /* Get the value of the third operand, i.e. the indirect operand. */
3004 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3005 operand3
= get_data_from_address (&inst
, operand1
);
3007 /* Calculate the PC value after the instruction, i.e. where the
3008 breakpoint should be. The order of the udw_operands is vital. */
3009 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3011 /* If this is an autoincrement addressing mode, check if the increment
3013 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3015 /* Get the size field. */
3016 size
= cris_get_size (inst
);
3018 /* If it's an extend instruction we don't want the signed extend bit,
3019 because it influences the size. */
3020 if (cris_get_opcode (inst
) < 4)
3022 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3024 process_autoincrement (size
, inst
, inst_env
);
3026 inst_env
->slot_needed
= 0;
3027 inst_env
->prefix_found
= 0;
3028 inst_env
->xflag_found
= 0;
3029 inst_env
->disable_interrupt
= 0;
3032 /* Handles the two-operand addressing mode, all modes except register, for
3033 the ADD, SUB CMP, AND and OR instruction. */
3036 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3037 inst_env_type
*inst_env
)
3039 if (inst_env
->prefix_found
)
3041 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3043 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3045 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3047 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3051 /* The mode is invalid for a prefixed base instruction. */
3052 inst_env
->invalid
= 1;
3058 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3062 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3065 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3067 unsigned long operand1
;
3068 unsigned long operand2
;
3070 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3071 instruction and can't have a prefix. */
3072 if (inst_env
->prefix_found
)
3074 inst_env
->invalid
= 1;
3078 /* Check if the instruction has PC as its target. */
3079 if (cris_get_operand2 (inst
) == REG_PC
)
3081 if (inst_env
->slot_needed
)
3083 inst_env
->invalid
= 1;
3086 operand1
= cris_get_quick_value (inst
);
3087 operand2
= inst_env
->reg
[REG_PC
];
3089 /* The size should now be dword. */
3090 cris_set_size_to_dword (&inst
);
3092 /* Calculate the PC value after the instruction, i.e. where the
3093 breakpoint should be. */
3094 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3096 inst_env
->slot_needed
= 0;
3097 inst_env
->prefix_found
= 0;
3098 inst_env
->xflag_found
= 0;
3099 inst_env
->disable_interrupt
= 0;
3102 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3105 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3107 unsigned long operand1
;
3108 unsigned long operand2
;
3110 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3111 instruction and can't have a prefix. */
3112 if (inst_env
->prefix_found
)
3114 inst_env
->invalid
= 1;
3117 /* Check if the instruction has PC as its target. */
3118 if (cris_get_operand2 (inst
) == REG_PC
)
3120 if (inst_env
->slot_needed
)
3122 inst_env
->invalid
= 1;
3125 /* The instruction has the PC as its target register. */
3126 operand1
= cris_get_quick_value (inst
);
3127 operand2
= inst_env
->reg
[REG_PC
];
3129 /* The quick value is signed, so check if we must do a signed extend. */
3130 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3133 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3135 /* The size should now be dword. */
3136 cris_set_size_to_dword (&inst
);
3138 /* Calculate the PC value after the instruction, i.e. where the
3139 breakpoint should be. */
3140 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3142 inst_env
->slot_needed
= 0;
3143 inst_env
->prefix_found
= 0;
3144 inst_env
->xflag_found
= 0;
3145 inst_env
->disable_interrupt
= 0;
3148 /* Translate op_type to a function and call it. */
3151 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3152 inst_env_type
*inst_env
)
3156 case cris_not_implemented_op
:
3157 not_implemented_op (inst
, inst_env
);
3161 abs_op (inst
, inst_env
);
3165 addi_op (inst
, inst_env
);
3169 asr_op (inst
, inst_env
);
3173 asrq_op (inst
, inst_env
);
3176 case cris_ax_ei_setf_op
:
3177 ax_ei_setf_op (inst
, inst_env
);
3180 case cris_bdap_prefix
:
3181 bdap_prefix (inst
, inst_env
);
3184 case cris_biap_prefix
:
3185 biap_prefix (inst
, inst_env
);
3189 break_op (inst
, inst_env
);
3192 case cris_btst_nop_op
:
3193 btst_nop_op (inst
, inst_env
);
3196 case cris_clearf_di_op
:
3197 clearf_di_op (inst
, inst_env
);
3200 case cris_dip_prefix
:
3201 dip_prefix (inst
, inst_env
);
3204 case cris_dstep_logshift_mstep_neg_not_op
:
3205 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3208 case cris_eight_bit_offset_branch_op
:
3209 eight_bit_offset_branch_op (inst
, inst_env
);
3212 case cris_move_mem_to_reg_movem_op
:
3213 move_mem_to_reg_movem_op (inst
, inst_env
);
3216 case cris_move_reg_to_mem_movem_op
:
3217 move_reg_to_mem_movem_op (inst
, inst_env
);
3220 case cris_move_to_preg_op
:
3221 move_to_preg_op (inst
, inst_env
);
3225 muls_op (inst
, inst_env
);
3229 mulu_op (inst
, inst_env
);
3232 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3233 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3236 case cris_none_reg_mode_clear_test_op
:
3237 none_reg_mode_clear_test_op (inst
, inst_env
);
3240 case cris_none_reg_mode_jump_op
:
3241 none_reg_mode_jump_op (inst
, inst_env
);
3244 case cris_none_reg_mode_move_from_preg_op
:
3245 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3248 case cris_quick_mode_add_sub_op
:
3249 quick_mode_add_sub_op (inst
, inst_env
);
3252 case cris_quick_mode_and_cmp_move_or_op
:
3253 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3256 case cris_quick_mode_bdap_prefix
:
3257 quick_mode_bdap_prefix (inst
, inst_env
);
3260 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3261 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3264 case cris_reg_mode_clear_op
:
3265 reg_mode_clear_op (inst
, inst_env
);
3268 case cris_reg_mode_jump_op
:
3269 reg_mode_jump_op (inst
, inst_env
);
3272 case cris_reg_mode_move_from_preg_op
:
3273 reg_mode_move_from_preg_op (inst
, inst_env
);
3276 case cris_reg_mode_test_op
:
3277 reg_mode_test_op (inst
, inst_env
);
3281 scc_op (inst
, inst_env
);
3284 case cris_sixteen_bit_offset_branch_op
:
3285 sixteen_bit_offset_branch_op (inst
, inst_env
);
3288 case cris_three_operand_add_sub_cmp_and_or_op
:
3289 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3292 case cris_three_operand_bound_op
:
3293 three_operand_bound_op (inst
, inst_env
);
3296 case cris_two_operand_bound_op
:
3297 two_operand_bound_op (inst
, inst_env
);
3301 xor_op (inst
, inst_env
);
3306 /* This wrapper is to avoid cris_get_assembler being called before
3307 exec_bfd has been set. */
3310 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3312 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3313 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3314 disassembler, even when there is no BFD. Does something like
3315 "gdb; target remote; disassmeble *0x123" work? */
3316 gdb_assert (exec_bfd
!= NULL
);
3317 print_insn
= cris_get_disassembler (exec_bfd
);
3318 gdb_assert (print_insn
!= NULL
);
3319 return print_insn (addr
, info
);
3322 /* Copied from <asm/elf.h>. */
3323 typedef unsigned long elf_greg_t
;
3325 /* Same as user_regs_struct struct in <asm/user.h>. */
3326 typedef elf_greg_t elf_gregset_t
[35];
3328 /* Unpack an elf_gregset_t into GDB's register cache. */
3331 supply_gregset (elf_gregset_t
*gregsetp
)
3334 elf_greg_t
*regp
= *gregsetp
;
3335 static char zerobuf
[4] = {0};
3337 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3338 knows about the actual size of each register so that's no problem. */
3339 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3341 supply_register (i
, (char *)®p
[i
]);
3345 /* Use a local version of this function to get the correct types for
3346 regsets, until multi-arch core support is ready. */
3349 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
3350 int which
, CORE_ADDR reg_addr
)
3352 elf_gregset_t gregset
;
3357 if (core_reg_size
!= sizeof (gregset
))
3359 warning ("wrong size gregset struct in core file");
3363 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3364 supply_gregset (&gregset
);
3368 /* We've covered all the kinds of registers we know about here,
3369 so this must be something we wouldn't know what to do with
3370 anyway. Just ignore it. */
3375 static struct core_fns cris_elf_core_fns
=
3377 bfd_target_elf_flavour
, /* core_flavour */
3378 default_check_format
, /* check_format */
3379 default_core_sniffer
, /* core_sniffer */
3380 fetch_core_registers
, /* core_read_registers */
3384 /* Fetch (and possibly build) an appropriate link_map_offsets
3385 structure for native GNU/Linux CRIS targets using the struct
3386 offsets defined in link.h (but without actual reference to that
3389 This makes it possible to access GNU/Linux CRIS shared libraries
3390 from a GDB that was not built on an GNU/Linux CRIS host (for cross
3393 See gdb/solib-svr4.h for an explanation of these fields. */
3395 static struct link_map_offsets
*
3396 cris_linux_svr4_fetch_link_map_offsets (void)
3398 static struct link_map_offsets lmo
;
3399 static struct link_map_offsets
*lmp
= NULL
;
3405 lmo
.r_debug_size
= 8; /* The actual size is 20 bytes, but
3406 this is all we need. */
3407 lmo
.r_map_offset
= 4;
3410 lmo
.link_map_size
= 20;
3412 lmo
.l_addr_offset
= 0;
3413 lmo
.l_addr_size
= 4;
3415 lmo
.l_name_offset
= 4;
3416 lmo
.l_name_size
= 4;
3418 lmo
.l_next_offset
= 12;
3419 lmo
.l_next_size
= 4;
3421 lmo
.l_prev_offset
= 16;
3422 lmo
.l_prev_size
= 4;
3429 cris_fpless_backtrace (char *noargs
, int from_tty
)
3431 /* Points at the instruction after the jsr (except when in innermost frame
3432 where it points at the original pc). */
3435 /* Temporary variable, used for parsing from the start of the function that
3436 the pc is in, up to the pc. */
3437 CORE_ADDR tmp_pc
= 0;
3440 /* Information about current frame. */
3441 struct symtab_and_line sal
;
3444 /* Present instruction. */
3445 unsigned short insn
;
3447 /* Next instruction, lookahead. */
3448 unsigned short insn_next
;
3450 /* This is to store the offset between sp at start of function and until we
3451 reach push srp (if any). */
3452 int sp_add_later
= 0;
3453 int push_srp_found
= 0;
3457 /* Frame counter. */
3460 /* For the innermost frame, we want to look at srp in case it's a leaf
3461 function (since there's no push srp in that case). */
3462 int innermost_frame
= 1;
3464 deprecated_read_register_gen (PC_REGNUM
, (char *) &pc
);
3465 deprecated_read_register_gen (SP_REGNUM
, (char *) &sp
);
3467 /* We make an explicit return when we can't find an outer frame. */
3470 /* Get file name and line number. */
3471 sal
= find_pc_line (pc
, 0);
3473 /* Get function name. */
3474 find_pc_partial_function (pc
, &func_name
, (CORE_ADDR
*) NULL
,
3475 (CORE_ADDR
*) NULL
);
3477 /* Print information about current frame. */
3478 printf_unfiltered ("#%i 0x%08lx in %s", frame
++, pc
, func_name
);
3481 printf_unfiltered (" at %s:%i", sal
.symtab
->filename
, sal
.line
);
3483 printf_unfiltered ("\n");
3485 /* Get the start address of this function. */
3486 tmp_pc
= get_pc_function_start (pc
);
3488 /* Mini parser, only meant to find push sp and sub ...,sp from the start
3489 of the function, up to the pc. */
3492 insn
= read_memory_unsigned_integer (tmp_pc
, sizeof (short));
3493 tmp_pc
+= sizeof (short);
3496 /* push <reg> 32 bit instruction */
3497 insn_next
= read_memory_unsigned_integer (tmp_pc
,
3499 tmp_pc
+= sizeof (short);
3501 /* Recognize srp. */
3502 if (insn_next
== 0xBE7E)
3504 /* For subsequent (not this one though) push or sub which
3505 affects sp, adjust sp immediately. */
3508 /* Note: this will break if we ever encounter a
3509 push vr (1 byte) or push ccr (2 bytes). */
3514 /* Some other register was pushed. */
3525 else if (cris_get_operand2 (insn
) == SP_REGNUM
3526 && cris_get_mode (insn
) == 0x0000
3527 && cris_get_opcode (insn
) == 0x000A)
3530 val
= cris_get_quick_value (insn
);
3538 sp_add_later
+= val
;
3542 else if (cris_get_operand2 (insn
) == SP_REGNUM
3543 /* Autoincrement addressing mode. */
3544 && cris_get_mode (insn
) == 0x0003
3546 && ((insn
) & 0x03E0) >> 5 == 0x0004)
3549 val
= get_data_from_address (&insn
, tmp_pc
);
3557 sp_add_later
+= val
;
3560 else if (cris_get_operand2 (insn
) == SP_REGNUM
3561 && ((insn
& 0x0F00) >> 8) == 0x0001
3562 && (cris_get_signed_offset (insn
) < 0))
3564 /* Immediate byte offset addressing prefix word with sp as base
3565 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
3566 is between 64 and 128.
3567 movem r<regsave>,[sp=sp-<val>] */
3568 val
= -cris_get_signed_offset (insn
);
3569 insn_next
= read_memory_unsigned_integer (tmp_pc
,
3571 tmp_pc
+= sizeof (short);
3573 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
3574 && cris_get_opcode (insn_next
) == 0x000F
3575 && cris_get_size (insn_next
) == 0x0003
3576 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
3584 sp_add_later
+= val
;
3595 /* sp should now point at where srp is stored on the stack. Update
3596 the pc to the srp. */
3597 pc
= read_memory_unsigned_integer (sp
, 4);
3599 else if (innermost_frame
)
3601 /* We couldn't find a push srp in the prologue, so this must be
3602 a leaf function, and thus we use the srp register directly.
3603 This should happen at most once, for the innermost function. */
3604 deprecated_read_register_gen (SRP_REGNUM
, (char *) &pc
);
3608 /* Couldn't find an outer frame. */
3612 /* Reset flag. (In case the innermost frame wasn't a leaf, we don't
3613 want to look at the srp register later either). */
3614 innermost_frame
= 0;
3616 /* Now, add the offset for everything up to, and including push srp,
3617 that was held back during the prologue parsing. */
3623 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3626 _initialize_cris_tdep (void)
3628 struct cmd_list_element
*c
;
3630 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3632 /* CRIS-specific user-commands. */
3633 c
= add_set_cmd ("cris-version", class_support
, var_integer
,
3634 (char *) &usr_cmd_cris_version
,
3635 "Set the current CRIS version.", &setlist
);
3636 set_cmd_sfunc (c
, cris_version_update
);
3637 add_show_from_set (c
, &showlist
);
3639 c
= add_set_enum_cmd ("cris-mode", class_support
, cris_mode_enums
,
3641 "Set the current CRIS mode.", &setlist
);
3642 set_cmd_sfunc (c
, cris_mode_update
);
3643 add_show_from_set (c
, &showlist
);
3645 c
= add_cmd ("cris-fpless-backtrace", class_support
, cris_fpless_backtrace
,
3646 "Display call chain using the subroutine return pointer.\n"
3647 "Note that this displays the address after the jump to the "
3648 "subroutine.", &cmdlist
);
3650 add_core_fns (&cris_elf_core_fns
);
3654 /* Prints out all target specific values. */
3657 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3659 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3662 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3663 tdep
->cris_version
);
3664 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3670 cris_version_update (char *ignore_args
, int from_tty
,
3671 struct cmd_list_element
*c
)
3673 struct gdbarch_info info
;
3675 /* NOTE: cagney/2002-03-17: The add_show_from_set() function clones
3676 the set command passed as a parameter. The clone operation will
3677 include (BUG?) any ``set'' command callback, if present.
3678 Commands like ``info set'' call all the ``show'' command
3679 callbacks. Unfortunately, for ``show'' commands cloned from
3680 ``set'', this includes callbacks belonging to ``set'' commands.
3681 Making this worse, this only occures if add_show_from_set() is
3682 called after add_cmd_sfunc() (BUG?). */
3684 /* From here on, trust the user's CRIS version setting. */
3685 if (cmd_type (c
) == set_cmd
)
3687 usr_cmd_cris_version_valid
= 1;
3689 /* Update the current architecture, if needed. */
3690 gdbarch_info_init (&info
);
3691 if (!gdbarch_update_p (info
))
3692 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_update: failed to update architecture.");
3697 cris_mode_update (char *ignore_args
, int from_tty
,
3698 struct cmd_list_element
*c
)
3700 struct gdbarch_info info
;
3702 /* NOTE: cagney/2002-03-17: The add_show_from_set() function clones
3703 the set command passed as a parameter. The clone operation will
3704 include (BUG?) any ``set'' command callback, if present.
3705 Commands like ``info set'' call all the ``show'' command
3706 callbacks. Unfortunately, for ``show'' commands cloned from
3707 ``set'', this includes callbacks belonging to ``set'' commands.
3708 Making this worse, this only occures if add_show_from_set() is
3709 called after add_cmd_sfunc() (BUG?). */
3711 /* From here on, trust the user's CRIS mode setting. */
3712 if (cmd_type (c
) == set_cmd
)
3714 usr_cmd_cris_mode_valid
= 1;
3716 /* Update the current architecture, if needed. */
3717 gdbarch_info_init (&info
);
3718 if (!gdbarch_update_p (info
))
3719 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_update: failed to update architecture.");
3723 /* Copied from pa64solib.c, with a couple of minor changes. */
3726 bfd_lookup_symbol (bfd
*abfd
, const char *symname
)
3728 unsigned int storage_needed
;
3730 asymbol
**symbol_table
;
3731 unsigned int number_of_symbols
;
3733 struct cleanup
*back_to
;
3734 CORE_ADDR symaddr
= 0;
3736 storage_needed
= bfd_get_symtab_upper_bound (abfd
);
3738 if (storage_needed
> 0)
3740 symbol_table
= (asymbol
**) xmalloc (storage_needed
);
3741 back_to
= make_cleanup (free
, symbol_table
);
3742 number_of_symbols
= bfd_canonicalize_symtab (abfd
, symbol_table
);
3744 for (i
= 0; i
< number_of_symbols
; i
++)
3746 sym
= *symbol_table
++;
3747 if (!strcmp (sym
->name
, symname
))
3749 /* Bfd symbols are section relative. */
3750 symaddr
= sym
->value
+ sym
->section
->vma
;
3754 do_cleanups (back_to
);
3759 static struct gdbarch
*
3760 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3762 struct gdbarch
*gdbarch
;
3763 struct gdbarch_tdep
*tdep
;
3765 const char *cris_mode
;
3768 if (usr_cmd_cris_version_valid
)
3770 /* Trust the user's CRIS version setting. */
3771 cris_version
= usr_cmd_cris_version
;
3775 /* Assume it's CRIS version 10. */
3779 if (usr_cmd_cris_mode_valid
)
3781 /* Trust the user's CRIS mode setting. */
3782 cris_mode
= usr_cmd_cris_mode
;
3784 else if (cris_version
== 10)
3786 /* Assume CRIS version 10 is in user mode. */
3787 cris_mode
= CRIS_MODE_USER
;
3791 /* Strictly speaking, older CRIS version don't have a supervisor mode,
3792 but we regard its only mode as supervisor mode. */
3793 cris_mode
= CRIS_MODE_SUPERVISOR
;
3796 /* Make the current settings visible to the user. */
3797 usr_cmd_cris_version
= cris_version
;
3798 usr_cmd_cris_mode
= cris_mode
;
3800 /* Find a candidate among the list of pre-declared architectures. Both
3801 CRIS version and ABI must match. */
3802 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3804 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3806 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
== cris_version
)
3807 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
== cris_mode
))
3808 return arches
->gdbarch
;
3811 /* No matching architecture was found. Create a new one. */
3812 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3813 gdbarch
= gdbarch_alloc (&info
, tdep
);
3815 tdep
->cris_version
= cris_version
;
3816 tdep
->cris_mode
= cris_mode
;
3818 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
3819 switch (info
.byte_order
)
3821 case BFD_ENDIAN_LITTLE
:
3825 case BFD_ENDIAN_BIG
:
3826 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: big endian byte order in info");
3830 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unknown byte order in info");
3833 set_gdbarch_return_value (gdbarch
, cris_return_value
);
3834 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
3835 cris_reg_struct_has_addr
);
3836 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
3838 /* There are 32 registers (some of which may not be implemented). */
3839 set_gdbarch_num_regs (gdbarch
, 32);
3840 set_gdbarch_sp_regnum (gdbarch
, 14);
3841 set_gdbarch_pc_regnum (gdbarch
, 15);
3842 set_gdbarch_register_name (gdbarch
, cris_register_name
);
3844 /* Length of ordinary registers used in push_word and a few other
3845 places. DEPRECATED_REGISTER_RAW_SIZE is the real way to know how
3846 big a register is. */
3847 set_gdbarch_deprecated_register_size (gdbarch
, 4);
3848 set_gdbarch_double_bit (gdbarch
, 64);
3849 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
3850 which means we have to set this explicitly. */
3851 set_gdbarch_long_double_bit (gdbarch
, 64);
3852 set_gdbarch_register_bytes_ok (gdbarch
, cris_register_bytes_ok
);
3853 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
3854 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
3856 /* The total amount of space needed to store (in an array called registers)
3857 GDB's copy of the machine's register state. Note: We can not use
3858 cris_register_size at this point, since it relies on current_gdbarch
3860 switch (tdep
->cris_version
)
3866 /* Support for these may be added later. */
3867 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unsupported CRIS version");
3872 /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15
3873 (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits),
3874 and P8 - P14 (32 bits). */
3875 register_bytes
= (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4);
3880 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
3881 P7 (32 bits), and P15 (32 bits) have been implemented. */
3882 register_bytes
= (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4);
3886 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unknown CRIS version");
3889 set_gdbarch_deprecated_register_bytes (gdbarch
, register_bytes
);
3891 /* Returns the register offset for the first byte of register regno's space
3892 in the saved register state. */
3893 set_gdbarch_deprecated_register_byte (gdbarch
, cris_register_offset
);
3895 /* The length of the registers in the actual machine representation. */
3896 set_gdbarch_deprecated_register_raw_size (gdbarch
, cris_register_size
);
3898 /* The largest value DEPRECATED_REGISTER_RAW_SIZE can have. */
3899 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, 32);
3901 /* The length of the registers in the program's representation. */
3902 set_gdbarch_deprecated_register_virtual_size (gdbarch
, cris_register_size
);
3904 /* The largest value DEPRECATED_REGISTER_VIRTUAL_SIZE can have. */
3905 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, 32);
3907 set_gdbarch_deprecated_register_virtual_type (gdbarch
, cris_register_virtual_type
);
3909 /* Dummy frame functions. */
3910 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
3911 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
3912 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
3914 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
3915 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
3917 /* The stack grows downward. */
3918 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3920 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
3922 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
3923 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
3924 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
3926 /* FIXME: Hook in the DWARF CFI frame unwinder.
3927 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3929 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
3930 frame_base_set_default (gdbarch
, &cris_frame_base
);
3932 /* Use target_specific function to define link map offsets. */
3933 set_solib_svr4_fetch_link_map_offsets
3934 (gdbarch
, cris_linux_svr4_fetch_link_map_offsets
);
3936 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3937 disassembler, even when there is no BFD. Does something like
3938 "gdb; target remote; disassmeble *0x123" work? */
3939 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);