1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
31 #include "dwarf2-frame.h"
39 #include "opcode/cris.h"
40 #include "arch-utils.h"
42 #include "gdb_assert.h"
44 /* To get entry_point_address. */
47 #include "solib.h" /* Support for shared libraries. */
48 #include "solib-svr4.h"
49 #include "gdb_string.h"
54 /* There are no floating point registers. Used in gdbserver low-linux.c. */
57 /* There are 16 general registers. */
60 /* There are 16 special registers. */
63 /* CRISv32 has a pseudo PC register, not noted here. */
65 /* CRISv32 has 16 support registers. */
69 /* Register numbers of various important registers.
70 CRIS_FP_REGNUM Contains address of executing stack frame.
71 STR_REGNUM Contains the address of structure return values.
72 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
73 ARG1_REGNUM Contains the first parameter to a function.
74 ARG2_REGNUM Contains the second parameter to a function.
75 ARG3_REGNUM Contains the third parameter to a function.
76 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
77 SP_REGNUM Contains address of top of stack.
78 PC_REGNUM Contains address of next instruction.
79 SRP_REGNUM Subroutine return pointer register.
80 BRP_REGNUM Breakpoint return pointer register. */
84 /* Enums with respect to the general registers, valid for all
85 CRIS versions. The frame pointer is always in R8. */
87 /* ABI related registers. */
95 /* Registers which happen to be common. */
100 /* CRISv10 et. al. specific registers. */
112 /* CRISv32 specific registers. */
125 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
127 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
147 extern const struct cris_spec_reg cris_spec_regs
[];
149 /* CRIS version, set via the user command 'set cris-version'. Affects
150 register names and sizes. */
151 static int usr_cmd_cris_version
;
153 /* Indicates whether to trust the above variable. */
154 static int usr_cmd_cris_version_valid
= 0;
156 static const char cris_mode_normal
[] = "normal";
157 static const char cris_mode_guru
[] = "guru";
158 static const char *cris_modes
[] = {
164 /* CRIS mode, set via the user command 'set cris-mode'. Affects
165 type of break instruction among other things. */
166 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
168 /* Whether to make use of Dwarf-2 CFI (default on). */
169 static int usr_cmd_cris_dwarf2_cfi
= 1;
171 /* CRIS architecture specific information. */
175 const char *cris_mode
;
179 /* Functions for accessing target dependent data. */
184 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
190 return (gdbarch_tdep (current_gdbarch
)->cris_mode
);
193 /* Sigtramp identification code copied from i386-linux-tdep.c. */
195 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
196 #define SIGTRAMP_OFFSET0 0
197 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
198 #define SIGTRAMP_OFFSET1 4
200 static const unsigned short sigtramp_code
[] =
202 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
203 SIGTRAMP_INSN1
/* break 13 */
206 #define SIGTRAMP_LEN (sizeof sigtramp_code)
208 /* Note: same length as normal sigtramp code. */
210 static const unsigned short rt_sigtramp_code
[] =
212 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
213 SIGTRAMP_INSN1
/* break 13 */
216 /* If PC is in a sigtramp routine, return the address of the start of
217 the routine. Otherwise, return 0. */
220 cris_sigtramp_start (struct frame_info
*next_frame
)
222 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
223 gdb_byte buf
[SIGTRAMP_LEN
];
225 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
228 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
230 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
233 pc
-= SIGTRAMP_OFFSET1
;
234 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
238 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
244 /* If PC is in a RT sigtramp routine, return the address of the start of
245 the routine. Otherwise, return 0. */
248 cris_rt_sigtramp_start (struct frame_info
*next_frame
)
250 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
251 gdb_byte buf
[SIGTRAMP_LEN
];
253 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
256 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
258 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
261 pc
-= SIGTRAMP_OFFSET1
;
262 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
266 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
272 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
273 routine, return the address of the associated sigcontext structure. */
276 cris_sigcontext_addr (struct frame_info
*next_frame
)
282 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
283 sp
= extract_unsigned_integer (buf
, 4);
285 /* Look for normal sigtramp frame first. */
286 pc
= cris_sigtramp_start (next_frame
);
289 /* struct signal_frame (arch/cris/kernel/signal.c) contains
290 struct sigcontext as its first member, meaning the SP points to
295 pc
= cris_rt_sigtramp_start (next_frame
);
298 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
299 a struct ucontext, which in turn contains a struct sigcontext.
301 4 + 4 + 128 to struct ucontext, then
302 4 + 4 + 12 to struct sigcontext. */
306 error (_("Couldn't recognize signal trampoline."));
310 struct cris_unwind_cache
312 /* The previous frame's inner most stack address. Used as this
313 frame ID's stack_addr. */
315 /* The frame's base, optionally used by the high-level debug info. */
318 /* How far the SP and r8 (FP) have been offset from the start of
319 the stack frame (as defined by the previous frame's stack
325 /* From old frame_extra_info struct. */
329 /* Table indicating the location of each and every register. */
330 struct trad_frame_saved_reg
*saved_regs
;
333 static struct cris_unwind_cache
*
334 cris_sigtramp_frame_unwind_cache (struct frame_info
*next_frame
,
337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
338 struct cris_unwind_cache
*info
;
346 return (*this_cache
);
348 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
349 (*this_cache
) = info
;
350 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
352 /* Zero all fields. */
358 info
->uses_frame
= 0;
360 info
->leaf_function
= 0;
362 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
363 info
->base
= extract_unsigned_integer (buf
, 4);
365 addr
= cris_sigcontext_addr (next_frame
);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep
->cris_version
== 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i
= 0; i
<= 13; i
++)
379 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
381 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
382 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
383 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
388 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[IRP_REGNUM
];
389 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (24 * 4);
394 /* R0 to R13 are stored in order at offset (1 * 4) in
396 for (i
= 0; i
<= 13; i
++)
397 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
399 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
400 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
401 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
402 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
403 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
404 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
405 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
406 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
407 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
409 /* FIXME: If ERP is in a delay slot at this point then the PC will
410 be wrong at this point. This problem manifests itself in the
411 sigaltstack.exp test case, which occasionally generates FAILs when
412 the signal is received while in a delay slot.
414 This could be solved by a couple of read_memory_unsigned_integer and a
415 trad_frame_set_value. */
416 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[ERP_REGNUM
];
418 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (25 * 4);
425 cris_sigtramp_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
426 struct frame_id
*this_id
)
428 struct cris_unwind_cache
*cache
=
429 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
430 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
433 /* Forward declaration. */
435 static void cris_frame_prev_register (struct frame_info
*next_frame
,
436 void **this_prologue_cache
,
437 int regnum
, int *optimizedp
,
438 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
439 int *realnump
, gdb_byte
*bufferp
);
441 cris_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
443 int regnum
, int *optimizedp
,
444 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
445 int *realnump
, gdb_byte
*valuep
)
447 /* Make sure we've initialized the cache. */
448 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
449 cris_frame_prev_register (next_frame
, this_cache
, regnum
,
450 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
453 static const struct frame_unwind cris_sigtramp_frame_unwind
=
456 cris_sigtramp_frame_this_id
,
457 cris_sigtramp_frame_prev_register
460 static const struct frame_unwind
*
461 cris_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
463 if (cris_sigtramp_start (next_frame
)
464 || cris_rt_sigtramp_start (next_frame
))
465 return &cris_sigtramp_frame_unwind
;
471 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
472 struct frame_info
*this_frame
)
474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
479 if (cris_mode () == cris_mode_guru
)
481 frame_unwind_register (this_frame
, NRP_REGNUM
, buf
);
485 frame_unwind_register (this_frame
, ERP_REGNUM
, buf
);
488 erp
= extract_unsigned_integer (buf
, 4);
492 /* In delay slot - check if there's a breakpoint at the preceding
494 if (breakpoint_here_p (erp
& ~0x1))
500 /* Hardware watchpoint support. */
502 /* We support 6 hardware data watchpoints, but cannot trigger on execute
503 (any combination of read/write is fine). */
506 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
510 /* No bookkeeping is done here; it is handled by the remote debug agent. */
512 if (tdep
->cris_version
!= 32)
515 /* CRISv32: Six data watchpoints, one for instructions. */
516 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
517 || type
== bp_hardware_watchpoint
) && count
<= 6)
518 || (type
== bp_hardware_breakpoint
&& count
<= 1));
521 /* The CRISv32 hardware data watchpoints work by specifying ranges,
522 which have no alignment or length restrictions. */
525 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
530 /* If the inferior has some watchpoint that triggered, return the
531 address associated with that watchpoint. Otherwise, return
535 cris_stopped_data_address (void)
538 eda
= read_register (EDA_REGNUM
);
542 /* The instruction environment needed to find single-step breakpoints. */
545 struct instruction_environment
547 unsigned long reg
[NUM_GENREGS
];
548 unsigned long preg
[NUM_SPECREGS
];
549 unsigned long branch_break_address
;
550 unsigned long delay_slot_pc
;
551 unsigned long prefix_value
;
556 int delay_slot_pc_active
;
558 int disable_interrupt
;
561 /* Machine-dependencies in CRIS for opcodes. */
563 /* Instruction sizes. */
564 enum cris_instruction_sizes
571 /* Addressing modes. */
572 enum cris_addressing_modes
579 /* Prefix addressing modes. */
580 enum cris_prefix_addressing_modes
582 PREFIX_INDEX_MODE
= 2,
583 PREFIX_ASSIGN_MODE
= 3,
585 /* Handle immediate byte offset addressing mode prefix format. */
586 PREFIX_OFFSET_MODE
= 2
589 /* Masks for opcodes. */
590 enum cris_opcode_masks
592 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
593 SIGNED_EXTEND_BIT_MASK
= 0x2,
594 SIGNED_BYTE_MASK
= 0x80,
595 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
596 SIGNED_WORD_MASK
= 0x8000,
597 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
598 SIGNED_DWORD_MASK
= 0x80000000,
599 SIGNED_QUICK_VALUE_MASK
= 0x20,
600 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
603 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
611 cris_get_operand2 (unsigned short insn
)
613 return ((insn
& 0xF000) >> 12);
617 cris_get_mode (unsigned short insn
)
619 return ((insn
& 0x0C00) >> 10);
623 cris_get_opcode (unsigned short insn
)
625 return ((insn
& 0x03C0) >> 6);
629 cris_get_size (unsigned short insn
)
631 return ((insn
& 0x0030) >> 4);
635 cris_get_operand1 (unsigned short insn
)
637 return (insn
& 0x000F);
640 /* Additional functions in order to handle opcodes. */
643 cris_get_quick_value (unsigned short insn
)
645 return (insn
& 0x003F);
649 cris_get_bdap_quick_offset (unsigned short insn
)
651 return (insn
& 0x00FF);
655 cris_get_branch_short_offset (unsigned short insn
)
657 return (insn
& 0x00FF);
661 cris_get_asr_shift_steps (unsigned long value
)
663 return (value
& 0x3F);
667 cris_get_clear_size (unsigned short insn
)
669 return ((insn
) & 0xC000);
673 cris_is_signed_extend_bit_on (unsigned short insn
)
675 return (((insn
) & 0x20) == 0x20);
679 cris_is_xflag_bit_on (unsigned short insn
)
681 return (((insn
) & 0x1000) == 0x1000);
685 cris_set_size_to_dword (unsigned short *insn
)
692 cris_get_signed_offset (unsigned short insn
)
694 return ((signed char) (insn
& 0x00FF));
697 /* Calls an op function given the op-type, working on the insn and the
699 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
701 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
702 struct gdbarch_list
*);
704 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
706 static void set_cris_version (char *ignore_args
, int from_tty
,
707 struct cmd_list_element
*c
);
709 static void set_cris_mode (char *ignore_args
, int from_tty
,
710 struct cmd_list_element
*c
);
712 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
713 struct cmd_list_element
*c
);
715 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
716 struct frame_info
*next_frame
,
717 struct cris_unwind_cache
*info
);
719 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
720 struct frame_info
*next_frame
,
721 struct cris_unwind_cache
*info
);
723 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
724 struct frame_info
*next_frame
);
726 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
727 struct frame_info
*next_frame
);
729 /* When arguments must be pushed onto the stack, they go on in reverse
730 order. The below implements a FILO (stack) to do this.
731 Copied from d10v-tdep.c. */
736 struct stack_item
*prev
;
740 static struct stack_item
*
741 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
743 struct stack_item
*si
;
744 si
= xmalloc (sizeof (struct stack_item
));
745 si
->data
= xmalloc (len
);
748 memcpy (si
->data
, contents
, len
);
752 static struct stack_item
*
753 pop_stack_item (struct stack_item
*si
)
755 struct stack_item
*dead
= si
;
762 /* Put here the code to store, into fi->saved_regs, the addresses of
763 the saved registers of frame described by FRAME_INFO. This
764 includes special registers such as pc and fp saved in special ways
765 in the stack frame. sp is even more special: the address we return
766 for it IS the sp for the next frame. */
768 struct cris_unwind_cache
*
769 cris_frame_unwind_cache (struct frame_info
*next_frame
,
770 void **this_prologue_cache
)
773 struct cris_unwind_cache
*info
;
776 if ((*this_prologue_cache
))
777 return (*this_prologue_cache
);
779 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
780 (*this_prologue_cache
) = info
;
781 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
783 /* Zero all fields. */
789 info
->uses_frame
= 0;
791 info
->leaf_function
= 0;
793 /* Prologue analysis does the rest... */
794 if (cris_version () == 32)
795 crisv32_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
798 cris_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
804 /* Given a GDB frame, determine the address of the calling function's
805 frame. This will be used to create a new GDB frame struct. */
808 cris_frame_this_id (struct frame_info
*next_frame
,
809 void **this_prologue_cache
,
810 struct frame_id
*this_id
)
812 struct cris_unwind_cache
*info
813 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
818 /* The FUNC is easy. */
819 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
821 /* Hopefully the prologue analysis either correctly determined the
822 frame's base (which is the SP from the previous frame), or set
823 that base to "NULL". */
824 base
= info
->prev_sp
;
828 id
= frame_id_build (base
, func
);
834 cris_frame_prev_register (struct frame_info
*next_frame
,
835 void **this_prologue_cache
,
836 int regnum
, int *optimizedp
,
837 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
838 int *realnump
, gdb_byte
*bufferp
)
840 struct cris_unwind_cache
*info
841 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
842 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
843 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
846 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
847 dummy frame. The frame ID's base needs to match the TOS value
848 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
851 static struct frame_id
852 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
854 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
855 frame_pc_unwind (next_frame
));
859 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
861 /* Align to the size of an instruction (so that they can safely be
862 pushed onto the stack). */
867 cris_push_dummy_code (struct gdbarch
*gdbarch
,
868 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
869 struct value
**args
, int nargs
,
870 struct type
*value_type
,
871 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
873 /* Allocate space sufficient for a breakpoint. */
875 /* Store the address of that breakpoint */
877 /* CRIS always starts the call at the callee's entry point. */
883 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
884 struct regcache
*regcache
, CORE_ADDR bp_addr
,
885 int nargs
, struct value
**args
, CORE_ADDR sp
,
886 int struct_return
, CORE_ADDR struct_addr
)
895 /* The function's arguments and memory allocated by gdb for the arguments to
896 point at reside in separate areas on the stack.
897 Both frame pointers grow toward higher addresses. */
901 struct stack_item
*si
= NULL
;
903 /* Push the return address. */
904 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
906 /* Are we returning a value using a structure return or a normal value
907 return? struct_addr is the address of the reserved space for the return
908 structure to be written on the stack. */
911 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
914 /* Now load as many as possible of the first arguments into registers,
915 and push the rest onto the stack. */
916 argreg
= ARG1_REGNUM
;
919 for (argnum
= 0; argnum
< nargs
; argnum
++)
926 len
= TYPE_LENGTH (value_type (args
[argnum
]));
927 val
= (char *) value_contents (args
[argnum
]);
929 /* How may registers worth of storage do we need for this argument? */
930 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
932 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
934 /* Data passed by value. Fits in available register(s). */
935 for (i
= 0; i
< reg_demand
; i
++)
937 regcache_cooked_write_unsigned (regcache
, argreg
,
938 *(unsigned long *) val
);
943 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
945 /* Data passed by value. Does not fit in available register(s).
946 Use the register(s) first, then the stack. */
947 for (i
= 0; i
< reg_demand
; i
++)
949 if (argreg
<= ARG4_REGNUM
)
951 regcache_cooked_write_unsigned (regcache
, argreg
,
952 *(unsigned long *) val
);
958 /* Push item for later so that pushed arguments
959 come in the right order. */
960 si
= push_stack_item (si
, val
, 4);
965 else if (len
> (2 * 4))
968 internal_error (__FILE__
, __LINE__
, _("We don't do this"));
972 /* Data passed by value. No available registers. Put it on
974 si
= push_stack_item (si
, val
, len
);
980 /* fp_arg must be word-aligned (i.e., don't += len) to match
981 the function prologue. */
982 sp
= (sp
- si
->len
) & ~3;
983 write_memory (sp
, si
->data
, si
->len
);
984 si
= pop_stack_item (si
);
987 /* Finally, update the SP register. */
988 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
993 static const struct frame_unwind cris_frame_unwind
=
997 cris_frame_prev_register
1000 const struct frame_unwind
*
1001 cris_frame_sniffer (struct frame_info
*next_frame
)
1003 return &cris_frame_unwind
;
1007 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1009 struct cris_unwind_cache
*info
1010 = cris_frame_unwind_cache (next_frame
, this_cache
);
1014 static const struct frame_base cris_frame_base
=
1017 cris_frame_base_address
,
1018 cris_frame_base_address
,
1019 cris_frame_base_address
1022 /* Frames information. The definition of the struct frame_info is
1026 enum frame_type type;
1030 If the compilation option -fno-omit-frame-pointer is present the
1031 variable frame will be set to the content of R8 which is the frame
1034 The variable pc contains the address where execution is performed
1035 in the present frame. The innermost frame contains the current content
1036 of the register PC. All other frames contain the content of the
1037 register PC in the next frame.
1039 The variable `type' indicates the frame's type: normal, SIGTRAMP
1040 (associated with a signal handler), dummy (associated with a dummy
1043 The variable return_pc contains the address where execution should be
1044 resumed when the present frame has finished, the return address.
1046 The variable leaf_function is 1 if the return address is in the register
1047 SRP, and 0 if it is on the stack.
1049 Prologue instructions C-code.
1050 The prologue may consist of (-fno-omit-frame-pointer)
1054 move.d sp,r8 move.d sp,r8
1056 movem rY,[sp] movem rY,[sp]
1057 move.S rZ,[r8-U] move.S rZ,[r8-U]
1059 where 1 is a non-terminal function, and 2 is a leaf-function.
1061 Note that this assumption is extremely brittle, and will break at the
1062 slightest change in GCC's prologue.
1064 If local variables are declared or register contents are saved on stack
1065 the subq-instruction will be present with X as the number of bytes
1066 needed for storage. The reshuffle with respect to r8 may be performed
1067 with any size S (b, w, d) and any of the general registers Z={0..13}.
1068 The offset U should be representable by a signed 8-bit value in all cases.
1069 Thus, the prefix word is assumed to be immediate byte offset mode followed
1070 by another word containing the instruction.
1079 Prologue instructions C++-code.
1080 Case 1) and 2) in the C-code may be followed by
1082 move.d r10,rS ; this
1086 move.S [r8+U],rZ ; P4
1088 if any of the call parameters are stored. The host expects these
1089 instructions to be executed in order to get the call parameters right. */
1091 /* Examine the prologue of a function. The variable ip is the address of
1092 the first instruction of the prologue. The variable limit is the address
1093 of the first instruction after the prologue. The variable fi contains the
1094 information in struct frame_info. The variable frameless_p controls whether
1095 the entire prologue is examined (0) or just enough instructions to
1096 determine that it is a prologue (1). */
1099 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1100 struct cris_unwind_cache
*info
)
1102 /* Present instruction. */
1103 unsigned short insn
;
1105 /* Next instruction, lookahead. */
1106 unsigned short insn_next
;
1109 /* Is there a push fp? */
1112 /* Number of byte on stack used for local variables and movem. */
1115 /* Highest register number in a movem. */
1118 /* move.d r<source_register>,rS */
1119 short source_register
;
1124 /* This frame is with respect to a leaf until a push srp is found. */
1127 info
->leaf_function
= 1;
1130 /* Assume nothing on stack. */
1134 /* If we were called without a next_frame, that means we were called
1135 from cris_skip_prologue which already tried to find the end of the
1136 prologue through the symbol information. 64 instructions past current
1137 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1138 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
1140 /* Find the prologue instructions. */
1141 while (pc
> 0 && pc
< limit
)
1143 insn
= read_memory_unsigned_integer (pc
, 2);
1147 /* push <reg> 32 bit instruction */
1148 insn_next
= read_memory_unsigned_integer (pc
, 2);
1150 regno
= cris_get_operand2 (insn_next
);
1153 info
->sp_offset
+= 4;
1155 /* This check, meant to recognize srp, used to be regno ==
1156 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1157 if (insn_next
== 0xBE7E)
1161 info
->leaf_function
= 0;
1164 else if (insn_next
== 0x8FEE)
1169 info
->r8_offset
= info
->sp_offset
;
1173 else if (insn
== 0x866E)
1178 info
->uses_frame
= 1;
1182 else if (cris_get_operand2 (insn
) == SP_REGNUM
1183 && cris_get_mode (insn
) == 0x0000
1184 && cris_get_opcode (insn
) == 0x000A)
1189 info
->sp_offset
+= cris_get_quick_value (insn
);
1192 else if (cris_get_mode (insn
) == 0x0002
1193 && cris_get_opcode (insn
) == 0x000F
1194 && cris_get_size (insn
) == 0x0003
1195 && cris_get_operand1 (insn
) == SP_REGNUM
)
1197 /* movem r<regsave>,[sp] */
1198 regsave
= cris_get_operand2 (insn
);
1200 else if (cris_get_operand2 (insn
) == SP_REGNUM
1201 && ((insn
& 0x0F00) >> 8) == 0x0001
1202 && (cris_get_signed_offset (insn
) < 0))
1204 /* Immediate byte offset addressing prefix word with sp as base
1205 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1206 is between 64 and 128.
1207 movem r<regsave>,[sp=sp-<val>] */
1210 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1212 insn_next
= read_memory_unsigned_integer (pc
, 2);
1214 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1215 && cris_get_opcode (insn_next
) == 0x000F
1216 && cris_get_size (insn_next
) == 0x0003
1217 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
1219 regsave
= cris_get_operand2 (insn_next
);
1223 /* The prologue ended before the limit was reached. */
1228 else if (cris_get_mode (insn
) == 0x0001
1229 && cris_get_opcode (insn
) == 0x0009
1230 && cris_get_size (insn
) == 0x0002)
1232 /* move.d r<10..13>,r<0..15> */
1233 source_register
= cris_get_operand1 (insn
);
1235 /* FIXME? In the glibc solibs, the prologue might contain something
1236 like (this example taken from relocate_doit):
1238 sub.d 0xfffef426,$r0
1239 which isn't covered by the source_register check below. Question
1240 is whether to add a check for this combo, or make better use of
1241 the limit variable instead. */
1242 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1244 /* The prologue ended before the limit was reached. */
1249 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1250 /* The size is a fixed-size. */
1251 && ((insn
& 0x0F00) >> 8) == 0x0001
1252 /* A negative offset. */
1253 && (cris_get_signed_offset (insn
) < 0))
1255 /* move.S rZ,[r8-U] (?) */
1256 insn_next
= read_memory_unsigned_integer (pc
, 2);
1258 regno
= cris_get_operand2 (insn_next
);
1259 if ((regno
>= 0 && regno
< SP_REGNUM
)
1260 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1261 && cris_get_opcode (insn_next
) == 0x000F)
1263 /* move.S rZ,[r8-U] */
1268 /* The prologue ended before the limit was reached. */
1273 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1274 /* The size is a fixed-size. */
1275 && ((insn
& 0x0F00) >> 8) == 0x0001
1276 /* A positive offset. */
1277 && (cris_get_signed_offset (insn
) > 0))
1279 /* move.S [r8+U],rZ (?) */
1280 insn_next
= read_memory_unsigned_integer (pc
, 2);
1282 regno
= cris_get_operand2 (insn_next
);
1283 if ((regno
>= 0 && regno
< SP_REGNUM
)
1284 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1285 && cris_get_opcode (insn_next
) == 0x0009
1286 && cris_get_operand1 (insn_next
) == regno
)
1288 /* move.S [r8+U],rZ */
1293 /* The prologue ended before the limit was reached. */
1300 /* The prologue ended before the limit was reached. */
1306 /* We only want to know the end of the prologue when next_frame and info
1307 are NULL (called from cris_skip_prologue i.e.). */
1308 if (next_frame
== NULL
&& info
== NULL
)
1313 info
->size
= info
->sp_offset
;
1315 /* Compute the previous frame's stack pointer (which is also the
1316 frame's ID's stack address), and this frame's base pointer. */
1317 if (info
->uses_frame
)
1320 /* The SP was moved to the FP. This indicates that a new frame
1321 was created. Get THIS frame's FP value by unwinding it from
1323 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
1325 info
->base
= this_base
;
1326 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1328 /* The FP points at the last saved register. Adjust the FP back
1329 to before the first saved register giving the SP. */
1330 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1335 /* Assume that the FP is this frame's SP but with that pushed
1336 stack space added back. */
1337 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1338 info
->base
= this_base
;
1339 info
->prev_sp
= info
->base
+ info
->size
;
1342 /* Calculate the addresses for the saved registers on the stack. */
1343 /* FIXME: The address calculation should really be done on the fly while
1344 we're analyzing the prologue (we only hold one regsave value as it is
1346 val
= info
->sp_offset
;
1348 for (regno
= regsave
; regno
>= 0; regno
--)
1350 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1354 /* The previous frame's SP needed to be computed. Save the computed
1356 trad_frame_set_value (info
->saved_regs
, SP_REGNUM
, info
->prev_sp
);
1358 if (!info
->leaf_function
)
1360 /* SRP saved on the stack. But where? */
1361 if (info
->r8_offset
== 0)
1363 /* R8 not pushed yet. */
1364 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1368 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1369 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1373 /* The PC is found in SRP (the actual register or located on the stack). */
1374 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1380 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1381 struct cris_unwind_cache
*info
)
1385 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1386 meant to be a full-fledged prologue scanner. It is only needed for
1387 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1389 * PLT stubs (library calls)
1391 * signal trampolines
1393 For those cases, it is assumed that there is no actual prologue; that
1394 the stack pointer is not adjusted, and (as a consequence) the return
1395 address is not pushed onto the stack. */
1397 /* We only want to know the end of the prologue when next_frame and info
1398 are NULL (called from cris_skip_prologue i.e.). */
1399 if (next_frame
== NULL
&& info
== NULL
)
1404 /* The SP is assumed to be unaltered. */
1405 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1406 info
->base
= this_base
;
1407 info
->prev_sp
= this_base
;
1409 /* The PC is assumed to be found in SRP. */
1410 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1415 /* Advance pc beyond any function entry prologue instructions at pc
1416 to reach some "real" code. */
1418 /* Given a PC value corresponding to the start of a function, return the PC
1419 of the first instruction after the function prologue. */
1422 cris_skip_prologue (CORE_ADDR pc
)
1424 CORE_ADDR func_addr
, func_end
;
1425 struct symtab_and_line sal
;
1426 CORE_ADDR pc_after_prologue
;
1428 /* If we have line debugging information, then the end of the prologue
1429 should the first assembly instruction of the first source line. */
1430 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1432 sal
= find_pc_line (func_addr
, 0);
1433 if (sal
.end
> 0 && sal
.end
< func_end
)
1437 if (cris_version () == 32)
1438 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1440 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1442 return pc_after_prologue
;
1446 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1449 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1454 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1457 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &sp
);
1461 /* Use the program counter to determine the contents and size of a breakpoint
1462 instruction. It returns a pointer to a string of bytes that encode a
1463 breakpoint instruction, stores the length of the string to *lenptr, and
1464 adjusts pcptr (if necessary) to point to the actual memory location where
1465 the breakpoint should be inserted. */
1467 static const unsigned char *
1468 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1470 static unsigned char break8_insn
[] = {0x38, 0xe9};
1471 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1474 if (cris_mode () == cris_mode_guru
)
1475 return break15_insn
;
1480 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1484 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1486 int version
= cris_version ();
1488 switch (spec_reg
.applicable_version
)
1490 case cris_ver_version_all
:
1492 case cris_ver_warning
:
1493 /* Indeterminate/obsolete. */
1496 return (version
>= 0 && version
<= 3);
1498 return (version
>= 3);
1500 return (version
== 8 || version
== 9);
1502 return (version
>= 8);
1503 case cris_ver_v0_10
:
1504 return (version
>= 0 && version
<= 10);
1505 case cris_ver_v3_10
:
1506 return (version
>= 3 && version
<= 10);
1507 case cris_ver_v8_10
:
1508 return (version
>= 8 && version
<= 10);
1510 return (version
== 10);
1512 return (version
>= 10);
1514 return (version
>= 32);
1516 /* Invalid cris version. */
1521 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1522 register, -1 for an invalid register. */
1525 cris_register_size (int regno
)
1527 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1531 if (regno
>= 0 && regno
< NUM_GENREGS
)
1533 /* General registers (R0 - R15) are 32 bits. */
1536 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1538 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1539 Adjust regno accordingly. */
1540 spec_regno
= regno
- NUM_GENREGS
;
1542 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1544 if (cris_spec_regs
[i
].number
== spec_regno
1545 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1546 /* Go with the first applicable register. */
1547 return cris_spec_regs
[i
].reg_size
;
1549 /* Special register not applicable to this CRIS version. */
1552 else if (regno
>= PC_REGNUM
&& regno
< NUM_REGS
)
1554 /* This will apply to CRISv32 only where there are additional registers
1555 after the special registers (pseudo PC and support registers). */
1563 /* Nonzero if regno should not be fetched from the target. This is the case
1564 for unimplemented (size 0) and non-existant registers. */
1567 cris_cannot_fetch_register (int regno
)
1569 return ((regno
< 0 || regno
>= NUM_REGS
)
1570 || (cris_register_size (regno
) == 0));
1573 /* Nonzero if regno should not be written to the target, for various
1577 cris_cannot_store_register (int regno
)
1579 /* There are three kinds of registers we refuse to write to.
1580 1. Those that not implemented.
1581 2. Those that are read-only (depends on the processor mode).
1582 3. Those registers to which a write has no effect.
1585 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1586 /* Not implemented. */
1589 else if (regno
== VR_REGNUM
)
1593 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1594 /* Writing has no effect. */
1597 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1598 agent decide whether they are writable. */
1603 /* Nonzero if regno should not be fetched from the target. This is the case
1604 for unimplemented (size 0) and non-existant registers. */
1607 crisv32_cannot_fetch_register (int regno
)
1609 return ((regno
< 0 || regno
>= NUM_REGS
)
1610 || (cris_register_size (regno
) == 0));
1613 /* Nonzero if regno should not be written to the target, for various
1617 crisv32_cannot_store_register (int regno
)
1619 /* There are three kinds of registers we refuse to write to.
1620 1. Those that not implemented.
1621 2. Those that are read-only (depends on the processor mode).
1622 3. Those registers to which a write has no effect.
1625 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1626 /* Not implemented. */
1629 else if (regno
== VR_REGNUM
)
1633 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1634 /* Writing has no effect. */
1637 /* Many special registers are read-only in user mode. Let the debug
1638 agent decide whether they are writable. */
1643 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1644 of data in register regno. */
1646 static struct type
*
1647 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1649 if (regno
== PC_REGNUM
)
1650 return builtin_type_void_func_ptr
;
1651 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1652 return builtin_type_void_data_ptr
;
1653 else if ((regno
>= 0 && regno
< SP_REGNUM
)
1654 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1655 /* Note: R8 taken care of previous clause. */
1656 return builtin_type_uint32
;
1657 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1658 return builtin_type_uint16
;
1659 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1660 return builtin_type_uint8
;
1662 /* Invalid (unimplemented) register. */
1663 return builtin_type_int0
;
1666 static struct type
*
1667 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1669 if (regno
== PC_REGNUM
)
1670 return builtin_type_void_func_ptr
;
1671 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1672 return builtin_type_void_data_ptr
;
1673 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1674 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1675 || (regno
== PID_REGNUM
)
1676 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1677 /* Note: R8 and SP taken care of by previous clause. */
1678 return builtin_type_uint32
;
1679 else if (regno
== WZ_REGNUM
)
1680 return builtin_type_uint16
;
1681 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1682 return builtin_type_uint8
;
1685 /* Invalid (unimplemented) register. Should not happen as there are
1686 no unimplemented CRISv32 registers. */
1687 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1688 return builtin_type_int0
;
1692 /* Stores a function return value of type type, where valbuf is the address
1693 of the value to be stored. */
1695 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1698 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1702 int len
= TYPE_LENGTH (type
);
1706 /* Put the return value in R10. */
1707 val
= extract_unsigned_integer (valbuf
, len
);
1708 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1712 /* Put the return value in R10 and R11. */
1713 val
= extract_unsigned_integer (valbuf
, 4);
1714 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1715 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1716 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1719 error (_("cris_store_return_value: type length too large."));
1722 /* Return the name of register regno as a string. Return NULL for an invalid or
1723 unimplemented register. */
1726 cris_special_register_name (int regno
)
1731 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1732 Adjust regno accordingly. */
1733 spec_regno
= regno
- NUM_GENREGS
;
1735 /* Assume nothing about the layout of the cris_spec_regs struct
1737 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1739 if (cris_spec_regs
[i
].number
== spec_regno
1740 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1741 /* Go with the first applicable register. */
1742 return cris_spec_regs
[i
].name
;
1744 /* Special register not applicable to this CRIS version. */
1749 cris_register_name (int regno
)
1751 static char *cris_genreg_names
[] =
1752 { "r0", "r1", "r2", "r3", \
1753 "r4", "r5", "r6", "r7", \
1754 "r8", "r9", "r10", "r11", \
1755 "r12", "r13", "sp", "pc" };
1757 if (regno
>= 0 && regno
< NUM_GENREGS
)
1759 /* General register. */
1760 return cris_genreg_names
[regno
];
1762 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1764 return cris_special_register_name (regno
);
1768 /* Invalid register. */
1774 crisv32_register_name (int regno
)
1776 static char *crisv32_genreg_names
[] =
1777 { "r0", "r1", "r2", "r3", \
1778 "r4", "r5", "r6", "r7", \
1779 "r8", "r9", "r10", "r11", \
1780 "r12", "r13", "sp", "acr"
1783 static char *crisv32_sreg_names
[] =
1784 { "s0", "s1", "s2", "s3", \
1785 "s4", "s5", "s6", "s7", \
1786 "s8", "s9", "s10", "s11", \
1787 "s12", "s13", "s14", "s15"
1790 if (regno
>= 0 && regno
< NUM_GENREGS
)
1792 /* General register. */
1793 return crisv32_genreg_names
[regno
];
1795 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1797 return cris_special_register_name (regno
);
1799 else if (regno
== PC_REGNUM
)
1803 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1805 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1809 /* Invalid register. */
1814 /* Convert DWARF register number REG to the appropriate register
1815 number used by GDB. */
1818 cris_dwarf2_reg_to_regnum (int reg
)
1820 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1821 numbering, MOF is 18).
1822 Adapted from gcc/config/cris/cris.h. */
1823 static int cris_dwarf_regmap
[] = {
1835 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1836 regnum
= cris_dwarf_regmap
[reg
];
1839 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
1844 /* DWARF-2 frame support. */
1847 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1848 struct dwarf2_frame_state_reg
*reg
,
1849 struct frame_info
*next_frame
)
1851 /* The return address column. */
1852 if (regnum
== PC_REGNUM
)
1853 reg
->how
= DWARF2_FRAME_REG_RA
;
1855 /* The call frame address. */
1856 else if (regnum
== SP_REGNUM
)
1857 reg
->how
= DWARF2_FRAME_REG_CFA
;
1860 /* Extract from an array regbuf containing the raw register state a function
1861 return value of type type, and copy that, in virtual format, into
1864 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1867 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1871 int len
= TYPE_LENGTH (type
);
1875 /* Get the return value from R10. */
1876 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1877 store_unsigned_integer (valbuf
, len
, val
);
1881 /* Get the return value from R10 and R11. */
1882 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1883 store_unsigned_integer (valbuf
, 4, val
);
1884 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1885 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1888 error (_("cris_extract_return_value: type length too large"));
1891 /* Handle the CRIS return value convention. */
1893 static enum return_value_convention
1894 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1895 struct regcache
*regcache
, gdb_byte
*readbuf
,
1896 const gdb_byte
*writebuf
)
1898 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1899 || TYPE_CODE (type
) == TYPE_CODE_UNION
1900 || TYPE_LENGTH (type
) > 8)
1901 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1902 goes on the stack. */
1903 return RETURN_VALUE_STRUCT_CONVENTION
;
1906 cris_extract_return_value (type
, regcache
, readbuf
);
1908 cris_store_return_value (type
, regcache
, writebuf
);
1910 return RETURN_VALUE_REGISTER_CONVENTION
;
1913 /* Returns 1 if the given type will be passed by pointer rather than
1916 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1920 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1922 return (TYPE_LENGTH (type
) > 8);
1925 /* Calculates a value that measures how good inst_args constraints an
1926 instruction. It stems from cris_constraint, found in cris-dis.c. */
1929 constraint (unsigned int insn
, const signed char *inst_args
,
1930 inst_env_type
*inst_env
)
1935 const char *s
= inst_args
;
1941 if ((insn
& 0x30) == 0x30)
1946 /* A prefix operand. */
1947 if (inst_env
->prefix_found
)
1953 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1954 valid "push" size. In case of special register, it may be != 4. */
1955 if (inst_env
->prefix_found
)
1961 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1969 tmp
= (insn
>> 0xC) & 0xF;
1971 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1973 /* Since we match four bits, we will give a value of
1974 4 - 1 = 3 in a match. If there is a corresponding
1975 exact match of a special register in another pattern, it
1976 will get a value of 4, which will be higher. This should
1977 be correct in that an exact pattern would match better that
1979 Note that there is a reason for not returning zero; the
1980 pattern for "clear" is partly matched in the bit-pattern
1981 (the two lower bits must be zero), while the bit-pattern
1982 for a move from a special register is matched in the
1983 register constraint.
1984 This also means we will will have a race condition if
1985 there is a partly match in three bits in the bit pattern. */
1986 if (tmp
== cris_spec_regs
[i
].number
)
1993 if (cris_spec_regs
[i
].name
== NULL
)
2000 /* Returns the number of bits set in the variable value. */
2003 number_of_bits (unsigned int value
)
2005 int number_of_bits
= 0;
2009 number_of_bits
+= 1;
2010 value
&= (value
- 1);
2012 return number_of_bits
;
2015 /* Finds the address that should contain the single step breakpoint(s).
2016 It stems from code in cris-dis.c. */
2019 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
2022 int max_level_of_match
= -1;
2023 int max_matched
= -1;
2026 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
2028 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
2029 && ((cris_opcodes
[i
].lose
& insn
) == 0)
2030 /* Only CRISv10 instructions, please. */
2031 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
2033 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
2034 if (level_of_match
>= 0)
2037 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
2038 if (level_of_match
> max_level_of_match
)
2041 max_level_of_match
= level_of_match
;
2042 if (level_of_match
== 16)
2044 /* All bits matched, cannot find better. */
2054 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2055 actually an internal error. */
2058 find_step_target (inst_env_type
*inst_env
)
2062 unsigned short insn
;
2064 /* Create a local register image and set the initial state. */
2065 for (i
= 0; i
< NUM_GENREGS
; i
++)
2067 inst_env
->reg
[i
] = (unsigned long) read_register (i
);
2069 offset
= NUM_GENREGS
;
2070 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2072 inst_env
->preg
[i
] = (unsigned long) read_register (offset
+ i
);
2074 inst_env
->branch_found
= 0;
2075 inst_env
->slot_needed
= 0;
2076 inst_env
->delay_slot_pc_active
= 0;
2077 inst_env
->prefix_found
= 0;
2078 inst_env
->invalid
= 0;
2079 inst_env
->xflag_found
= 0;
2080 inst_env
->disable_interrupt
= 0;
2082 /* Look for a step target. */
2085 /* Read an instruction from the client. */
2086 insn
= read_memory_unsigned_integer (inst_env
->reg
[PC_REGNUM
], 2);
2088 /* If the instruction is not in a delay slot the new content of the
2089 PC is [PC] + 2. If the instruction is in a delay slot it is not
2090 that simple. Since a instruction in a delay slot cannot change
2091 the content of the PC, it does not matter what value PC will have.
2092 Just make sure it is a valid instruction. */
2093 if (!inst_env
->delay_slot_pc_active
)
2095 inst_env
->reg
[PC_REGNUM
] += 2;
2099 inst_env
->delay_slot_pc_active
= 0;
2100 inst_env
->reg
[PC_REGNUM
] = inst_env
->delay_slot_pc
;
2102 /* Analyse the present instruction. */
2103 i
= find_cris_op (insn
, inst_env
);
2106 inst_env
->invalid
= 1;
2110 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
2112 } while (!inst_env
->invalid
2113 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2114 || inst_env
->slot_needed
));
2118 /* There is no hardware single-step support. The function find_step_target
2119 digs through the opcodes in order to find all possible targets.
2120 Either one ordinary target or two targets for branches may be found. */
2123 cris_software_single_step (enum target_signal ignore
, int insert_breakpoints
)
2125 inst_env_type inst_env
;
2127 if (insert_breakpoints
)
2129 /* Analyse the present instruction environment and insert
2131 int status
= find_step_target (&inst_env
);
2134 /* Could not find a target. Things are likely to go downhill
2136 warning (_("CRIS software single step could not find a step target."));
2140 /* Insert at most two breakpoints. One for the next PC content
2141 and possibly another one for a branch, jump, etc. */
2142 CORE_ADDR next_pc
= (CORE_ADDR
) inst_env
.reg
[PC_REGNUM
];
2143 insert_single_step_breakpoint (next_pc
);
2144 if (inst_env
.branch_found
2145 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2147 CORE_ADDR branch_target_address
2148 = (CORE_ADDR
) inst_env
.branch_break_address
;
2149 insert_single_step_breakpoint (branch_target_address
);
2154 remove_single_step_breakpoints ();
2157 /* Calculates the prefix value for quick offset addressing mode. */
2160 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2162 /* It's invalid to be in a delay slot. You can't have a prefix to this
2163 instruction (not 100% sure). */
2164 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2166 inst_env
->invalid
= 1;
2170 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2171 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2173 /* A prefix doesn't change the xflag_found. But the rest of the flags
2175 inst_env
->slot_needed
= 0;
2176 inst_env
->prefix_found
= 1;
2179 /* Updates the autoincrement register. The size of the increment is derived
2180 from the size of the operation. The PC is always kept aligned on even
2184 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2186 if (size
== INST_BYTE_SIZE
)
2188 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2190 /* The PC must be word aligned, so increase the PC with one
2191 word even if the size is byte. */
2192 if (cris_get_operand1 (inst
) == REG_PC
)
2194 inst_env
->reg
[REG_PC
] += 1;
2197 else if (size
== INST_WORD_SIZE
)
2199 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2201 else if (size
== INST_DWORD_SIZE
)
2203 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2208 inst_env
->invalid
= 1;
2212 /* Just a forward declaration. */
2214 static unsigned long get_data_from_address (unsigned short *inst
,
2217 /* Calculates the prefix value for the general case of offset addressing
2221 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2226 /* It's invalid to be in a delay slot. */
2227 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2229 inst_env
->invalid
= 1;
2233 /* The calculation of prefix_value used to be after process_autoincrement,
2234 but that fails for an instruction such as jsr [$r0+12] which is encoded
2235 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2236 mustn't be incremented until we have read it and what it points at. */
2237 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2239 /* The offset is an indirection of the contents of the operand1 register. */
2240 inst_env
->prefix_value
+=
2241 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
2243 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2245 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2248 /* A prefix doesn't change the xflag_found. But the rest of the flags
2250 inst_env
->slot_needed
= 0;
2251 inst_env
->prefix_found
= 1;
2254 /* Calculates the prefix value for the index addressing mode. */
2257 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2259 /* It's invalid to be in a delay slot. I can't see that it's possible to
2260 have a prefix to this instruction. So I will treat this as invalid. */
2261 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2263 inst_env
->invalid
= 1;
2267 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2269 /* The offset is the operand2 value shifted the size of the instruction
2271 inst_env
->prefix_value
+=
2272 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2274 /* If the PC is operand1 (base) the address used is the address after
2275 the main instruction, i.e. address + 2 (the PC is already compensated
2276 for the prefix operation). */
2277 if (cris_get_operand1 (inst
) == REG_PC
)
2279 inst_env
->prefix_value
+= 2;
2282 /* A prefix doesn't change the xflag_found. But the rest of the flags
2284 inst_env
->slot_needed
= 0;
2285 inst_env
->xflag_found
= 0;
2286 inst_env
->prefix_found
= 1;
2289 /* Calculates the prefix value for the double indirect addressing mode. */
2292 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2297 /* It's invalid to be in a delay slot. */
2298 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2300 inst_env
->invalid
= 1;
2304 /* The prefix value is one dereference of the contents of the operand1
2306 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2307 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
2309 /* Check if the mode is autoincrement. */
2310 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2312 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2315 /* A prefix doesn't change the xflag_found. But the rest of the flags
2317 inst_env
->slot_needed
= 0;
2318 inst_env
->xflag_found
= 0;
2319 inst_env
->prefix_found
= 1;
2322 /* Finds the destination for a branch with 8-bits offset. */
2325 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2330 /* If we have a prefix or are in a delay slot it's bad. */
2331 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2333 inst_env
->invalid
= 1;
2337 /* We have a branch, find out where the branch will land. */
2338 offset
= cris_get_branch_short_offset (inst
);
2340 /* Check if the offset is signed. */
2341 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2346 /* The offset ends with the sign bit, set it to zero. The address
2347 should always be word aligned. */
2348 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2350 inst_env
->branch_found
= 1;
2351 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2353 inst_env
->slot_needed
= 1;
2354 inst_env
->prefix_found
= 0;
2355 inst_env
->xflag_found
= 0;
2356 inst_env
->disable_interrupt
= 1;
2359 /* Finds the destination for a branch with 16-bits offset. */
2362 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2366 /* If we have a prefix or is in a delay slot it's bad. */
2367 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2369 inst_env
->invalid
= 1;
2373 /* We have a branch, find out the offset for the branch. */
2374 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2376 /* The instruction is one word longer than normal, so add one word
2378 inst_env
->reg
[REG_PC
] += 2;
2380 inst_env
->branch_found
= 1;
2381 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2384 inst_env
->slot_needed
= 1;
2385 inst_env
->prefix_found
= 0;
2386 inst_env
->xflag_found
= 0;
2387 inst_env
->disable_interrupt
= 1;
2390 /* Handles the ABS instruction. */
2393 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2398 /* ABS can't have a prefix, so it's bad if it does. */
2399 if (inst_env
->prefix_found
)
2401 inst_env
->invalid
= 1;
2405 /* Check if the operation affects the PC. */
2406 if (cris_get_operand2 (inst
) == REG_PC
)
2409 /* It's invalid to change to the PC if we are in a delay slot. */
2410 if (inst_env
->slot_needed
)
2412 inst_env
->invalid
= 1;
2416 value
= (long) inst_env
->reg
[REG_PC
];
2418 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2419 if (value
!= SIGNED_DWORD_MASK
)
2422 inst_env
->reg
[REG_PC
] = (long) value
;
2426 inst_env
->slot_needed
= 0;
2427 inst_env
->prefix_found
= 0;
2428 inst_env
->xflag_found
= 0;
2429 inst_env
->disable_interrupt
= 0;
2432 /* Handles the ADDI instruction. */
2435 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2437 /* It's invalid to have the PC as base register. And ADDI can't have
2439 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2441 inst_env
->invalid
= 1;
2445 inst_env
->slot_needed
= 0;
2446 inst_env
->prefix_found
= 0;
2447 inst_env
->xflag_found
= 0;
2448 inst_env
->disable_interrupt
= 0;
2451 /* Handles the ASR instruction. */
2454 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2457 unsigned long value
;
2458 unsigned long signed_extend_mask
= 0;
2460 /* ASR can't have a prefix, so check that it doesn't. */
2461 if (inst_env
->prefix_found
)
2463 inst_env
->invalid
= 1;
2467 /* Check if the PC is the target register. */
2468 if (cris_get_operand2 (inst
) == REG_PC
)
2470 /* It's invalid to change the PC in a delay slot. */
2471 if (inst_env
->slot_needed
)
2473 inst_env
->invalid
= 1;
2476 /* Get the number of bits to shift. */
2477 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2478 value
= inst_env
->reg
[REG_PC
];
2480 /* Find out how many bits the operation should apply to. */
2481 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2483 if (value
& SIGNED_BYTE_MASK
)
2485 signed_extend_mask
= 0xFF;
2486 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2487 signed_extend_mask
= ~signed_extend_mask
;
2489 value
= value
>> shift_steps
;
2490 value
|= signed_extend_mask
;
2492 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2493 inst_env
->reg
[REG_PC
] |= value
;
2495 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2497 if (value
& SIGNED_WORD_MASK
)
2499 signed_extend_mask
= 0xFFFF;
2500 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2501 signed_extend_mask
= ~signed_extend_mask
;
2503 value
= value
>> shift_steps
;
2504 value
|= signed_extend_mask
;
2506 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2507 inst_env
->reg
[REG_PC
] |= value
;
2509 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2511 if (value
& SIGNED_DWORD_MASK
)
2513 signed_extend_mask
= 0xFFFFFFFF;
2514 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2515 signed_extend_mask
= ~signed_extend_mask
;
2517 value
= value
>> shift_steps
;
2518 value
|= signed_extend_mask
;
2519 inst_env
->reg
[REG_PC
] = value
;
2522 inst_env
->slot_needed
= 0;
2523 inst_env
->prefix_found
= 0;
2524 inst_env
->xflag_found
= 0;
2525 inst_env
->disable_interrupt
= 0;
2528 /* Handles the ASRQ instruction. */
2531 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2535 unsigned long value
;
2536 unsigned long signed_extend_mask
= 0;
2538 /* ASRQ can't have a prefix, so check that it doesn't. */
2539 if (inst_env
->prefix_found
)
2541 inst_env
->invalid
= 1;
2545 /* Check if the PC is the target register. */
2546 if (cris_get_operand2 (inst
) == REG_PC
)
2549 /* It's invalid to change the PC in a delay slot. */
2550 if (inst_env
->slot_needed
)
2552 inst_env
->invalid
= 1;
2555 /* The shift size is given as a 5 bit quick value, i.e. we don't
2556 want the the sign bit of the quick value. */
2557 shift_steps
= cris_get_asr_shift_steps (inst
);
2558 value
= inst_env
->reg
[REG_PC
];
2559 if (value
& SIGNED_DWORD_MASK
)
2561 signed_extend_mask
= 0xFFFFFFFF;
2562 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2563 signed_extend_mask
= ~signed_extend_mask
;
2565 value
= value
>> shift_steps
;
2566 value
|= signed_extend_mask
;
2567 inst_env
->reg
[REG_PC
] = value
;
2569 inst_env
->slot_needed
= 0;
2570 inst_env
->prefix_found
= 0;
2571 inst_env
->xflag_found
= 0;
2572 inst_env
->disable_interrupt
= 0;
2575 /* Handles the AX, EI and SETF instruction. */
2578 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2580 if (inst_env
->prefix_found
)
2582 inst_env
->invalid
= 1;
2585 /* Check if the instruction is setting the X flag. */
2586 if (cris_is_xflag_bit_on (inst
))
2588 inst_env
->xflag_found
= 1;
2592 inst_env
->xflag_found
= 0;
2594 inst_env
->slot_needed
= 0;
2595 inst_env
->prefix_found
= 0;
2596 inst_env
->disable_interrupt
= 1;
2599 /* Checks if the instruction is in assign mode. If so, it updates the assign
2600 register. Note that check_assign assumes that the caller has checked that
2601 there is a prefix to this instruction. The mode check depends on this. */
2604 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2606 /* Check if it's an assign addressing mode. */
2607 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2609 /* Assign the prefix value to operand 1. */
2610 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2614 /* Handles the 2-operand BOUND instruction. */
2617 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2619 /* It's invalid to have the PC as the index operand. */
2620 if (cris_get_operand2 (inst
) == REG_PC
)
2622 inst_env
->invalid
= 1;
2625 /* Check if we have a prefix. */
2626 if (inst_env
->prefix_found
)
2628 check_assign (inst
, inst_env
);
2630 /* Check if this is an autoincrement mode. */
2631 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2633 /* It's invalid to change the PC in a delay slot. */
2634 if (inst_env
->slot_needed
)
2636 inst_env
->invalid
= 1;
2639 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2641 inst_env
->slot_needed
= 0;
2642 inst_env
->prefix_found
= 0;
2643 inst_env
->xflag_found
= 0;
2644 inst_env
->disable_interrupt
= 0;
2647 /* Handles the 3-operand BOUND instruction. */
2650 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2652 /* It's an error if we haven't got a prefix. And it's also an error
2653 if the PC is the destination register. */
2654 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2656 inst_env
->invalid
= 1;
2659 inst_env
->slot_needed
= 0;
2660 inst_env
->prefix_found
= 0;
2661 inst_env
->xflag_found
= 0;
2662 inst_env
->disable_interrupt
= 0;
2665 /* Clears the status flags in inst_env. */
2668 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2670 /* It's an error if we have got a prefix. */
2671 if (inst_env
->prefix_found
)
2673 inst_env
->invalid
= 1;
2677 inst_env
->slot_needed
= 0;
2678 inst_env
->prefix_found
= 0;
2679 inst_env
->xflag_found
= 0;
2680 inst_env
->disable_interrupt
= 0;
2683 /* Clears the status flags in inst_env. */
2686 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2688 /* It's an error if we have got a prefix. */
2689 if (inst_env
->prefix_found
)
2691 inst_env
->invalid
= 1;
2695 inst_env
->slot_needed
= 0;
2696 inst_env
->prefix_found
= 0;
2697 inst_env
->xflag_found
= 0;
2698 inst_env
->disable_interrupt
= 1;
2701 /* Handles the CLEAR instruction if it's in register mode. */
2704 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2706 /* Check if the target is the PC. */
2707 if (cris_get_operand2 (inst
) == REG_PC
)
2709 /* The instruction will clear the instruction's size bits. */
2710 int clear_size
= cris_get_clear_size (inst
);
2711 if (clear_size
== INST_BYTE_SIZE
)
2713 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2715 if (clear_size
== INST_WORD_SIZE
)
2717 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2719 if (clear_size
== INST_DWORD_SIZE
)
2721 inst_env
->delay_slot_pc
= 0x0;
2723 /* The jump will be delayed with one delay slot. So we need a delay
2725 inst_env
->slot_needed
= 1;
2726 inst_env
->delay_slot_pc_active
= 1;
2730 /* The PC will not change => no delay slot. */
2731 inst_env
->slot_needed
= 0;
2733 inst_env
->prefix_found
= 0;
2734 inst_env
->xflag_found
= 0;
2735 inst_env
->disable_interrupt
= 0;
2738 /* Handles the TEST instruction if it's in register mode. */
2741 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2743 /* It's an error if we have got a prefix. */
2744 if (inst_env
->prefix_found
)
2746 inst_env
->invalid
= 1;
2749 inst_env
->slot_needed
= 0;
2750 inst_env
->prefix_found
= 0;
2751 inst_env
->xflag_found
= 0;
2752 inst_env
->disable_interrupt
= 0;
2756 /* Handles the CLEAR and TEST instruction if the instruction isn't
2757 in register mode. */
2760 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2762 /* Check if we are in a prefix mode. */
2763 if (inst_env
->prefix_found
)
2765 /* The only way the PC can change is if this instruction is in
2766 assign addressing mode. */
2767 check_assign (inst
, inst_env
);
2769 /* Indirect mode can't change the PC so just check if the mode is
2771 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2773 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2775 inst_env
->slot_needed
= 0;
2776 inst_env
->prefix_found
= 0;
2777 inst_env
->xflag_found
= 0;
2778 inst_env
->disable_interrupt
= 0;
2781 /* Checks that the PC isn't the destination register or the instructions has
2785 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2787 /* It's invalid to have the PC as the destination. The instruction can't
2789 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2791 inst_env
->invalid
= 1;
2795 inst_env
->slot_needed
= 0;
2796 inst_env
->prefix_found
= 0;
2797 inst_env
->xflag_found
= 0;
2798 inst_env
->disable_interrupt
= 0;
2801 /* Checks that the instruction doesn't have a prefix. */
2804 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2806 /* The instruction can't have a prefix. */
2807 if (inst_env
->prefix_found
)
2809 inst_env
->invalid
= 1;
2813 inst_env
->slot_needed
= 0;
2814 inst_env
->prefix_found
= 0;
2815 inst_env
->xflag_found
= 0;
2816 inst_env
->disable_interrupt
= 1;
2819 /* Checks that the PC isn't the destination register and that the instruction
2820 doesn't have a prefix. */
2823 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2825 /* It's invalid to have the PC as the destination. The instruction can't
2827 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2829 inst_env
->invalid
= 1;
2833 inst_env
->slot_needed
= 0;
2834 inst_env
->prefix_found
= 0;
2835 inst_env
->xflag_found
= 0;
2836 inst_env
->disable_interrupt
= 1;
2839 /* Handles the register mode JUMP instruction. */
2842 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2844 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2845 you can't have a prefix. */
2846 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2848 inst_env
->invalid
= 1;
2852 /* Just change the PC. */
2853 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2854 inst_env
->slot_needed
= 0;
2855 inst_env
->prefix_found
= 0;
2856 inst_env
->xflag_found
= 0;
2857 inst_env
->disable_interrupt
= 1;
2860 /* Handles the JUMP instruction for all modes except register. */
2863 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2865 unsigned long newpc
;
2868 /* It's invalid to do a JUMP in a delay slot. */
2869 if (inst_env
->slot_needed
)
2871 inst_env
->invalid
= 1;
2875 /* Check if we have a prefix. */
2876 if (inst_env
->prefix_found
)
2878 check_assign (inst
, inst_env
);
2880 /* Get the new value for the the PC. */
2882 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2887 /* Get the new value for the PC. */
2888 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2889 newpc
= read_memory_unsigned_integer (address
, 4);
2891 /* Check if we should increment a register. */
2892 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2894 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2897 inst_env
->reg
[REG_PC
] = newpc
;
2899 inst_env
->slot_needed
= 0;
2900 inst_env
->prefix_found
= 0;
2901 inst_env
->xflag_found
= 0;
2902 inst_env
->disable_interrupt
= 1;
2905 /* Handles moves to special registers (aka P-register) for all modes. */
2908 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2910 if (inst_env
->prefix_found
)
2912 /* The instruction has a prefix that means we are only interested if
2913 the instruction is in assign mode. */
2914 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2916 /* The prefix handles the problem if we are in a delay slot. */
2917 if (cris_get_operand1 (inst
) == REG_PC
)
2919 /* Just take care of the assign. */
2920 check_assign (inst
, inst_env
);
2924 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2926 /* The instruction doesn't have a prefix, the only case left that we
2927 are interested in is the autoincrement mode. */
2928 if (cris_get_operand1 (inst
) == REG_PC
)
2930 /* If the PC is to be incremented it's invalid to be in a
2932 if (inst_env
->slot_needed
)
2934 inst_env
->invalid
= 1;
2938 /* The increment depends on the size of the special register. */
2939 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2941 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2943 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2945 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2949 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2953 inst_env
->slot_needed
= 0;
2954 inst_env
->prefix_found
= 0;
2955 inst_env
->xflag_found
= 0;
2956 inst_env
->disable_interrupt
= 1;
2959 /* Handles moves from special registers (aka P-register) for all modes
2963 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2965 if (inst_env
->prefix_found
)
2967 /* The instruction has a prefix that means we are only interested if
2968 the instruction is in assign mode. */
2969 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2971 /* The prefix handles the problem if we are in a delay slot. */
2972 if (cris_get_operand1 (inst
) == REG_PC
)
2974 /* Just take care of the assign. */
2975 check_assign (inst
, inst_env
);
2979 /* The instruction doesn't have a prefix, the only case left that we
2980 are interested in is the autoincrement mode. */
2981 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2983 if (cris_get_operand1 (inst
) == REG_PC
)
2985 /* If the PC is to be incremented it's invalid to be in a
2987 if (inst_env
->slot_needed
)
2989 inst_env
->invalid
= 1;
2993 /* The increment depends on the size of the special register. */
2994 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2996 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2998 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
3000 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
3004 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
3008 inst_env
->slot_needed
= 0;
3009 inst_env
->prefix_found
= 0;
3010 inst_env
->xflag_found
= 0;
3011 inst_env
->disable_interrupt
= 1;
3014 /* Handles moves from special registers (aka P-register) when the mode
3018 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
3020 /* Register mode move from special register can't have a prefix. */
3021 if (inst_env
->prefix_found
)
3023 inst_env
->invalid
= 1;
3027 if (cris_get_operand1 (inst
) == REG_PC
)
3029 /* It's invalid to change the PC in a delay slot. */
3030 if (inst_env
->slot_needed
)
3032 inst_env
->invalid
= 1;
3035 /* The destination is the PC, the jump will have a delay slot. */
3036 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
3037 inst_env
->slot_needed
= 1;
3038 inst_env
->delay_slot_pc_active
= 1;
3042 /* If the destination isn't PC, there will be no jump. */
3043 inst_env
->slot_needed
= 0;
3045 inst_env
->prefix_found
= 0;
3046 inst_env
->xflag_found
= 0;
3047 inst_env
->disable_interrupt
= 1;
3050 /* Handles the MOVEM from memory to general register instruction. */
3053 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3055 if (inst_env
->prefix_found
)
3057 /* The prefix handles the problem if we are in a delay slot. Is the
3058 MOVEM instruction going to change the PC? */
3059 if (cris_get_operand2 (inst
) >= REG_PC
)
3061 inst_env
->reg
[REG_PC
] =
3062 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
3064 /* The assign value is the value after the increment. Normally, the
3065 assign value is the value before the increment. */
3066 if ((cris_get_operand1 (inst
) == REG_PC
)
3067 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3069 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3070 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3075 /* Is the MOVEM instruction going to change the PC? */
3076 if (cris_get_operand2 (inst
) == REG_PC
)
3078 /* It's invalid to change the PC in a delay slot. */
3079 if (inst_env
->slot_needed
)
3081 inst_env
->invalid
= 1;
3084 inst_env
->reg
[REG_PC
] =
3085 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3088 /* The increment is not depending on the size, instead it's depending
3089 on the number of registers loaded from memory. */
3090 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3092 /* It's invalid to change the PC in a delay slot. */
3093 if (inst_env
->slot_needed
)
3095 inst_env
->invalid
= 1;
3098 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3101 inst_env
->slot_needed
= 0;
3102 inst_env
->prefix_found
= 0;
3103 inst_env
->xflag_found
= 0;
3104 inst_env
->disable_interrupt
= 0;
3107 /* Handles the MOVEM to memory from general register instruction. */
3110 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3112 if (inst_env
->prefix_found
)
3114 /* The assign value is the value after the increment. Normally, the
3115 assign value is the value before the increment. */
3116 if ((cris_get_operand1 (inst
) == REG_PC
) &&
3117 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3119 /* The prefix handles the problem if we are in a delay slot. */
3120 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3121 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3126 /* The increment is not depending on the size, instead it's depending
3127 on the number of registers loaded to memory. */
3128 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3130 /* It's invalid to change the PC in a delay slot. */
3131 if (inst_env
->slot_needed
)
3133 inst_env
->invalid
= 1;
3136 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3139 inst_env
->slot_needed
= 0;
3140 inst_env
->prefix_found
= 0;
3141 inst_env
->xflag_found
= 0;
3142 inst_env
->disable_interrupt
= 0;
3145 /* Handles the intructions that's not yet implemented, by setting
3146 inst_env->invalid to true. */
3149 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3151 inst_env
->invalid
= 1;
3154 /* Handles the XOR instruction. */
3157 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3159 /* XOR can't have a prefix. */
3160 if (inst_env
->prefix_found
)
3162 inst_env
->invalid
= 1;
3166 /* Check if the PC is the target. */
3167 if (cris_get_operand2 (inst
) == REG_PC
)
3169 /* It's invalid to change the PC in a delay slot. */
3170 if (inst_env
->slot_needed
)
3172 inst_env
->invalid
= 1;
3175 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3177 inst_env
->slot_needed
= 0;
3178 inst_env
->prefix_found
= 0;
3179 inst_env
->xflag_found
= 0;
3180 inst_env
->disable_interrupt
= 0;
3183 /* Handles the MULS instruction. */
3186 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3188 /* MULS/U can't have a prefix. */
3189 if (inst_env
->prefix_found
)
3191 inst_env
->invalid
= 1;
3195 /* Consider it invalid if the PC is the target. */
3196 if (cris_get_operand2 (inst
) == REG_PC
)
3198 inst_env
->invalid
= 1;
3201 inst_env
->slot_needed
= 0;
3202 inst_env
->prefix_found
= 0;
3203 inst_env
->xflag_found
= 0;
3204 inst_env
->disable_interrupt
= 0;
3207 /* Handles the MULU instruction. */
3210 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3212 /* MULS/U can't have a prefix. */
3213 if (inst_env
->prefix_found
)
3215 inst_env
->invalid
= 1;
3219 /* Consider it invalid if the PC is the target. */
3220 if (cris_get_operand2 (inst
) == REG_PC
)
3222 inst_env
->invalid
= 1;
3225 inst_env
->slot_needed
= 0;
3226 inst_env
->prefix_found
= 0;
3227 inst_env
->xflag_found
= 0;
3228 inst_env
->disable_interrupt
= 0;
3231 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3232 The MOVE instruction is the move from source to register. */
3235 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3236 unsigned long source1
, unsigned long source2
)
3238 unsigned long pc_mask
;
3239 unsigned long operation_mask
;
3241 /* Find out how many bits the operation should apply to. */
3242 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3244 pc_mask
= 0xFFFFFF00;
3245 operation_mask
= 0xFF;
3247 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3249 pc_mask
= 0xFFFF0000;
3250 operation_mask
= 0xFFFF;
3252 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3255 operation_mask
= 0xFFFFFFFF;
3259 /* The size is out of range. */
3260 inst_env
->invalid
= 1;
3264 /* The instruction just works on uw_operation_mask bits. */
3265 source2
&= operation_mask
;
3266 source1
&= operation_mask
;
3268 /* Now calculate the result. The opcode's 3 first bits separates
3269 the different actions. */
3270 switch (cris_get_opcode (inst
) & 7)
3280 case 2: /* subtract */
3284 case 3: /* compare */
3296 inst_env
->invalid
= 1;
3302 /* Make sure that the result doesn't contain more than the instruction
3304 source2
&= operation_mask
;
3306 /* Calculate the new breakpoint address. */
3307 inst_env
->reg
[REG_PC
] &= pc_mask
;
3308 inst_env
->reg
[REG_PC
] |= source1
;
3312 /* Extends the value from either byte or word size to a dword. If the mode
3313 is zero extend then the value is extended with zero. If instead the mode
3314 is signed extend the sign bit of the value is taken into consideration. */
3316 static unsigned long
3317 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3319 /* The size can be either byte or word, check which one it is.
3320 Don't check the highest bit, it's indicating if it's a zero
3322 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3327 /* Check if the instruction is signed extend. If so, check if value has
3329 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3331 value
|= SIGNED_WORD_EXTEND_MASK
;
3339 /* Check if the instruction is signed extend. If so, check if value has
3341 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3343 value
|= SIGNED_BYTE_EXTEND_MASK
;
3346 /* The size should now be dword. */
3347 cris_set_size_to_dword (inst
);
3351 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3352 instruction. The MOVE instruction is the move from source to register. */
3355 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3356 inst_env_type
*inst_env
)
3358 unsigned long operand1
;
3359 unsigned long operand2
;
3361 /* It's invalid to have a prefix to the instruction. This is a register
3362 mode instruction and can't have a prefix. */
3363 if (inst_env
->prefix_found
)
3365 inst_env
->invalid
= 1;
3368 /* Check if the instruction has PC as its target. */
3369 if (cris_get_operand2 (inst
) == REG_PC
)
3371 if (inst_env
->slot_needed
)
3373 inst_env
->invalid
= 1;
3376 /* The instruction has the PC as its target register. */
3377 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3378 operand2
= inst_env
->reg
[REG_PC
];
3380 /* Check if it's a extend, signed or zero instruction. */
3381 if (cris_get_opcode (inst
) < 4)
3383 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3385 /* Calculate the PC value after the instruction, i.e. where the
3386 breakpoint should be. The order of the udw_operands is vital. */
3387 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3389 inst_env
->slot_needed
= 0;
3390 inst_env
->prefix_found
= 0;
3391 inst_env
->xflag_found
= 0;
3392 inst_env
->disable_interrupt
= 0;
3395 /* Returns the data contained at address. The size of the data is derived from
3396 the size of the operation. If the instruction is a zero or signed
3397 extend instruction, the size field is changed in instruction. */
3399 static unsigned long
3400 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3402 int size
= cris_get_size (*inst
);
3403 unsigned long value
;
3405 /* If it's an extend instruction we don't want the signed extend bit,
3406 because it influences the size. */
3407 if (cris_get_opcode (*inst
) < 4)
3409 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3411 /* Is there a need for checking the size? Size should contain the number of
3414 value
= read_memory_unsigned_integer (address
, size
);
3416 /* Check if it's an extend, signed or zero instruction. */
3417 if (cris_get_opcode (*inst
) < 4)
3419 value
= do_sign_or_zero_extend (value
, inst
);
3424 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3425 instructions. The MOVE instruction is the move from source to register. */
3428 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3429 inst_env_type
*inst_env
)
3431 unsigned long operand2
;
3432 unsigned long operand3
;
3434 check_assign (inst
, inst_env
);
3435 if (cris_get_operand2 (inst
) == REG_PC
)
3437 operand2
= inst_env
->reg
[REG_PC
];
3439 /* Get the value of the third operand. */
3440 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3442 /* Calculate the PC value after the instruction, i.e. where the
3443 breakpoint should be. The order of the udw_operands is vital. */
3444 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3446 inst_env
->slot_needed
= 0;
3447 inst_env
->prefix_found
= 0;
3448 inst_env
->xflag_found
= 0;
3449 inst_env
->disable_interrupt
= 0;
3452 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3453 OR instructions. Note that for this to work as expected, the calling
3454 function must have made sure that there is a prefix to this instruction. */
3457 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3458 inst_env_type
*inst_env
)
3460 unsigned long operand2
;
3461 unsigned long operand3
;
3463 if (cris_get_operand1 (inst
) == REG_PC
)
3465 /* The PC will be changed by the instruction. */
3466 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3468 /* Get the value of the third operand. */
3469 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3471 /* Calculate the PC value after the instruction, i.e. where the
3472 breakpoint should be. */
3473 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3475 inst_env
->slot_needed
= 0;
3476 inst_env
->prefix_found
= 0;
3477 inst_env
->xflag_found
= 0;
3478 inst_env
->disable_interrupt
= 0;
3481 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3482 instructions. The MOVE instruction is the move from source to register. */
3485 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3486 inst_env_type
*inst_env
)
3488 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3490 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3491 SUB, AND or OR something weird is going on (if everything works these
3492 instructions should end up in the three operand version). */
3493 inst_env
->invalid
= 1;
3498 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3500 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3502 inst_env
->slot_needed
= 0;
3503 inst_env
->prefix_found
= 0;
3504 inst_env
->xflag_found
= 0;
3505 inst_env
->disable_interrupt
= 0;
3508 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3509 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3510 source to register. */
3513 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3514 inst_env_type
*inst_env
)
3516 unsigned long operand1
;
3517 unsigned long operand2
;
3518 unsigned long operand3
;
3521 /* The instruction is either an indirect or autoincrement addressing mode.
3522 Check if the destination register is the PC. */
3523 if (cris_get_operand2 (inst
) == REG_PC
)
3525 /* Must be done here, get_data_from_address may change the size
3527 size
= cris_get_size (inst
);
3528 operand2
= inst_env
->reg
[REG_PC
];
3530 /* Get the value of the third operand, i.e. the indirect operand. */
3531 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3532 operand3
= get_data_from_address (&inst
, operand1
);
3534 /* Calculate the PC value after the instruction, i.e. where the
3535 breakpoint should be. The order of the udw_operands is vital. */
3536 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3538 /* If this is an autoincrement addressing mode, check if the increment
3540 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3542 /* Get the size field. */
3543 size
= cris_get_size (inst
);
3545 /* If it's an extend instruction we don't want the signed extend bit,
3546 because it influences the size. */
3547 if (cris_get_opcode (inst
) < 4)
3549 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3551 process_autoincrement (size
, inst
, inst_env
);
3553 inst_env
->slot_needed
= 0;
3554 inst_env
->prefix_found
= 0;
3555 inst_env
->xflag_found
= 0;
3556 inst_env
->disable_interrupt
= 0;
3559 /* Handles the two-operand addressing mode, all modes except register, for
3560 the ADD, SUB CMP, AND and OR instruction. */
3563 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3564 inst_env_type
*inst_env
)
3566 if (inst_env
->prefix_found
)
3568 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3570 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3572 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3574 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3578 /* The mode is invalid for a prefixed base instruction. */
3579 inst_env
->invalid
= 1;
3585 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3589 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3592 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3594 unsigned long operand1
;
3595 unsigned long operand2
;
3597 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3598 instruction and can't have a prefix. */
3599 if (inst_env
->prefix_found
)
3601 inst_env
->invalid
= 1;
3605 /* Check if the instruction has PC as its target. */
3606 if (cris_get_operand2 (inst
) == REG_PC
)
3608 if (inst_env
->slot_needed
)
3610 inst_env
->invalid
= 1;
3613 operand1
= cris_get_quick_value (inst
);
3614 operand2
= inst_env
->reg
[REG_PC
];
3616 /* The size should now be dword. */
3617 cris_set_size_to_dword (&inst
);
3619 /* Calculate the PC value after the instruction, i.e. where the
3620 breakpoint should be. */
3621 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3623 inst_env
->slot_needed
= 0;
3624 inst_env
->prefix_found
= 0;
3625 inst_env
->xflag_found
= 0;
3626 inst_env
->disable_interrupt
= 0;
3629 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3632 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3634 unsigned long operand1
;
3635 unsigned long operand2
;
3637 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3638 instruction and can't have a prefix. */
3639 if (inst_env
->prefix_found
)
3641 inst_env
->invalid
= 1;
3644 /* Check if the instruction has PC as its target. */
3645 if (cris_get_operand2 (inst
) == REG_PC
)
3647 if (inst_env
->slot_needed
)
3649 inst_env
->invalid
= 1;
3652 /* The instruction has the PC as its target register. */
3653 operand1
= cris_get_quick_value (inst
);
3654 operand2
= inst_env
->reg
[REG_PC
];
3656 /* The quick value is signed, so check if we must do a signed extend. */
3657 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3660 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3662 /* The size should now be dword. */
3663 cris_set_size_to_dword (&inst
);
3665 /* Calculate the PC value after the instruction, i.e. where the
3666 breakpoint should be. */
3667 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3669 inst_env
->slot_needed
= 0;
3670 inst_env
->prefix_found
= 0;
3671 inst_env
->xflag_found
= 0;
3672 inst_env
->disable_interrupt
= 0;
3675 /* Translate op_type to a function and call it. */
3678 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3679 inst_env_type
*inst_env
)
3683 case cris_not_implemented_op
:
3684 not_implemented_op (inst
, inst_env
);
3688 abs_op (inst
, inst_env
);
3692 addi_op (inst
, inst_env
);
3696 asr_op (inst
, inst_env
);
3700 asrq_op (inst
, inst_env
);
3703 case cris_ax_ei_setf_op
:
3704 ax_ei_setf_op (inst
, inst_env
);
3707 case cris_bdap_prefix
:
3708 bdap_prefix (inst
, inst_env
);
3711 case cris_biap_prefix
:
3712 biap_prefix (inst
, inst_env
);
3716 break_op (inst
, inst_env
);
3719 case cris_btst_nop_op
:
3720 btst_nop_op (inst
, inst_env
);
3723 case cris_clearf_di_op
:
3724 clearf_di_op (inst
, inst_env
);
3727 case cris_dip_prefix
:
3728 dip_prefix (inst
, inst_env
);
3731 case cris_dstep_logshift_mstep_neg_not_op
:
3732 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3735 case cris_eight_bit_offset_branch_op
:
3736 eight_bit_offset_branch_op (inst
, inst_env
);
3739 case cris_move_mem_to_reg_movem_op
:
3740 move_mem_to_reg_movem_op (inst
, inst_env
);
3743 case cris_move_reg_to_mem_movem_op
:
3744 move_reg_to_mem_movem_op (inst
, inst_env
);
3747 case cris_move_to_preg_op
:
3748 move_to_preg_op (inst
, inst_env
);
3752 muls_op (inst
, inst_env
);
3756 mulu_op (inst
, inst_env
);
3759 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3760 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3763 case cris_none_reg_mode_clear_test_op
:
3764 none_reg_mode_clear_test_op (inst
, inst_env
);
3767 case cris_none_reg_mode_jump_op
:
3768 none_reg_mode_jump_op (inst
, inst_env
);
3771 case cris_none_reg_mode_move_from_preg_op
:
3772 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3775 case cris_quick_mode_add_sub_op
:
3776 quick_mode_add_sub_op (inst
, inst_env
);
3779 case cris_quick_mode_and_cmp_move_or_op
:
3780 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3783 case cris_quick_mode_bdap_prefix
:
3784 quick_mode_bdap_prefix (inst
, inst_env
);
3787 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3788 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3791 case cris_reg_mode_clear_op
:
3792 reg_mode_clear_op (inst
, inst_env
);
3795 case cris_reg_mode_jump_op
:
3796 reg_mode_jump_op (inst
, inst_env
);
3799 case cris_reg_mode_move_from_preg_op
:
3800 reg_mode_move_from_preg_op (inst
, inst_env
);
3803 case cris_reg_mode_test_op
:
3804 reg_mode_test_op (inst
, inst_env
);
3808 scc_op (inst
, inst_env
);
3811 case cris_sixteen_bit_offset_branch_op
:
3812 sixteen_bit_offset_branch_op (inst
, inst_env
);
3815 case cris_three_operand_add_sub_cmp_and_or_op
:
3816 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3819 case cris_three_operand_bound_op
:
3820 three_operand_bound_op (inst
, inst_env
);
3823 case cris_two_operand_bound_op
:
3824 two_operand_bound_op (inst
, inst_env
);
3828 xor_op (inst
, inst_env
);
3833 /* This wrapper is to avoid cris_get_assembler being called before
3834 exec_bfd has been set. */
3837 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3839 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3840 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3841 disassembler, even when there is no BFD. Does something like
3842 "gdb; target remote; disassmeble *0x123" work? */
3843 gdb_assert (exec_bfd
!= NULL
);
3844 print_insn
= cris_get_disassembler (exec_bfd
);
3845 gdb_assert (print_insn
!= NULL
);
3846 return print_insn (addr
, info
);
3849 /* Copied from <asm/elf.h>. */
3850 typedef unsigned long elf_greg_t
;
3852 /* Same as user_regs_struct struct in <asm/user.h>. */
3853 #define CRISV10_ELF_NGREG 35
3854 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3856 #define CRISV32_ELF_NGREG 32
3857 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3859 /* Unpack an elf_gregset_t into GDB's register cache. */
3862 supply_gregset (elf_gregset_t
*gregsetp
)
3864 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3866 elf_greg_t
*regp
= *gregsetp
;
3867 static char zerobuf
[4] = {0};
3869 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3870 knows about the actual size of each register so that's no problem. */
3871 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3873 regcache_raw_supply (current_regcache
, i
, (char *)®p
[i
]);
3876 if (tdep
->cris_version
== 32)
3878 /* Needed to set pseudo-register PC for CRISv32. */
3879 /* FIXME: If ERP is in a delay slot at this point then the PC will
3880 be wrong. Issue a warning to alert the user. */
3881 regcache_raw_supply (current_regcache
, PC_REGNUM
,
3882 (char *)®p
[ERP_REGNUM
]);
3884 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3885 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3889 /* Use a local version of this function to get the correct types for
3890 regsets, until multi-arch core support is ready. */
3893 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
3894 int which
, CORE_ADDR reg_addr
)
3896 elf_gregset_t gregset
;
3901 if (core_reg_size
!= sizeof (elf_gregset_t
)
3902 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3904 warning (_("wrong size gregset struct in core file"));
3908 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3909 supply_gregset (&gregset
);
3913 /* We've covered all the kinds of registers we know about here,
3914 so this must be something we wouldn't know what to do with
3915 anyway. Just ignore it. */
3920 static struct core_fns cris_elf_core_fns
=
3922 bfd_target_elf_flavour
, /* core_flavour */
3923 default_check_format
, /* check_format */
3924 default_core_sniffer
, /* core_sniffer */
3925 fetch_core_registers
, /* core_read_registers */
3929 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3932 _initialize_cris_tdep (void)
3934 static struct cmd_list_element
*cris_set_cmdlist
;
3935 static struct cmd_list_element
*cris_show_cmdlist
;
3937 struct cmd_list_element
*c
;
3939 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3941 /* CRIS-specific user-commands. */
3942 add_setshow_uinteger_cmd ("cris-version", class_support
,
3943 &usr_cmd_cris_version
,
3944 _("Set the current CRIS version."),
3945 _("Show the current CRIS version."),
3947 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3950 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3951 &setlist
, &showlist
);
3953 add_setshow_enum_cmd ("cris-mode", class_support
,
3954 cris_modes
, &usr_cmd_cris_mode
,
3955 _("Set the current CRIS mode."),
3956 _("Show the current CRIS mode."),
3958 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3959 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3961 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3962 &setlist
, &showlist
);
3964 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3965 &usr_cmd_cris_dwarf2_cfi
,
3966 _("Set the usage of Dwarf-2 CFI for CRIS."),
3967 _("Show the usage of Dwarf-2 CFI for CRIS."),
3968 _("Set this to \"off\" if using gcc-cris < R59."),
3969 set_cris_dwarf2_cfi
,
3970 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3971 &setlist
, &showlist
);
3973 deprecated_add_core_fns (&cris_elf_core_fns
);
3976 /* Prints out all target specific values. */
3979 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3981 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3984 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3985 tdep
->cris_version
);
3986 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3988 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3989 tdep
->cris_dwarf2_cfi
);
3994 set_cris_version (char *ignore_args
, int from_tty
,
3995 struct cmd_list_element
*c
)
3997 struct gdbarch_info info
;
3999 usr_cmd_cris_version_valid
= 1;
4001 /* Update the current architecture, if needed. */
4002 gdbarch_info_init (&info
);
4003 if (!gdbarch_update_p (info
))
4004 internal_error (__FILE__
, __LINE__
,
4005 _("cris_gdbarch_update: failed to update architecture."));
4009 set_cris_mode (char *ignore_args
, int from_tty
,
4010 struct cmd_list_element
*c
)
4012 struct gdbarch_info info
;
4014 /* Update the current architecture, if needed. */
4015 gdbarch_info_init (&info
);
4016 if (!gdbarch_update_p (info
))
4017 internal_error (__FILE__
, __LINE__
,
4018 "cris_gdbarch_update: failed to update architecture.");
4022 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
4023 struct cmd_list_element
*c
)
4025 struct gdbarch_info info
;
4027 /* Update the current architecture, if needed. */
4028 gdbarch_info_init (&info
);
4029 if (!gdbarch_update_p (info
))
4030 internal_error (__FILE__
, __LINE__
,
4031 _("cris_gdbarch_update: failed to update architecture."));
4034 static struct gdbarch
*
4035 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4037 struct gdbarch
*gdbarch
;
4038 struct gdbarch_tdep
*tdep
;
4041 if (usr_cmd_cris_version_valid
)
4043 /* Trust the user's CRIS version setting. */
4044 cris_version
= usr_cmd_cris_version
;
4046 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4052 /* Assume it's CRIS version 10. */
4056 /* Make the current settings visible to the user. */
4057 usr_cmd_cris_version
= cris_version
;
4059 /* Find a candidate among the list of pre-declared architectures. */
4060 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4062 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4064 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4065 == usr_cmd_cris_version
)
4066 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4067 == usr_cmd_cris_mode
)
4068 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4069 == usr_cmd_cris_dwarf2_cfi
))
4070 return arches
->gdbarch
;
4073 /* No matching architecture was found. Create a new one. */
4074 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4075 gdbarch
= gdbarch_alloc (&info
, tdep
);
4077 tdep
->cris_version
= usr_cmd_cris_version
;
4078 tdep
->cris_mode
= usr_cmd_cris_mode
;
4079 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4081 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4082 switch (info
.byte_order
)
4084 case BFD_ENDIAN_LITTLE
:
4088 case BFD_ENDIAN_BIG
:
4089 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: big endian byte order in info"));
4093 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: unknown byte order in info"));
4096 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4097 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
4098 cris_reg_struct_has_addr
);
4099 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
4101 set_gdbarch_sp_regnum (gdbarch
, 14);
4103 /* Length of ordinary registers used in push_word and a few other
4104 places. register_size() is the real way to know how big a
4107 set_gdbarch_double_bit (gdbarch
, 64);
4108 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
4109 which means we have to set this explicitly. */
4110 set_gdbarch_long_double_bit (gdbarch
, 64);
4112 /* The total amount of space needed to store (in an array called registers)
4113 GDB's copy of the machine's register state. Note: We can not use
4114 cris_register_size at this point, since it relies on current_gdbarch
4116 switch (tdep
->cris_version
)
4124 /* Old versions; not supported. */
4125 internal_error (__FILE__
, __LINE__
,
4126 _("cris_gdbarch_init: unsupported CRIS version"));
4131 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4132 P7 (32 bits), and P15 (32 bits) have been implemented. */
4133 set_gdbarch_pc_regnum (gdbarch
, 15);
4134 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4135 /* There are 32 registers (some of which may not be implemented). */
4136 set_gdbarch_num_regs (gdbarch
, 32);
4137 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4138 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4139 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4141 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4145 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4146 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4147 and pseudo-register PC (32 bits). */
4148 set_gdbarch_pc_regnum (gdbarch
, 32);
4149 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4150 /* 32 registers + pseudo-register PC + 16 support registers. */
4151 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4152 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4154 set_gdbarch_cannot_store_register
4155 (gdbarch
, crisv32_cannot_store_register
);
4156 set_gdbarch_cannot_fetch_register
4157 (gdbarch
, crisv32_cannot_fetch_register
);
4159 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4161 set_gdbarch_single_step_through_delay
4162 (gdbarch
, crisv32_single_step_through_delay
);
4167 internal_error (__FILE__
, __LINE__
,
4168 _("cris_gdbarch_init: unknown CRIS version"));
4171 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4172 have the same ABI). */
4173 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4174 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4175 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4176 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4178 /* The stack grows downward. */
4179 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4181 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4183 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4184 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4185 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
4187 if (tdep
->cris_dwarf2_cfi
== 1)
4189 /* Hook in the Dwarf-2 frame sniffer. */
4190 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4191 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4192 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
4195 if (tdep
->cris_mode
!= cris_mode_guru
)
4197 frame_unwind_append_sniffer (gdbarch
, cris_sigtramp_frame_sniffer
);
4200 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
4201 frame_base_set_default (gdbarch
, &cris_frame_base
);
4203 set_solib_svr4_fetch_link_map_offsets
4204 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
4206 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4207 disassembler, even when there is no BFD. Does something like
4208 "gdb; target remote; disassmeble *0x123" work? */
4209 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);