1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h" /* For struct link_map_offsets. */
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
62 /* Register numbers of various important registers.
63 CRIS_FP_REGNUM Contains address of executing stack frame.
64 STR_REGNUM Contains the address of structure return values.
65 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
66 ARG1_REGNUM Contains the first parameter to a function.
67 ARG2_REGNUM Contains the second parameter to a function.
68 ARG3_REGNUM Contains the third parameter to a function.
69 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
70 SP_REGNUM Contains address of top of stack.
71 PC_REGNUM Contains address of next instruction.
72 SRP_REGNUM Subroutine return pointer register.
73 BRP_REGNUM Breakpoint return pointer register. */
77 /* Enums with respect to the general registers, valid for all
87 /* Enums with respect to the special registers, some of which may not be
88 applicable to all CRIS versions. */
106 extern const struct cris_spec_reg cris_spec_regs
[];
108 /* CRIS version, set via the user command 'set cris-version'. Affects
109 register names and sizes.*/
110 static unsigned int usr_cmd_cris_version
;
112 /* Indicates whether to trust the above variable. */
113 static int usr_cmd_cris_version_valid
= 0;
115 /* Whether to make use of Dwarf-2 CFI (default on). */
116 static int usr_cmd_cris_dwarf2_cfi
= 1;
118 /* CRIS architecture specific information. */
121 unsigned int cris_version
;
125 /* Functions for accessing target dependent data. */
130 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
133 /* Sigtramp identification code copied from i386-linux-tdep.c. */
135 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
136 #define SIGTRAMP_OFFSET0 0
137 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
138 #define SIGTRAMP_OFFSET1 4
140 static const unsigned short sigtramp_code
[] =
142 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
143 SIGTRAMP_INSN1
/* break 13 */
146 #define SIGTRAMP_LEN (sizeof sigtramp_code)
148 /* Note: same length as normal sigtramp code. */
150 static const unsigned short rt_sigtramp_code
[] =
152 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
153 SIGTRAMP_INSN1
/* break 13 */
156 /* If PC is in a sigtramp routine, return the address of the start of
157 the routine. Otherwise, return 0. */
160 cris_sigtramp_start (struct frame_info
*next_frame
)
162 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
163 unsigned short buf
[SIGTRAMP_LEN
];
165 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
168 if (buf
[0] != SIGTRAMP_INSN0
)
170 if (buf
[0] != SIGTRAMP_INSN1
)
173 pc
-= SIGTRAMP_OFFSET1
;
174 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
178 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
184 /* If PC is in a RT sigtramp routine, return the address of the start of
185 the routine. Otherwise, return 0. */
188 cris_rt_sigtramp_start (struct frame_info
*next_frame
)
190 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
191 unsigned short buf
[SIGTRAMP_LEN
];
193 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
196 if (buf
[0] != SIGTRAMP_INSN0
)
198 if (buf
[0] != SIGTRAMP_INSN1
)
201 pc
-= SIGTRAMP_OFFSET1
;
202 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
206 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
212 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
213 routine, return the address of the associated sigcontext structure. */
216 cris_sigcontext_addr (struct frame_info
*next_frame
)
222 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
223 sp
= extract_unsigned_integer (buf
, 4);
225 /* Look for normal sigtramp frame first. */
226 pc
= cris_sigtramp_start (next_frame
);
229 /* struct signal_frame (arch/cris/kernel/signal.c) contains
230 struct sigcontext as its first member, meaning the SP points to
235 pc
= cris_rt_sigtramp_start (next_frame
);
238 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
239 a struct ucontext, which in turn contains a struct sigcontext.
241 4 + 4 + 128 to struct ucontext, then
242 4 + 4 + 12 to struct sigcontext. */
246 error ("Couldn't recognize signal trampoline.");
250 struct cris_unwind_cache
252 /* The previous frame's inner most stack address. Used as this
253 frame ID's stack_addr. */
255 /* The frame's base, optionally used by the high-level debug info. */
258 /* How far the SP and r8 (FP) have been offset from the start of
259 the stack frame (as defined by the previous frame's stack
265 /* From old frame_extra_info struct. */
269 /* Table indicating the location of each and every register. */
270 struct trad_frame_saved_reg
*saved_regs
;
273 static struct cris_unwind_cache
*
274 cris_sigtramp_frame_unwind_cache (struct frame_info
*next_frame
,
277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
278 struct cris_unwind_cache
*info
;
286 return (*this_cache
);
288 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
289 (*this_cache
) = info
;
290 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
292 /* Zero all fields. */
298 info
->uses_frame
= 0;
300 info
->leaf_function
= 0;
302 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
303 info
->base
= extract_unsigned_integer (buf
, 4);
305 addr
= cris_sigcontext_addr (next_frame
);
307 /* Layout of the sigcontext struct:
310 unsigned long oldmask;
314 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
316 for (i
= 0; i
<= 13; i
++)
317 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
319 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
320 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
321 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
322 /* Note: IRP is off by 2 at this point. There's no point in correcting it
323 though since that will mean that the backtrace will show a PC different
324 from what is shown when stopped. */
325 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
326 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[IRP_REGNUM
];
327 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (24 * 4);
333 cris_sigtramp_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
334 struct frame_id
*this_id
)
336 struct cris_unwind_cache
*cache
=
337 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
338 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
341 /* Forward declaration. */
343 static void cris_frame_prev_register (struct frame_info
*next_frame
,
344 void **this_prologue_cache
,
345 int regnum
, int *optimizedp
,
346 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
347 int *realnump
, void *bufferp
);
349 cris_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
351 int regnum
, int *optimizedp
,
352 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
353 int *realnump
, void *valuep
)
355 /* Make sure we've initialized the cache. */
356 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
357 cris_frame_prev_register (next_frame
, this_cache
, regnum
,
358 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
361 static const struct frame_unwind cris_sigtramp_frame_unwind
=
364 cris_sigtramp_frame_this_id
,
365 cris_sigtramp_frame_prev_register
368 static const struct frame_unwind
*
369 cris_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
371 if (cris_sigtramp_start (next_frame
)
372 || cris_rt_sigtramp_start (next_frame
))
373 return &cris_sigtramp_frame_unwind
;
378 /* The instruction environment needed to find single-step breakpoints. */
380 struct instruction_environment
382 unsigned long reg
[NUM_GENREGS
];
383 unsigned long preg
[NUM_SPECREGS
];
384 unsigned long branch_break_address
;
385 unsigned long delay_slot_pc
;
386 unsigned long prefix_value
;
391 int delay_slot_pc_active
;
393 int disable_interrupt
;
396 /* Save old breakpoints in order to restore the state before a single_step.
397 At most, two breakpoints will have to be remembered. */
399 char binsn_quantum
[BREAKPOINT_MAX
];
400 static binsn_quantum break_mem
[2];
401 static CORE_ADDR next_pc
= 0;
402 static CORE_ADDR branch_target_address
= 0;
403 static unsigned char branch_break_inserted
= 0;
405 /* Machine-dependencies in CRIS for opcodes. */
407 /* Instruction sizes. */
408 enum cris_instruction_sizes
415 /* Addressing modes. */
416 enum cris_addressing_modes
423 /* Prefix addressing modes. */
424 enum cris_prefix_addressing_modes
426 PREFIX_INDEX_MODE
= 2,
427 PREFIX_ASSIGN_MODE
= 3,
429 /* Handle immediate byte offset addressing mode prefix format. */
430 PREFIX_OFFSET_MODE
= 2
433 /* Masks for opcodes. */
434 enum cris_opcode_masks
436 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
437 SIGNED_EXTEND_BIT_MASK
= 0x2,
438 SIGNED_BYTE_MASK
= 0x80,
439 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
440 SIGNED_WORD_MASK
= 0x8000,
441 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
442 SIGNED_DWORD_MASK
= 0x80000000,
443 SIGNED_QUICK_VALUE_MASK
= 0x20,
444 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
447 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
455 cris_get_operand2 (unsigned short insn
)
457 return ((insn
& 0xF000) >> 12);
461 cris_get_mode (unsigned short insn
)
463 return ((insn
& 0x0C00) >> 10);
467 cris_get_opcode (unsigned short insn
)
469 return ((insn
& 0x03C0) >> 6);
473 cris_get_size (unsigned short insn
)
475 return ((insn
& 0x0030) >> 4);
479 cris_get_operand1 (unsigned short insn
)
481 return (insn
& 0x000F);
484 /* Additional functions in order to handle opcodes. */
487 cris_get_quick_value (unsigned short insn
)
489 return (insn
& 0x003F);
493 cris_get_bdap_quick_offset (unsigned short insn
)
495 return (insn
& 0x00FF);
499 cris_get_branch_short_offset (unsigned short insn
)
501 return (insn
& 0x00FF);
505 cris_get_asr_shift_steps (unsigned long value
)
507 return (value
& 0x3F);
511 cris_get_clear_size (unsigned short insn
)
513 return ((insn
) & 0xC000);
517 cris_is_signed_extend_bit_on (unsigned short insn
)
519 return (((insn
) & 0x20) == 0x20);
523 cris_is_xflag_bit_on (unsigned short insn
)
525 return (((insn
) & 0x1000) == 0x1000);
529 cris_set_size_to_dword (unsigned short *insn
)
536 cris_get_signed_offset (unsigned short insn
)
538 return ((signed char) (insn
& 0x00FF));
541 /* Calls an op function given the op-type, working on the insn and the
543 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
545 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
546 struct gdbarch_list
*);
548 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
550 static void set_cris_version (char *ignore_args
, int from_tty
,
551 struct cmd_list_element
*c
);
553 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
554 struct cmd_list_element
*c
);
556 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
557 struct frame_info
*next_frame
,
558 struct cris_unwind_cache
*info
);
560 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
561 struct frame_info
*next_frame
);
563 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
564 struct frame_info
*next_frame
);
566 /* When arguments must be pushed onto the stack, they go on in reverse
567 order. The below implements a FILO (stack) to do this.
568 Copied from d10v-tdep.c. */
573 struct stack_item
*prev
;
577 static struct stack_item
*
578 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
580 struct stack_item
*si
;
581 si
= xmalloc (sizeof (struct stack_item
));
582 si
->data
= xmalloc (len
);
585 memcpy (si
->data
, contents
, len
);
589 static struct stack_item
*
590 pop_stack_item (struct stack_item
*si
)
592 struct stack_item
*dead
= si
;
599 /* Put here the code to store, into fi->saved_regs, the addresses of
600 the saved registers of frame described by FRAME_INFO. This
601 includes special registers such as pc and fp saved in special ways
602 in the stack frame. sp is even more special: the address we return
603 for it IS the sp for the next frame. */
605 struct cris_unwind_cache
*
606 cris_frame_unwind_cache (struct frame_info
*next_frame
,
607 void **this_prologue_cache
)
610 struct cris_unwind_cache
*info
;
613 if ((*this_prologue_cache
))
614 return (*this_prologue_cache
);
616 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
617 (*this_prologue_cache
) = info
;
618 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
620 /* Zero all fields. */
626 info
->uses_frame
= 0;
628 info
->leaf_function
= 0;
630 /* Prologue analysis does the rest... */
631 cris_scan_prologue (frame_func_unwind (next_frame
), next_frame
, info
);
636 /* Given a GDB frame, determine the address of the calling function's
637 frame. This will be used to create a new GDB frame struct. */
640 cris_frame_this_id (struct frame_info
*next_frame
,
641 void **this_prologue_cache
,
642 struct frame_id
*this_id
)
644 struct cris_unwind_cache
*info
645 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
650 /* The FUNC is easy. */
651 func
= frame_func_unwind (next_frame
);
653 /* Hopefully the prologue analysis either correctly determined the
654 frame's base (which is the SP from the previous frame), or set
655 that base to "NULL". */
656 base
= info
->prev_sp
;
660 id
= frame_id_build (base
, func
);
666 cris_frame_prev_register (struct frame_info
*next_frame
,
667 void **this_prologue_cache
,
668 int regnum
, int *optimizedp
,
669 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
670 int *realnump
, void *bufferp
)
672 struct cris_unwind_cache
*info
673 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
674 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
675 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
678 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
679 dummy frame. The frame ID's base needs to match the TOS value
680 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
683 static struct frame_id
684 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
686 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
687 frame_pc_unwind (next_frame
));
691 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
693 /* Align to the size of an instruction (so that they can safely be
694 pushed onto the stack). */
699 cris_push_dummy_code (struct gdbarch
*gdbarch
,
700 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
701 struct value
**args
, int nargs
,
702 struct type
*value_type
,
703 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
705 /* Allocate space sufficient for a breakpoint. */
707 /* Store the address of that breakpoint */
709 /* CRIS always starts the call at the callee's entry point. */
715 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
716 struct regcache
*regcache
, CORE_ADDR bp_addr
,
717 int nargs
, struct value
**args
, CORE_ADDR sp
,
718 int struct_return
, CORE_ADDR struct_addr
)
727 /* The function's arguments and memory allocated by gdb for the arguments to
728 point at reside in separate areas on the stack.
729 Both frame pointers grow toward higher addresses. */
733 struct stack_item
*si
= NULL
;
735 /* Push the return address. */
736 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
738 /* Are we returning a value using a structure return or a normal value
739 return? struct_addr is the address of the reserved space for the return
740 structure to be written on the stack. */
743 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
746 /* Now load as many as possible of the first arguments into registers,
747 and push the rest onto the stack. */
748 argreg
= ARG1_REGNUM
;
751 for (argnum
= 0; argnum
< nargs
; argnum
++)
758 len
= TYPE_LENGTH (value_type (args
[argnum
]));
759 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
761 /* How may registers worth of storage do we need for this argument? */
762 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
764 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
766 /* Data passed by value. Fits in available register(s). */
767 for (i
= 0; i
< reg_demand
; i
++)
769 regcache_cooked_write_unsigned (regcache
, argreg
,
770 *(unsigned long *) val
);
775 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
777 /* Data passed by value. Does not fit in available register(s).
778 Use the register(s) first, then the stack. */
779 for (i
= 0; i
< reg_demand
; i
++)
781 if (argreg
<= ARG4_REGNUM
)
783 regcache_cooked_write_unsigned (regcache
, argreg
,
784 *(unsigned long *) val
);
790 /* Push item for later so that pushed arguments
791 come in the right order. */
792 si
= push_stack_item (si
, val
, 4);
797 else if (len
> (2 * 4))
800 internal_error (__FILE__
, __LINE__
, "We don't do this");
804 /* Data passed by value. No available registers. Put it on
806 si
= push_stack_item (si
, val
, len
);
812 /* fp_arg must be word-aligned (i.e., don't += len) to match
813 the function prologue. */
814 sp
= (sp
- si
->len
) & ~3;
815 write_memory (sp
, si
->data
, si
->len
);
816 si
= pop_stack_item (si
);
819 /* Finally, update the SP register. */
820 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
825 static const struct frame_unwind cris_frame_unwind
= {
828 cris_frame_prev_register
831 const struct frame_unwind
*
832 cris_frame_sniffer (struct frame_info
*next_frame
)
834 return &cris_frame_unwind
;
838 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
840 struct cris_unwind_cache
*info
841 = cris_frame_unwind_cache (next_frame
, this_cache
);
845 static const struct frame_base cris_frame_base
= {
847 cris_frame_base_address
,
848 cris_frame_base_address
,
849 cris_frame_base_address
852 /* Frames information. The definition of the struct frame_info is
856 enum frame_type type;
860 If the compilation option -fno-omit-frame-pointer is present the
861 variable frame will be set to the content of R8 which is the frame
864 The variable pc contains the address where execution is performed
865 in the present frame. The innermost frame contains the current content
866 of the register PC. All other frames contain the content of the
867 register PC in the next frame.
869 The variable `type' indicates the frame's type: normal, SIGTRAMP
870 (associated with a signal handler), dummy (associated with a dummy
873 The variable return_pc contains the address where execution should be
874 resumed when the present frame has finished, the return address.
876 The variable leaf_function is 1 if the return address is in the register
877 SRP, and 0 if it is on the stack.
879 Prologue instructions C-code.
880 The prologue may consist of (-fno-omit-frame-pointer)
884 move.d sp,r8 move.d sp,r8
886 movem rY,[sp] movem rY,[sp]
887 move.S rZ,[r8-U] move.S rZ,[r8-U]
889 where 1 is a non-terminal function, and 2 is a leaf-function.
891 Note that this assumption is extremely brittle, and will break at the
892 slightest change in GCC's prologue.
894 If local variables are declared or register contents are saved on stack
895 the subq-instruction will be present with X as the number of bytes
896 needed for storage. The reshuffle with respect to r8 may be performed
897 with any size S (b, w, d) and any of the general registers Z={0..13}.
898 The offset U should be representable by a signed 8-bit value in all cases.
899 Thus, the prefix word is assumed to be immediate byte offset mode followed
900 by another word containing the instruction.
909 Prologue instructions C++-code.
910 Case 1) and 2) in the C-code may be followed by
916 move.S [r8+U],rZ ; P4
918 if any of the call parameters are stored. The host expects these
919 instructions to be executed in order to get the call parameters right. */
921 /* Examine the prologue of a function. The variable ip is the address of
922 the first instruction of the prologue. The variable limit is the address
923 of the first instruction after the prologue. The variable fi contains the
924 information in struct frame_info. The variable frameless_p controls whether
925 the entire prologue is examined (0) or just enough instructions to
926 determine that it is a prologue (1). */
929 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
930 struct cris_unwind_cache
*info
)
932 /* Present instruction. */
935 /* Next instruction, lookahead. */
936 unsigned short insn_next
;
939 /* Is there a push fp? */
942 /* Number of byte on stack used for local variables and movem. */
945 /* Highest register number in a movem. */
948 /* move.d r<source_register>,rS */
949 short source_register
;
954 /* This frame is with respect to a leaf until a push srp is found. */
957 info
->leaf_function
= 1;
960 /* Assume nothing on stack. */
964 /* If we were called without a next_frame, that means we were called
965 from cris_skip_prologue which already tried to find the end of the
966 prologue through the symbol information. 64 instructions past current
967 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
968 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
970 /* Find the prologue instructions. */
971 while (pc
> 0 && pc
< limit
)
973 insn
= read_memory_unsigned_integer (pc
, 2);
977 /* push <reg> 32 bit instruction */
978 insn_next
= read_memory_unsigned_integer (pc
, 2);
980 regno
= cris_get_operand2 (insn_next
);
983 info
->sp_offset
+= 4;
985 /* This check, meant to recognize srp, used to be regno ==
986 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
987 if (insn_next
== 0xBE7E)
991 info
->leaf_function
= 0;
994 else if (insn_next
== 0x8FEE)
999 info
->r8_offset
= info
->sp_offset
;
1003 else if (insn
== 0x866E)
1008 info
->uses_frame
= 1;
1012 else if (cris_get_operand2 (insn
) == SP_REGNUM
1013 && cris_get_mode (insn
) == 0x0000
1014 && cris_get_opcode (insn
) == 0x000A)
1019 info
->sp_offset
+= cris_get_quick_value (insn
);
1022 else if (cris_get_mode (insn
) == 0x0002
1023 && cris_get_opcode (insn
) == 0x000F
1024 && cris_get_size (insn
) == 0x0003
1025 && cris_get_operand1 (insn
) == SP_REGNUM
)
1027 /* movem r<regsave>,[sp] */
1028 regsave
= cris_get_operand2 (insn
);
1030 else if (cris_get_operand2 (insn
) == SP_REGNUM
1031 && ((insn
& 0x0F00) >> 8) == 0x0001
1032 && (cris_get_signed_offset (insn
) < 0))
1034 /* Immediate byte offset addressing prefix word with sp as base
1035 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1036 is between 64 and 128.
1037 movem r<regsave>,[sp=sp-<val>] */
1040 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1042 insn_next
= read_memory_unsigned_integer (pc
, 2);
1044 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1045 && cris_get_opcode (insn_next
) == 0x000F
1046 && cris_get_size (insn_next
) == 0x0003
1047 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
1049 regsave
= cris_get_operand2 (insn_next
);
1053 /* The prologue ended before the limit was reached. */
1058 else if (cris_get_mode (insn
) == 0x0001
1059 && cris_get_opcode (insn
) == 0x0009
1060 && cris_get_size (insn
) == 0x0002)
1062 /* move.d r<10..13>,r<0..15> */
1063 source_register
= cris_get_operand1 (insn
);
1065 /* FIXME? In the glibc solibs, the prologue might contain something
1066 like (this example taken from relocate_doit):
1068 sub.d 0xfffef426,$r0
1069 which isn't covered by the source_register check below. Question
1070 is whether to add a check for this combo, or make better use of
1071 the limit variable instead. */
1072 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1074 /* The prologue ended before the limit was reached. */
1079 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1080 /* The size is a fixed-size. */
1081 && ((insn
& 0x0F00) >> 8) == 0x0001
1082 /* A negative offset. */
1083 && (cris_get_signed_offset (insn
) < 0))
1085 /* move.S rZ,[r8-U] (?) */
1086 insn_next
= read_memory_unsigned_integer (pc
, 2);
1088 regno
= cris_get_operand2 (insn_next
);
1089 if ((regno
>= 0 && regno
< SP_REGNUM
)
1090 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1091 && cris_get_opcode (insn_next
) == 0x000F)
1093 /* move.S rZ,[r8-U] */
1098 /* The prologue ended before the limit was reached. */
1103 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1104 /* The size is a fixed-size. */
1105 && ((insn
& 0x0F00) >> 8) == 0x0001
1106 /* A positive offset. */
1107 && (cris_get_signed_offset (insn
) > 0))
1109 /* move.S [r8+U],rZ (?) */
1110 insn_next
= read_memory_unsigned_integer (pc
, 2);
1112 regno
= cris_get_operand2 (insn_next
);
1113 if ((regno
>= 0 && regno
< SP_REGNUM
)
1114 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1115 && cris_get_opcode (insn_next
) == 0x0009
1116 && cris_get_operand1 (insn_next
) == regno
)
1118 /* move.S [r8+U],rZ */
1123 /* The prologue ended before the limit was reached. */
1130 /* The prologue ended before the limit was reached. */
1136 /* We only want to know the end of the prologue when next_frame and info
1137 are NULL (called from cris_skip_prologue i.e.). */
1138 if (next_frame
== NULL
&& info
== NULL
)
1143 info
->size
= info
->sp_offset
;
1145 /* Compute the previous frame's stack pointer (which is also the
1146 frame's ID's stack address), and this frame's base pointer. */
1147 if (info
->uses_frame
)
1150 /* The SP was moved to the FP. This indicates that a new frame
1151 was created. Get THIS frame's FP value by unwinding it from
1153 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
1155 info
->base
= this_base
;
1156 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1158 /* The FP points at the last saved register. Adjust the FP back
1159 to before the first saved register giving the SP. */
1160 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1165 /* Assume that the FP is this frame's SP but with that pushed
1166 stack space added back. */
1167 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1168 info
->base
= this_base
;
1169 info
->prev_sp
= info
->base
+ info
->size
;
1172 /* Calculate the addresses for the saved registers on the stack. */
1173 /* FIXME: The address calculation should really be done on the fly while
1174 we're analyzing the prologue (we only hold one regsave value as it is
1176 val
= info
->sp_offset
;
1178 for (regno
= regsave
; regno
>= 0; regno
--)
1180 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1184 /* The previous frame's SP needed to be computed. Save the computed
1186 trad_frame_set_value (info
->saved_regs
, SP_REGNUM
, info
->prev_sp
);
1188 if (!info
->leaf_function
)
1190 /* SRP saved on the stack. But where? */
1191 if (info
->r8_offset
== 0)
1193 /* R8 not pushed yet. */
1194 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1198 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1199 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1203 /* The PC is found in SRP (the actual register or located on the stack). */
1204 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1209 /* Advance pc beyond any function entry prologue instructions at pc
1210 to reach some "real" code. */
1212 /* Given a PC value corresponding to the start of a function, return the PC
1213 of the first instruction after the function prologue. */
1216 cris_skip_prologue (CORE_ADDR pc
)
1218 CORE_ADDR func_addr
, func_end
;
1219 struct symtab_and_line sal
;
1220 CORE_ADDR pc_after_prologue
;
1222 /* If we have line debugging information, then the end of the prologue
1223 should the first assembly instruction of the first source line. */
1224 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1226 sal
= find_pc_line (func_addr
, 0);
1227 if (sal
.end
> 0 && sal
.end
< func_end
)
1231 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1232 return pc_after_prologue
;
1236 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1239 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1244 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1247 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &sp
);
1251 /* Use the program counter to determine the contents and size of a breakpoint
1252 instruction. It returns a pointer to a string of bytes that encode a
1253 breakpoint instruction, stores the length of the string to *lenptr, and
1254 adjusts pcptr (if necessary) to point to the actual memory location where
1255 the breakpoint should be inserted. */
1257 static const unsigned char *
1258 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1260 static unsigned char break_insn
[] = {0x38, 0xe9};
1266 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1270 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1272 int version
= cris_version ();
1274 switch (spec_reg
.applicable_version
)
1276 case cris_ver_version_all
:
1278 case cris_ver_warning
:
1279 /* Indeterminate/obsolete. */
1282 return (version
>= 0 && version
<= 3);
1284 return (version
>= 3);
1286 return (version
== 8 || version
== 9);
1288 return (version
>= 8);
1290 return (version
>= 10);
1292 /* Invalid cris version. */
1297 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1298 register, -1 for an invalid register. */
1301 cris_register_size (int regno
)
1306 if (regno
>= 0 && regno
< NUM_GENREGS
)
1308 /* General registers (R0 - R15) are 32 bits. */
1311 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1313 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1314 Adjust regno accordingly. */
1315 spec_regno
= regno
- NUM_GENREGS
;
1317 /* The entries in cris_spec_regs are stored in register number order,
1318 which means we can shortcut into the array when searching it. */
1319 for (i
= spec_regno
; cris_spec_regs
[i
].name
!= NULL
; i
++)
1321 if (cris_spec_regs
[i
].number
== spec_regno
1322 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1323 /* Go with the first applicable register. */
1324 return cris_spec_regs
[i
].reg_size
;
1326 /* Special register not applicable to this CRIS version. */
1331 /* Invalid register. */
1336 /* Nonzero if regno should not be fetched from the target. This is the case
1337 for unimplemented (size 0) and non-existant registers. */
1340 cris_cannot_fetch_register (int regno
)
1342 return ((regno
< 0 || regno
>= NUM_REGS
)
1343 || (cris_register_size (regno
) == 0));
1346 /* Nonzero if regno should not be written to the target, for various
1350 cris_cannot_store_register (int regno
)
1352 /* There are three kinds of registers we refuse to write to.
1353 1. Those that not implemented.
1354 2. Those that are read-only (depends on the processor mode).
1355 3. Those registers to which a write has no effect.
1358 if (regno
< 0 || regno
>= NUM_REGS
|| cris_register_size (regno
) == 0)
1359 /* Not implemented. */
1362 else if (regno
== VR_REGNUM
)
1366 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1367 /* Writing has no effect. */
1370 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1371 agent decide whether they are writable. */
1376 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1377 of data in register regno. */
1379 static struct type
*
1380 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1382 if (regno
== PC_REGNUM
)
1383 return builtin_type_void_func_ptr
;
1384 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1385 return builtin_type_void_data_ptr
;
1386 else if ((regno
>= 0 && regno
< SP_REGNUM
)
1387 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1388 /* Note: R8 taken care of previous clause. */
1389 return builtin_type_uint32
;
1390 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1391 return builtin_type_uint16
;
1392 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1393 return builtin_type_uint8
;
1395 /* Invalid (unimplemented) register. */
1396 return builtin_type_int0
;
1399 /* Stores a function return value of type type, where valbuf is the address
1400 of the value to be stored. */
1402 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1405 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1409 int len
= TYPE_LENGTH (type
);
1413 /* Put the return value in R10. */
1414 val
= extract_unsigned_integer (valbuf
, len
);
1415 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1419 /* Put the return value in R10 and R11. */
1420 val
= extract_unsigned_integer (valbuf
, 4);
1421 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1422 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1423 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1426 error ("cris_store_return_value: type length too large.");
1429 /* Return the name of register regno as a string. Return NULL for an invalid or
1430 unimplemented register. */
1433 cris_register_name (int regno
)
1435 static char *cris_genreg_names
[] =
1436 { "r0", "r1", "r2", "r3", \
1437 "r4", "r5", "r6", "r7", \
1438 "r8", "r9", "r10", "r11", \
1439 "r12", "r13", "sp", "pc" };
1444 if (regno
>= 0 && regno
< NUM_GENREGS
)
1446 /* General register. */
1447 return cris_genreg_names
[regno
];
1449 else if (regno
>= NUM_GENREGS
&& regno
< NUM_REGS
)
1451 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1452 Adjust regno accordingly. */
1453 spec_regno
= regno
- NUM_GENREGS
;
1455 /* The entries in cris_spec_regs are stored in register number order,
1456 which means we can shortcut into the array when searching it. */
1457 for (i
= spec_regno
; cris_spec_regs
[i
].name
!= NULL
; i
++)
1459 if (cris_spec_regs
[i
].number
== spec_regno
1460 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1461 /* Go with the first applicable register. */
1462 return cris_spec_regs
[i
].name
;
1464 /* Special register not applicable to this CRIS version. */
1469 /* Invalid register. */
1474 /* Convert DWARF register number REG to the appropriate register
1475 number used by GDB. */
1478 cris_dwarf2_reg_to_regnum (int reg
)
1480 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1481 numbering, MOF is 18).
1482 Adapted from gcc/config/cris/cris.h. */
1483 static int cris_dwarf_regmap
[] = {
1495 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1496 regnum
= cris_dwarf_regmap
[reg
];
1499 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
1504 /* DWARF-2 frame support. */
1507 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1508 struct dwarf2_frame_state_reg
*reg
)
1510 /* The return address column. */
1511 if (regnum
== PC_REGNUM
)
1512 reg
->how
= DWARF2_FRAME_REG_RA
;
1514 /* The call frame address. */
1515 else if (regnum
== SP_REGNUM
)
1516 reg
->how
= DWARF2_FRAME_REG_CFA
;
1519 /* Extract from an array regbuf containing the raw register state a function
1520 return value of type type, and copy that, in virtual format, into
1523 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1526 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1530 int len
= TYPE_LENGTH (type
);
1534 /* Get the return value from R10. */
1535 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1536 store_unsigned_integer (valbuf
, len
, val
);
1540 /* Get the return value from R10 and R11. */
1541 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1542 store_unsigned_integer (valbuf
, 4, val
);
1543 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1544 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1547 error ("cris_extract_return_value: type length too large");
1550 /* Handle the CRIS return value convention. */
1552 static enum return_value_convention
1553 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1554 struct regcache
*regcache
, void *readbuf
,
1555 const void *writebuf
)
1557 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1558 || TYPE_CODE (type
) == TYPE_CODE_UNION
1559 || TYPE_LENGTH (type
) > 8)
1560 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1561 goes on the stack. */
1562 return RETURN_VALUE_STRUCT_CONVENTION
;
1565 cris_extract_return_value (type
, regcache
, readbuf
);
1567 cris_store_return_value (type
, regcache
, writebuf
);
1569 return RETURN_VALUE_REGISTER_CONVENTION
;
1572 /* Returns 1 if the given type will be passed by pointer rather than
1575 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1579 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1581 return (TYPE_LENGTH (type
) > 8);
1584 /* Calculates a value that measures how good inst_args constraints an
1585 instruction. It stems from cris_constraint, found in cris-dis.c. */
1588 constraint (unsigned int insn
, const signed char *inst_args
,
1589 inst_env_type
*inst_env
)
1594 const char *s
= inst_args
;
1600 if ((insn
& 0x30) == 0x30)
1605 /* A prefix operand. */
1606 if (inst_env
->prefix_found
)
1612 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1613 valid "push" size. In case of special register, it may be != 4. */
1614 if (inst_env
->prefix_found
)
1620 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1628 tmp
= (insn
>> 0xC) & 0xF;
1630 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1632 /* Since we match four bits, we will give a value of
1633 4 - 1 = 3 in a match. If there is a corresponding
1634 exact match of a special register in another pattern, it
1635 will get a value of 4, which will be higher. This should
1636 be correct in that an exact pattern would match better that
1638 Note that there is a reason for not returning zero; the
1639 pattern for "clear" is partly matched in the bit-pattern
1640 (the two lower bits must be zero), while the bit-pattern
1641 for a move from a special register is matched in the
1642 register constraint.
1643 This also means we will will have a race condition if
1644 there is a partly match in three bits in the bit pattern. */
1645 if (tmp
== cris_spec_regs
[i
].number
)
1652 if (cris_spec_regs
[i
].name
== NULL
)
1659 /* Returns the number of bits set in the variable value. */
1662 number_of_bits (unsigned int value
)
1664 int number_of_bits
= 0;
1668 number_of_bits
+= 1;
1669 value
&= (value
- 1);
1671 return number_of_bits
;
1674 /* Finds the address that should contain the single step breakpoint(s).
1675 It stems from code in cris-dis.c. */
1678 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
1681 int max_level_of_match
= -1;
1682 int max_matched
= -1;
1685 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
1687 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
1688 && ((cris_opcodes
[i
].lose
& insn
) == 0))
1690 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
1691 if (level_of_match
>= 0)
1694 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
1695 if (level_of_match
> max_level_of_match
)
1698 max_level_of_match
= level_of_match
;
1699 if (level_of_match
== 16)
1701 /* All bits matched, cannot find better. */
1711 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1712 actually an internal error. */
1715 find_step_target (inst_env_type
*inst_env
)
1719 unsigned short insn
;
1721 /* Create a local register image and set the initial state. */
1722 for (i
= 0; i
< NUM_GENREGS
; i
++)
1724 inst_env
->reg
[i
] = (unsigned long) read_register (i
);
1726 offset
= NUM_GENREGS
;
1727 for (i
= 0; i
< NUM_SPECREGS
; i
++)
1729 inst_env
->preg
[i
] = (unsigned long) read_register (offset
+ i
);
1731 inst_env
->branch_found
= 0;
1732 inst_env
->slot_needed
= 0;
1733 inst_env
->delay_slot_pc_active
= 0;
1734 inst_env
->prefix_found
= 0;
1735 inst_env
->invalid
= 0;
1736 inst_env
->xflag_found
= 0;
1737 inst_env
->disable_interrupt
= 0;
1739 /* Look for a step target. */
1742 /* Read an instruction from the client. */
1743 insn
= read_memory_unsigned_integer (inst_env
->reg
[PC_REGNUM
], 2);
1745 /* If the instruction is not in a delay slot the new content of the
1746 PC is [PC] + 2. If the instruction is in a delay slot it is not
1747 that simple. Since a instruction in a delay slot cannot change
1748 the content of the PC, it does not matter what value PC will have.
1749 Just make sure it is a valid instruction. */
1750 if (!inst_env
->delay_slot_pc_active
)
1752 inst_env
->reg
[PC_REGNUM
] += 2;
1756 inst_env
->delay_slot_pc_active
= 0;
1757 inst_env
->reg
[PC_REGNUM
] = inst_env
->delay_slot_pc
;
1759 /* Analyse the present instruction. */
1760 i
= find_cris_op (insn
, inst_env
);
1763 inst_env
->invalid
= 1;
1767 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
1769 } while (!inst_env
->invalid
1770 && (inst_env
->prefix_found
|| inst_env
->xflag_found
1771 || inst_env
->slot_needed
));
1775 /* There is no hardware single-step support. The function find_step_target
1776 digs through the opcodes in order to find all possible targets.
1777 Either one ordinary target or two targets for branches may be found. */
1780 cris_software_single_step (enum target_signal ignore
, int insert_breakpoints
)
1782 inst_env_type inst_env
;
1784 if (insert_breakpoints
)
1786 /* Analyse the present instruction environment and insert
1788 int status
= find_step_target (&inst_env
);
1791 /* Could not find a target. FIXME: Should do something. */
1792 warning ("cris_software_single_step: unable to find step target");
1796 /* Insert at most two breakpoints. One for the next PC content
1797 and possibly another one for a branch, jump, etc. */
1798 next_pc
= (CORE_ADDR
) inst_env
.reg
[PC_REGNUM
];
1799 target_insert_breakpoint (next_pc
, break_mem
[0]);
1800 if (inst_env
.branch_found
1801 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
1803 branch_target_address
=
1804 (CORE_ADDR
) inst_env
.branch_break_address
;
1805 target_insert_breakpoint (branch_target_address
, break_mem
[1]);
1806 branch_break_inserted
= 1;
1812 /* Remove breakpoints. */
1813 target_remove_breakpoint (next_pc
, break_mem
[0]);
1814 if (branch_break_inserted
)
1816 target_remove_breakpoint (branch_target_address
, break_mem
[1]);
1817 branch_break_inserted
= 0;
1822 /* Calculates the prefix value for quick offset addressing mode. */
1825 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1827 /* It's invalid to be in a delay slot. You can't have a prefix to this
1828 instruction (not 100% sure). */
1829 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1831 inst_env
->invalid
= 1;
1835 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
1836 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
1838 /* A prefix doesn't change the xflag_found. But the rest of the flags
1840 inst_env
->slot_needed
= 0;
1841 inst_env
->prefix_found
= 1;
1844 /* Updates the autoincrement register. The size of the increment is derived
1845 from the size of the operation. The PC is always kept aligned on even
1849 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
1851 if (size
== INST_BYTE_SIZE
)
1853 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
1855 /* The PC must be word aligned, so increase the PC with one
1856 word even if the size is byte. */
1857 if (cris_get_operand1 (inst
) == REG_PC
)
1859 inst_env
->reg
[REG_PC
] += 1;
1862 else if (size
== INST_WORD_SIZE
)
1864 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
1866 else if (size
== INST_DWORD_SIZE
)
1868 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
1873 inst_env
->invalid
= 1;
1877 /* Just a forward declaration. */
1879 static unsigned long get_data_from_address (unsigned short *inst
,
1882 /* Calculates the prefix value for the general case of offset addressing
1886 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1891 /* It's invalid to be in a delay slot. */
1892 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1894 inst_env
->invalid
= 1;
1898 /* The calculation of prefix_value used to be after process_autoincrement,
1899 but that fails for an instruction such as jsr [$r0+12] which is encoded
1900 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
1901 mustn't be incremented until we have read it and what it points at. */
1902 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
1904 /* The offset is an indirection of the contents of the operand1 register. */
1905 inst_env
->prefix_value
+=
1906 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
1908 if (cris_get_mode (inst
) == AUTOINC_MODE
)
1910 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
1913 /* A prefix doesn't change the xflag_found. But the rest of the flags
1915 inst_env
->slot_needed
= 0;
1916 inst_env
->prefix_found
= 1;
1919 /* Calculates the prefix value for the index addressing mode. */
1922 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1924 /* It's invalid to be in a delay slot. I can't see that it's possible to
1925 have a prefix to this instruction. So I will treat this as invalid. */
1926 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1928 inst_env
->invalid
= 1;
1932 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
1934 /* The offset is the operand2 value shifted the size of the instruction
1936 inst_env
->prefix_value
+=
1937 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
1939 /* If the PC is operand1 (base) the address used is the address after
1940 the main instruction, i.e. address + 2 (the PC is already compensated
1941 for the prefix operation). */
1942 if (cris_get_operand1 (inst
) == REG_PC
)
1944 inst_env
->prefix_value
+= 2;
1947 /* A prefix doesn't change the xflag_found. But the rest of the flags
1949 inst_env
->slot_needed
= 0;
1950 inst_env
->xflag_found
= 0;
1951 inst_env
->prefix_found
= 1;
1954 /* Calculates the prefix value for the double indirect addressing mode. */
1957 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
1962 /* It's invalid to be in a delay slot. */
1963 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1965 inst_env
->invalid
= 1;
1969 /* The prefix value is one dereference of the contents of the operand1
1971 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
1972 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
1974 /* Check if the mode is autoincrement. */
1975 if (cris_get_mode (inst
) == AUTOINC_MODE
)
1977 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
1980 /* A prefix doesn't change the xflag_found. But the rest of the flags
1982 inst_env
->slot_needed
= 0;
1983 inst_env
->xflag_found
= 0;
1984 inst_env
->prefix_found
= 1;
1987 /* Finds the destination for a branch with 8-bits offset. */
1990 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
1995 /* If we have a prefix or are in a delay slot it's bad. */
1996 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
1998 inst_env
->invalid
= 1;
2002 /* We have a branch, find out where the branch will land. */
2003 offset
= cris_get_branch_short_offset (inst
);
2005 /* Check if the offset is signed. */
2006 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2011 /* The offset ends with the sign bit, set it to zero. The address
2012 should always be word aligned. */
2013 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2015 inst_env
->branch_found
= 1;
2016 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2018 inst_env
->slot_needed
= 1;
2019 inst_env
->prefix_found
= 0;
2020 inst_env
->xflag_found
= 0;
2021 inst_env
->disable_interrupt
= 1;
2024 /* Finds the destination for a branch with 16-bits offset. */
2027 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2031 /* If we have a prefix or is in a delay slot it's bad. */
2032 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2034 inst_env
->invalid
= 1;
2038 /* We have a branch, find out the offset for the branch. */
2039 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2041 /* The instruction is one word longer than normal, so add one word
2043 inst_env
->reg
[REG_PC
] += 2;
2045 inst_env
->branch_found
= 1;
2046 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2049 inst_env
->slot_needed
= 1;
2050 inst_env
->prefix_found
= 0;
2051 inst_env
->xflag_found
= 0;
2052 inst_env
->disable_interrupt
= 1;
2055 /* Handles the ABS instruction. */
2058 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2063 /* ABS can't have a prefix, so it's bad if it does. */
2064 if (inst_env
->prefix_found
)
2066 inst_env
->invalid
= 1;
2070 /* Check if the operation affects the PC. */
2071 if (cris_get_operand2 (inst
) == REG_PC
)
2074 /* It's invalid to change to the PC if we are in a delay slot. */
2075 if (inst_env
->slot_needed
)
2077 inst_env
->invalid
= 1;
2081 value
= (long) inst_env
->reg
[REG_PC
];
2083 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2084 if (value
!= SIGNED_DWORD_MASK
)
2087 inst_env
->reg
[REG_PC
] = (long) value
;
2091 inst_env
->slot_needed
= 0;
2092 inst_env
->prefix_found
= 0;
2093 inst_env
->xflag_found
= 0;
2094 inst_env
->disable_interrupt
= 0;
2097 /* Handles the ADDI instruction. */
2100 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2102 /* It's invalid to have the PC as base register. And ADDI can't have
2104 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2106 inst_env
->invalid
= 1;
2110 inst_env
->slot_needed
= 0;
2111 inst_env
->prefix_found
= 0;
2112 inst_env
->xflag_found
= 0;
2113 inst_env
->disable_interrupt
= 0;
2116 /* Handles the ASR instruction. */
2119 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2122 unsigned long value
;
2123 unsigned long signed_extend_mask
= 0;
2125 /* ASR can't have a prefix, so check that it doesn't. */
2126 if (inst_env
->prefix_found
)
2128 inst_env
->invalid
= 1;
2132 /* Check if the PC is the target register. */
2133 if (cris_get_operand2 (inst
) == REG_PC
)
2135 /* It's invalid to change the PC in a delay slot. */
2136 if (inst_env
->slot_needed
)
2138 inst_env
->invalid
= 1;
2141 /* Get the number of bits to shift. */
2142 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2143 value
= inst_env
->reg
[REG_PC
];
2145 /* Find out how many bits the operation should apply to. */
2146 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2148 if (value
& SIGNED_BYTE_MASK
)
2150 signed_extend_mask
= 0xFF;
2151 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2152 signed_extend_mask
= ~signed_extend_mask
;
2154 value
= value
>> shift_steps
;
2155 value
|= signed_extend_mask
;
2157 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2158 inst_env
->reg
[REG_PC
] |= value
;
2160 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2162 if (value
& SIGNED_WORD_MASK
)
2164 signed_extend_mask
= 0xFFFF;
2165 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2166 signed_extend_mask
= ~signed_extend_mask
;
2168 value
= value
>> shift_steps
;
2169 value
|= signed_extend_mask
;
2171 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2172 inst_env
->reg
[REG_PC
] |= value
;
2174 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2176 if (value
& SIGNED_DWORD_MASK
)
2178 signed_extend_mask
= 0xFFFFFFFF;
2179 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2180 signed_extend_mask
= ~signed_extend_mask
;
2182 value
= value
>> shift_steps
;
2183 value
|= signed_extend_mask
;
2184 inst_env
->reg
[REG_PC
] = value
;
2187 inst_env
->slot_needed
= 0;
2188 inst_env
->prefix_found
= 0;
2189 inst_env
->xflag_found
= 0;
2190 inst_env
->disable_interrupt
= 0;
2193 /* Handles the ASRQ instruction. */
2196 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2200 unsigned long value
;
2201 unsigned long signed_extend_mask
= 0;
2203 /* ASRQ can't have a prefix, so check that it doesn't. */
2204 if (inst_env
->prefix_found
)
2206 inst_env
->invalid
= 1;
2210 /* Check if the PC is the target register. */
2211 if (cris_get_operand2 (inst
) == REG_PC
)
2214 /* It's invalid to change the PC in a delay slot. */
2215 if (inst_env
->slot_needed
)
2217 inst_env
->invalid
= 1;
2220 /* The shift size is given as a 5 bit quick value, i.e. we don't
2221 want the the sign bit of the quick value. */
2222 shift_steps
= cris_get_asr_shift_steps (inst
);
2223 value
= inst_env
->reg
[REG_PC
];
2224 if (value
& SIGNED_DWORD_MASK
)
2226 signed_extend_mask
= 0xFFFFFFFF;
2227 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2228 signed_extend_mask
= ~signed_extend_mask
;
2230 value
= value
>> shift_steps
;
2231 value
|= signed_extend_mask
;
2232 inst_env
->reg
[REG_PC
] = value
;
2234 inst_env
->slot_needed
= 0;
2235 inst_env
->prefix_found
= 0;
2236 inst_env
->xflag_found
= 0;
2237 inst_env
->disable_interrupt
= 0;
2240 /* Handles the AX, EI and SETF instruction. */
2243 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2245 if (inst_env
->prefix_found
)
2247 inst_env
->invalid
= 1;
2250 /* Check if the instruction is setting the X flag. */
2251 if (cris_is_xflag_bit_on (inst
))
2253 inst_env
->xflag_found
= 1;
2257 inst_env
->xflag_found
= 0;
2259 inst_env
->slot_needed
= 0;
2260 inst_env
->prefix_found
= 0;
2261 inst_env
->disable_interrupt
= 1;
2264 /* Checks if the instruction is in assign mode. If so, it updates the assign
2265 register. Note that check_assign assumes that the caller has checked that
2266 there is a prefix to this instruction. The mode check depends on this. */
2269 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2271 /* Check if it's an assign addressing mode. */
2272 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2274 /* Assign the prefix value to operand 1. */
2275 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2279 /* Handles the 2-operand BOUND instruction. */
2282 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2284 /* It's invalid to have the PC as the index operand. */
2285 if (cris_get_operand2 (inst
) == REG_PC
)
2287 inst_env
->invalid
= 1;
2290 /* Check if we have a prefix. */
2291 if (inst_env
->prefix_found
)
2293 check_assign (inst
, inst_env
);
2295 /* Check if this is an autoincrement mode. */
2296 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2298 /* It's invalid to change the PC in a delay slot. */
2299 if (inst_env
->slot_needed
)
2301 inst_env
->invalid
= 1;
2304 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2306 inst_env
->slot_needed
= 0;
2307 inst_env
->prefix_found
= 0;
2308 inst_env
->xflag_found
= 0;
2309 inst_env
->disable_interrupt
= 0;
2312 /* Handles the 3-operand BOUND instruction. */
2315 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2317 /* It's an error if we haven't got a prefix. And it's also an error
2318 if the PC is the destination register. */
2319 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2321 inst_env
->invalid
= 1;
2324 inst_env
->slot_needed
= 0;
2325 inst_env
->prefix_found
= 0;
2326 inst_env
->xflag_found
= 0;
2327 inst_env
->disable_interrupt
= 0;
2330 /* Clears the status flags in inst_env. */
2333 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2335 /* It's an error if we have got a prefix. */
2336 if (inst_env
->prefix_found
)
2338 inst_env
->invalid
= 1;
2342 inst_env
->slot_needed
= 0;
2343 inst_env
->prefix_found
= 0;
2344 inst_env
->xflag_found
= 0;
2345 inst_env
->disable_interrupt
= 0;
2348 /* Clears the status flags in inst_env. */
2351 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2353 /* It's an error if we have got a prefix. */
2354 if (inst_env
->prefix_found
)
2356 inst_env
->invalid
= 1;
2360 inst_env
->slot_needed
= 0;
2361 inst_env
->prefix_found
= 0;
2362 inst_env
->xflag_found
= 0;
2363 inst_env
->disable_interrupt
= 1;
2366 /* Handles the CLEAR instruction if it's in register mode. */
2369 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2371 /* Check if the target is the PC. */
2372 if (cris_get_operand2 (inst
) == REG_PC
)
2374 /* The instruction will clear the instruction's size bits. */
2375 int clear_size
= cris_get_clear_size (inst
);
2376 if (clear_size
== INST_BYTE_SIZE
)
2378 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2380 if (clear_size
== INST_WORD_SIZE
)
2382 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2384 if (clear_size
== INST_DWORD_SIZE
)
2386 inst_env
->delay_slot_pc
= 0x0;
2388 /* The jump will be delayed with one delay slot. So we need a delay
2390 inst_env
->slot_needed
= 1;
2391 inst_env
->delay_slot_pc_active
= 1;
2395 /* The PC will not change => no delay slot. */
2396 inst_env
->slot_needed
= 0;
2398 inst_env
->prefix_found
= 0;
2399 inst_env
->xflag_found
= 0;
2400 inst_env
->disable_interrupt
= 0;
2403 /* Handles the TEST instruction if it's in register mode. */
2406 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2408 /* It's an error if we have got a prefix. */
2409 if (inst_env
->prefix_found
)
2411 inst_env
->invalid
= 1;
2414 inst_env
->slot_needed
= 0;
2415 inst_env
->prefix_found
= 0;
2416 inst_env
->xflag_found
= 0;
2417 inst_env
->disable_interrupt
= 0;
2421 /* Handles the CLEAR and TEST instruction if the instruction isn't
2422 in register mode. */
2425 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2427 /* Check if we are in a prefix mode. */
2428 if (inst_env
->prefix_found
)
2430 /* The only way the PC can change is if this instruction is in
2431 assign addressing mode. */
2432 check_assign (inst
, inst_env
);
2434 /* Indirect mode can't change the PC so just check if the mode is
2436 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2438 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2440 inst_env
->slot_needed
= 0;
2441 inst_env
->prefix_found
= 0;
2442 inst_env
->xflag_found
= 0;
2443 inst_env
->disable_interrupt
= 0;
2446 /* Checks that the PC isn't the destination register or the instructions has
2450 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2452 /* It's invalid to have the PC as the destination. The instruction can't
2454 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2456 inst_env
->invalid
= 1;
2460 inst_env
->slot_needed
= 0;
2461 inst_env
->prefix_found
= 0;
2462 inst_env
->xflag_found
= 0;
2463 inst_env
->disable_interrupt
= 0;
2466 /* Checks that the instruction doesn't have a prefix. */
2469 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2471 /* The instruction can't have a prefix. */
2472 if (inst_env
->prefix_found
)
2474 inst_env
->invalid
= 1;
2478 inst_env
->slot_needed
= 0;
2479 inst_env
->prefix_found
= 0;
2480 inst_env
->xflag_found
= 0;
2481 inst_env
->disable_interrupt
= 1;
2484 /* Checks that the PC isn't the destination register and that the instruction
2485 doesn't have a prefix. */
2488 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2490 /* It's invalid to have the PC as the destination. The instruction can't
2492 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2494 inst_env
->invalid
= 1;
2498 inst_env
->slot_needed
= 0;
2499 inst_env
->prefix_found
= 0;
2500 inst_env
->xflag_found
= 0;
2501 inst_env
->disable_interrupt
= 1;
2504 /* Handles the register mode JUMP instruction. */
2507 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2509 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2510 you can't have a prefix. */
2511 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2513 inst_env
->invalid
= 1;
2517 /* Just change the PC. */
2518 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2519 inst_env
->slot_needed
= 0;
2520 inst_env
->prefix_found
= 0;
2521 inst_env
->xflag_found
= 0;
2522 inst_env
->disable_interrupt
= 1;
2525 /* Handles the JUMP instruction for all modes except register. */
2528 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2530 unsigned long newpc
;
2533 /* It's invalid to do a JUMP in a delay slot. */
2534 if (inst_env
->slot_needed
)
2536 inst_env
->invalid
= 1;
2540 /* Check if we have a prefix. */
2541 if (inst_env
->prefix_found
)
2543 check_assign (inst
, inst_env
);
2545 /* Get the new value for the the PC. */
2547 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2552 /* Get the new value for the PC. */
2553 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2554 newpc
= read_memory_unsigned_integer (address
, 4);
2556 /* Check if we should increment a register. */
2557 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2559 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2562 inst_env
->reg
[REG_PC
] = newpc
;
2564 inst_env
->slot_needed
= 0;
2565 inst_env
->prefix_found
= 0;
2566 inst_env
->xflag_found
= 0;
2567 inst_env
->disable_interrupt
= 1;
2570 /* Handles moves to special registers (aka P-register) for all modes. */
2573 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2575 if (inst_env
->prefix_found
)
2577 /* The instruction has a prefix that means we are only interested if
2578 the instruction is in assign mode. */
2579 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2581 /* The prefix handles the problem if we are in a delay slot. */
2582 if (cris_get_operand1 (inst
) == REG_PC
)
2584 /* Just take care of the assign. */
2585 check_assign (inst
, inst_env
);
2589 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2591 /* The instruction doesn't have a prefix, the only case left that we
2592 are interested in is the autoincrement mode. */
2593 if (cris_get_operand1 (inst
) == REG_PC
)
2595 /* If the PC is to be incremented it's invalid to be in a
2597 if (inst_env
->slot_needed
)
2599 inst_env
->invalid
= 1;
2603 /* The increment depends on the size of the special register. */
2604 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2606 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2608 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2610 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2614 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2618 inst_env
->slot_needed
= 0;
2619 inst_env
->prefix_found
= 0;
2620 inst_env
->xflag_found
= 0;
2621 inst_env
->disable_interrupt
= 1;
2624 /* Handles moves from special registers (aka P-register) for all modes
2628 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2630 if (inst_env
->prefix_found
)
2632 /* The instruction has a prefix that means we are only interested if
2633 the instruction is in assign mode. */
2634 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2636 /* The prefix handles the problem if we are in a delay slot. */
2637 if (cris_get_operand1 (inst
) == REG_PC
)
2639 /* Just take care of the assign. */
2640 check_assign (inst
, inst_env
);
2644 /* The instruction doesn't have a prefix, the only case left that we
2645 are interested in is the autoincrement mode. */
2646 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2648 if (cris_get_operand1 (inst
) == REG_PC
)
2650 /* If the PC is to be incremented it's invalid to be in a
2652 if (inst_env
->slot_needed
)
2654 inst_env
->invalid
= 1;
2658 /* The increment depends on the size of the special register. */
2659 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2661 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2663 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2665 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2669 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2673 inst_env
->slot_needed
= 0;
2674 inst_env
->prefix_found
= 0;
2675 inst_env
->xflag_found
= 0;
2676 inst_env
->disable_interrupt
= 1;
2679 /* Handles moves from special registers (aka P-register) when the mode
2683 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2685 /* Register mode move from special register can't have a prefix. */
2686 if (inst_env
->prefix_found
)
2688 inst_env
->invalid
= 1;
2692 if (cris_get_operand1 (inst
) == REG_PC
)
2694 /* It's invalid to change the PC in a delay slot. */
2695 if (inst_env
->slot_needed
)
2697 inst_env
->invalid
= 1;
2700 /* The destination is the PC, the jump will have a delay slot. */
2701 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
2702 inst_env
->slot_needed
= 1;
2703 inst_env
->delay_slot_pc_active
= 1;
2707 /* If the destination isn't PC, there will be no jump. */
2708 inst_env
->slot_needed
= 0;
2710 inst_env
->prefix_found
= 0;
2711 inst_env
->xflag_found
= 0;
2712 inst_env
->disable_interrupt
= 1;
2715 /* Handles the MOVEM from memory to general register instruction. */
2718 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2720 if (inst_env
->prefix_found
)
2722 /* The prefix handles the problem if we are in a delay slot. Is the
2723 MOVEM instruction going to change the PC? */
2724 if (cris_get_operand2 (inst
) >= REG_PC
)
2726 inst_env
->reg
[REG_PC
] =
2727 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
2729 /* The assign value is the value after the increment. Normally, the
2730 assign value is the value before the increment. */
2731 if ((cris_get_operand1 (inst
) == REG_PC
)
2732 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
2734 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
2735 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2740 /* Is the MOVEM instruction going to change the PC? */
2741 if (cris_get_operand2 (inst
) == REG_PC
)
2743 /* It's invalid to change the PC in a delay slot. */
2744 if (inst_env
->slot_needed
)
2746 inst_env
->invalid
= 1;
2749 inst_env
->reg
[REG_PC
] =
2750 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
2753 /* The increment is not depending on the size, instead it's depending
2754 on the number of registers loaded from memory. */
2755 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
2757 /* It's invalid to change the PC in a delay slot. */
2758 if (inst_env
->slot_needed
)
2760 inst_env
->invalid
= 1;
2763 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2766 inst_env
->slot_needed
= 0;
2767 inst_env
->prefix_found
= 0;
2768 inst_env
->xflag_found
= 0;
2769 inst_env
->disable_interrupt
= 0;
2772 /* Handles the MOVEM to memory from general register instruction. */
2775 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
2777 if (inst_env
->prefix_found
)
2779 /* The assign value is the value after the increment. Normally, the
2780 assign value is the value before the increment. */
2781 if ((cris_get_operand1 (inst
) == REG_PC
) &&
2782 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
2784 /* The prefix handles the problem if we are in a delay slot. */
2785 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
2786 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2791 /* The increment is not depending on the size, instead it's depending
2792 on the number of registers loaded to memory. */
2793 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
2795 /* It's invalid to change the PC in a delay slot. */
2796 if (inst_env
->slot_needed
)
2798 inst_env
->invalid
= 1;
2801 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
2804 inst_env
->slot_needed
= 0;
2805 inst_env
->prefix_found
= 0;
2806 inst_env
->xflag_found
= 0;
2807 inst_env
->disable_interrupt
= 0;
2810 /* Handles the intructions that's not yet implemented, by setting
2811 inst_env->invalid to true. */
2814 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
2816 inst_env
->invalid
= 1;
2819 /* Handles the XOR instruction. */
2822 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
2824 /* XOR can't have a prefix. */
2825 if (inst_env
->prefix_found
)
2827 inst_env
->invalid
= 1;
2831 /* Check if the PC is the target. */
2832 if (cris_get_operand2 (inst
) == REG_PC
)
2834 /* It's invalid to change the PC in a delay slot. */
2835 if (inst_env
->slot_needed
)
2837 inst_env
->invalid
= 1;
2840 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
2842 inst_env
->slot_needed
= 0;
2843 inst_env
->prefix_found
= 0;
2844 inst_env
->xflag_found
= 0;
2845 inst_env
->disable_interrupt
= 0;
2848 /* Handles the MULS instruction. */
2851 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
2853 /* MULS/U can't have a prefix. */
2854 if (inst_env
->prefix_found
)
2856 inst_env
->invalid
= 1;
2860 /* Consider it invalid if the PC is the target. */
2861 if (cris_get_operand2 (inst
) == REG_PC
)
2863 inst_env
->invalid
= 1;
2866 inst_env
->slot_needed
= 0;
2867 inst_env
->prefix_found
= 0;
2868 inst_env
->xflag_found
= 0;
2869 inst_env
->disable_interrupt
= 0;
2872 /* Handles the MULU instruction. */
2875 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
2877 /* MULS/U can't have a prefix. */
2878 if (inst_env
->prefix_found
)
2880 inst_env
->invalid
= 1;
2884 /* Consider it invalid if the PC is the target. */
2885 if (cris_get_operand2 (inst
) == REG_PC
)
2887 inst_env
->invalid
= 1;
2890 inst_env
->slot_needed
= 0;
2891 inst_env
->prefix_found
= 0;
2892 inst_env
->xflag_found
= 0;
2893 inst_env
->disable_interrupt
= 0;
2896 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
2897 The MOVE instruction is the move from source to register. */
2900 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
2901 unsigned long source1
, unsigned long source2
)
2903 unsigned long pc_mask
;
2904 unsigned long operation_mask
;
2906 /* Find out how many bits the operation should apply to. */
2907 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2909 pc_mask
= 0xFFFFFF00;
2910 operation_mask
= 0xFF;
2912 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2914 pc_mask
= 0xFFFF0000;
2915 operation_mask
= 0xFFFF;
2917 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2920 operation_mask
= 0xFFFFFFFF;
2924 /* The size is out of range. */
2925 inst_env
->invalid
= 1;
2929 /* The instruction just works on uw_operation_mask bits. */
2930 source2
&= operation_mask
;
2931 source1
&= operation_mask
;
2933 /* Now calculate the result. The opcode's 3 first bits separates
2934 the different actions. */
2935 switch (cris_get_opcode (inst
) & 7)
2945 case 2: /* subtract */
2949 case 3: /* compare */
2961 inst_env
->invalid
= 1;
2967 /* Make sure that the result doesn't contain more than the instruction
2969 source2
&= operation_mask
;
2971 /* Calculate the new breakpoint address. */
2972 inst_env
->reg
[REG_PC
] &= pc_mask
;
2973 inst_env
->reg
[REG_PC
] |= source1
;
2977 /* Extends the value from either byte or word size to a dword. If the mode
2978 is zero extend then the value is extended with zero. If instead the mode
2979 is signed extend the sign bit of the value is taken into consideration. */
2981 static unsigned long
2982 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
2984 /* The size can be either byte or word, check which one it is.
2985 Don't check the highest bit, it's indicating if it's a zero
2987 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
2992 /* Check if the instruction is signed extend. If so, check if value has
2994 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
2996 value
|= SIGNED_WORD_EXTEND_MASK
;
3004 /* Check if the instruction is signed extend. If so, check if value has
3006 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3008 value
|= SIGNED_BYTE_EXTEND_MASK
;
3011 /* The size should now be dword. */
3012 cris_set_size_to_dword (inst
);
3016 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3017 instruction. The MOVE instruction is the move from source to register. */
3020 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3021 inst_env_type
*inst_env
)
3023 unsigned long operand1
;
3024 unsigned long operand2
;
3026 /* It's invalid to have a prefix to the instruction. This is a register
3027 mode instruction and can't have a prefix. */
3028 if (inst_env
->prefix_found
)
3030 inst_env
->invalid
= 1;
3033 /* Check if the instruction has PC as its target. */
3034 if (cris_get_operand2 (inst
) == REG_PC
)
3036 if (inst_env
->slot_needed
)
3038 inst_env
->invalid
= 1;
3041 /* The instruction has the PC as its target register. */
3042 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3043 operand2
= inst_env
->reg
[REG_PC
];
3045 /* Check if it's a extend, signed or zero instruction. */
3046 if (cris_get_opcode (inst
) < 4)
3048 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3050 /* Calculate the PC value after the instruction, i.e. where the
3051 breakpoint should be. The order of the udw_operands is vital. */
3052 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3054 inst_env
->slot_needed
= 0;
3055 inst_env
->prefix_found
= 0;
3056 inst_env
->xflag_found
= 0;
3057 inst_env
->disable_interrupt
= 0;
3060 /* Returns the data contained at address. The size of the data is derived from
3061 the size of the operation. If the instruction is a zero or signed
3062 extend instruction, the size field is changed in instruction. */
3064 static unsigned long
3065 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3067 int size
= cris_get_size (*inst
);
3068 unsigned long value
;
3070 /* If it's an extend instruction we don't want the signed extend bit,
3071 because it influences the size. */
3072 if (cris_get_opcode (*inst
) < 4)
3074 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3076 /* Is there a need for checking the size? Size should contain the number of
3079 value
= read_memory_unsigned_integer (address
, size
);
3081 /* Check if it's an extend, signed or zero instruction. */
3082 if (cris_get_opcode (*inst
) < 4)
3084 value
= do_sign_or_zero_extend (value
, inst
);
3089 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3090 instructions. The MOVE instruction is the move from source to register. */
3093 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3094 inst_env_type
*inst_env
)
3096 unsigned long operand2
;
3097 unsigned long operand3
;
3099 check_assign (inst
, inst_env
);
3100 if (cris_get_operand2 (inst
) == REG_PC
)
3102 operand2
= inst_env
->reg
[REG_PC
];
3104 /* Get the value of the third operand. */
3105 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3107 /* Calculate the PC value after the instruction, i.e. where the
3108 breakpoint should be. The order of the udw_operands is vital. */
3109 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3111 inst_env
->slot_needed
= 0;
3112 inst_env
->prefix_found
= 0;
3113 inst_env
->xflag_found
= 0;
3114 inst_env
->disable_interrupt
= 0;
3117 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3118 OR instructions. Note that for this to work as expected, the calling
3119 function must have made sure that there is a prefix to this instruction. */
3122 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3123 inst_env_type
*inst_env
)
3125 unsigned long operand2
;
3126 unsigned long operand3
;
3128 if (cris_get_operand1 (inst
) == REG_PC
)
3130 /* The PC will be changed by the instruction. */
3131 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3133 /* Get the value of the third operand. */
3134 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3136 /* Calculate the PC value after the instruction, i.e. where the
3137 breakpoint should be. */
3138 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3140 inst_env
->slot_needed
= 0;
3141 inst_env
->prefix_found
= 0;
3142 inst_env
->xflag_found
= 0;
3143 inst_env
->disable_interrupt
= 0;
3146 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3147 instructions. The MOVE instruction is the move from source to register. */
3150 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3151 inst_env_type
*inst_env
)
3153 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3155 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3156 SUB, AND or OR something weird is going on (if everything works these
3157 instructions should end up in the three operand version). */
3158 inst_env
->invalid
= 1;
3163 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3165 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3167 inst_env
->slot_needed
= 0;
3168 inst_env
->prefix_found
= 0;
3169 inst_env
->xflag_found
= 0;
3170 inst_env
->disable_interrupt
= 0;
3173 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3174 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3175 source to register. */
3178 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3179 inst_env_type
*inst_env
)
3181 unsigned long operand1
;
3182 unsigned long operand2
;
3183 unsigned long operand3
;
3186 /* The instruction is either an indirect or autoincrement addressing mode.
3187 Check if the destination register is the PC. */
3188 if (cris_get_operand2 (inst
) == REG_PC
)
3190 /* Must be done here, get_data_from_address may change the size
3192 size
= cris_get_size (inst
);
3193 operand2
= inst_env
->reg
[REG_PC
];
3195 /* Get the value of the third operand, i.e. the indirect operand. */
3196 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3197 operand3
= get_data_from_address (&inst
, operand1
);
3199 /* Calculate the PC value after the instruction, i.e. where the
3200 breakpoint should be. The order of the udw_operands is vital. */
3201 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3203 /* If this is an autoincrement addressing mode, check if the increment
3205 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3207 /* Get the size field. */
3208 size
= cris_get_size (inst
);
3210 /* If it's an extend instruction we don't want the signed extend bit,
3211 because it influences the size. */
3212 if (cris_get_opcode (inst
) < 4)
3214 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3216 process_autoincrement (size
, inst
, inst_env
);
3218 inst_env
->slot_needed
= 0;
3219 inst_env
->prefix_found
= 0;
3220 inst_env
->xflag_found
= 0;
3221 inst_env
->disable_interrupt
= 0;
3224 /* Handles the two-operand addressing mode, all modes except register, for
3225 the ADD, SUB CMP, AND and OR instruction. */
3228 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3229 inst_env_type
*inst_env
)
3231 if (inst_env
->prefix_found
)
3233 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3235 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3237 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3239 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3243 /* The mode is invalid for a prefixed base instruction. */
3244 inst_env
->invalid
= 1;
3250 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3254 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3257 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3259 unsigned long operand1
;
3260 unsigned long operand2
;
3262 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3263 instruction and can't have a prefix. */
3264 if (inst_env
->prefix_found
)
3266 inst_env
->invalid
= 1;
3270 /* Check if the instruction has PC as its target. */
3271 if (cris_get_operand2 (inst
) == REG_PC
)
3273 if (inst_env
->slot_needed
)
3275 inst_env
->invalid
= 1;
3278 operand1
= cris_get_quick_value (inst
);
3279 operand2
= inst_env
->reg
[REG_PC
];
3281 /* The size should now be dword. */
3282 cris_set_size_to_dword (&inst
);
3284 /* Calculate the PC value after the instruction, i.e. where the
3285 breakpoint should be. */
3286 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3288 inst_env
->slot_needed
= 0;
3289 inst_env
->prefix_found
= 0;
3290 inst_env
->xflag_found
= 0;
3291 inst_env
->disable_interrupt
= 0;
3294 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3297 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3299 unsigned long operand1
;
3300 unsigned long operand2
;
3302 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3303 instruction and can't have a prefix. */
3304 if (inst_env
->prefix_found
)
3306 inst_env
->invalid
= 1;
3309 /* Check if the instruction has PC as its target. */
3310 if (cris_get_operand2 (inst
) == REG_PC
)
3312 if (inst_env
->slot_needed
)
3314 inst_env
->invalid
= 1;
3317 /* The instruction has the PC as its target register. */
3318 operand1
= cris_get_quick_value (inst
);
3319 operand2
= inst_env
->reg
[REG_PC
];
3321 /* The quick value is signed, so check if we must do a signed extend. */
3322 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3325 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3327 /* The size should now be dword. */
3328 cris_set_size_to_dword (&inst
);
3330 /* Calculate the PC value after the instruction, i.e. where the
3331 breakpoint should be. */
3332 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3334 inst_env
->slot_needed
= 0;
3335 inst_env
->prefix_found
= 0;
3336 inst_env
->xflag_found
= 0;
3337 inst_env
->disable_interrupt
= 0;
3340 /* Translate op_type to a function and call it. */
3343 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3344 inst_env_type
*inst_env
)
3348 case cris_not_implemented_op
:
3349 not_implemented_op (inst
, inst_env
);
3353 abs_op (inst
, inst_env
);
3357 addi_op (inst
, inst_env
);
3361 asr_op (inst
, inst_env
);
3365 asrq_op (inst
, inst_env
);
3368 case cris_ax_ei_setf_op
:
3369 ax_ei_setf_op (inst
, inst_env
);
3372 case cris_bdap_prefix
:
3373 bdap_prefix (inst
, inst_env
);
3376 case cris_biap_prefix
:
3377 biap_prefix (inst
, inst_env
);
3381 break_op (inst
, inst_env
);
3384 case cris_btst_nop_op
:
3385 btst_nop_op (inst
, inst_env
);
3388 case cris_clearf_di_op
:
3389 clearf_di_op (inst
, inst_env
);
3392 case cris_dip_prefix
:
3393 dip_prefix (inst
, inst_env
);
3396 case cris_dstep_logshift_mstep_neg_not_op
:
3397 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3400 case cris_eight_bit_offset_branch_op
:
3401 eight_bit_offset_branch_op (inst
, inst_env
);
3404 case cris_move_mem_to_reg_movem_op
:
3405 move_mem_to_reg_movem_op (inst
, inst_env
);
3408 case cris_move_reg_to_mem_movem_op
:
3409 move_reg_to_mem_movem_op (inst
, inst_env
);
3412 case cris_move_to_preg_op
:
3413 move_to_preg_op (inst
, inst_env
);
3417 muls_op (inst
, inst_env
);
3421 mulu_op (inst
, inst_env
);
3424 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3425 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3428 case cris_none_reg_mode_clear_test_op
:
3429 none_reg_mode_clear_test_op (inst
, inst_env
);
3432 case cris_none_reg_mode_jump_op
:
3433 none_reg_mode_jump_op (inst
, inst_env
);
3436 case cris_none_reg_mode_move_from_preg_op
:
3437 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3440 case cris_quick_mode_add_sub_op
:
3441 quick_mode_add_sub_op (inst
, inst_env
);
3444 case cris_quick_mode_and_cmp_move_or_op
:
3445 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3448 case cris_quick_mode_bdap_prefix
:
3449 quick_mode_bdap_prefix (inst
, inst_env
);
3452 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3453 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3456 case cris_reg_mode_clear_op
:
3457 reg_mode_clear_op (inst
, inst_env
);
3460 case cris_reg_mode_jump_op
:
3461 reg_mode_jump_op (inst
, inst_env
);
3464 case cris_reg_mode_move_from_preg_op
:
3465 reg_mode_move_from_preg_op (inst
, inst_env
);
3468 case cris_reg_mode_test_op
:
3469 reg_mode_test_op (inst
, inst_env
);
3473 scc_op (inst
, inst_env
);
3476 case cris_sixteen_bit_offset_branch_op
:
3477 sixteen_bit_offset_branch_op (inst
, inst_env
);
3480 case cris_three_operand_add_sub_cmp_and_or_op
:
3481 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3484 case cris_three_operand_bound_op
:
3485 three_operand_bound_op (inst
, inst_env
);
3488 case cris_two_operand_bound_op
:
3489 two_operand_bound_op (inst
, inst_env
);
3493 xor_op (inst
, inst_env
);
3498 /* This wrapper is to avoid cris_get_assembler being called before
3499 exec_bfd has been set. */
3502 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3504 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3505 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3506 disassembler, even when there is no BFD. Does something like
3507 "gdb; target remote; disassmeble *0x123" work? */
3508 gdb_assert (exec_bfd
!= NULL
);
3509 print_insn
= cris_get_disassembler (exec_bfd
);
3510 gdb_assert (print_insn
!= NULL
);
3511 return print_insn (addr
, info
);
3514 /* Copied from <asm/elf.h>. */
3515 typedef unsigned long elf_greg_t
;
3517 /* Same as user_regs_struct struct in <asm/user.h>. */
3518 typedef elf_greg_t elf_gregset_t
[35];
3520 /* Unpack an elf_gregset_t into GDB's register cache. */
3523 supply_gregset (elf_gregset_t
*gregsetp
)
3526 elf_greg_t
*regp
= *gregsetp
;
3527 static char zerobuf
[4] = {0};
3529 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3530 knows about the actual size of each register so that's no problem. */
3531 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3533 regcache_raw_supply (current_regcache
, i
, (char *)®p
[i
]);
3537 /* Use a local version of this function to get the correct types for
3538 regsets, until multi-arch core support is ready. */
3541 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
3542 int which
, CORE_ADDR reg_addr
)
3544 elf_gregset_t gregset
;
3549 if (core_reg_size
!= sizeof (gregset
))
3551 warning ("wrong size gregset struct in core file");
3555 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3556 supply_gregset (&gregset
);
3560 /* We've covered all the kinds of registers we know about here,
3561 so this must be something we wouldn't know what to do with
3562 anyway. Just ignore it. */
3567 static struct core_fns cris_elf_core_fns
=
3569 bfd_target_elf_flavour
, /* core_flavour */
3570 default_check_format
, /* check_format */
3571 default_core_sniffer
, /* core_sniffer */
3572 fetch_core_registers
, /* core_read_registers */
3576 /* Fetch (and possibly build) an appropriate link_map_offsets
3577 structure for native GNU/Linux CRIS targets using the struct
3578 offsets defined in link.h (but without actual reference to that
3581 This makes it possible to access GNU/Linux CRIS shared libraries
3582 from a GDB that was not built on an GNU/Linux CRIS host (for cross
3585 See gdb/solib-svr4.h for an explanation of these fields. */
3587 static struct link_map_offsets
*
3588 cris_linux_svr4_fetch_link_map_offsets (void)
3590 static struct link_map_offsets lmo
;
3591 static struct link_map_offsets
*lmp
= NULL
;
3597 lmo
.r_debug_size
= 8; /* The actual size is 20 bytes, but
3598 this is all we need. */
3599 lmo
.r_map_offset
= 4;
3602 lmo
.link_map_size
= 20;
3604 lmo
.l_addr_offset
= 0;
3605 lmo
.l_addr_size
= 4;
3607 lmo
.l_name_offset
= 4;
3608 lmo
.l_name_size
= 4;
3610 lmo
.l_next_offset
= 12;
3611 lmo
.l_next_size
= 4;
3613 lmo
.l_prev_offset
= 16;
3614 lmo
.l_prev_size
= 4;
3620 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3623 _initialize_cris_tdep (void)
3625 static struct cmd_list_element
*cris_set_cmdlist
;
3626 static struct cmd_list_element
*cris_show_cmdlist
;
3628 struct cmd_list_element
*c
;
3630 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3632 /* CRIS-specific user-commands. */
3633 add_setshow_uinteger_cmd ("cris-version", class_support
,
3634 &usr_cmd_cris_version
,
3635 "Set the current CRIS version.",
3636 "Show the current CRIS version.",
3637 "Set if autodetection fails.",
3638 "Current CRIS version is %s.",
3639 set_cris_version
, NULL
,
3640 &setlist
, &showlist
);
3642 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3643 &usr_cmd_cris_dwarf2_cfi
,
3644 "Set the usage of Dwarf-2 CFI for CRIS.",
3645 "Show the usage of Dwarf-2 CFI for CRIS.",
3646 "Set to \"off\" if using gcc-cris < R59.",
3647 "Usage of Dwarf-2 CFI for CRIS is %d.",
3648 set_cris_dwarf2_cfi
, NULL
,
3649 &setlist
, &showlist
);
3651 deprecated_add_core_fns (&cris_elf_core_fns
);
3654 /* Prints out all target specific values. */
3657 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3659 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3662 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3663 tdep
->cris_version
);
3664 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3665 tdep
->cris_dwarf2_cfi
);
3670 set_cris_version (char *ignore_args
, int from_tty
,
3671 struct cmd_list_element
*c
)
3673 struct gdbarch_info info
;
3675 usr_cmd_cris_version_valid
= 1;
3677 /* Update the current architecture, if needed. */
3678 gdbarch_info_init (&info
);
3679 if (!gdbarch_update_p (info
))
3680 internal_error (__FILE__
, __LINE__
,
3681 "cris_gdbarch_update: failed to update architecture.");
3685 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
3686 struct cmd_list_element
*c
)
3688 struct gdbarch_info info
;
3690 /* Update the current architecture, if needed. */
3691 gdbarch_info_init (&info
);
3692 if (!gdbarch_update_p (info
))
3693 internal_error (__FILE__
, __LINE__
,
3694 "cris_gdbarch_update: failed to update architecture.");
3697 static struct gdbarch
*
3698 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3700 struct gdbarch
*gdbarch
;
3701 struct gdbarch_tdep
*tdep
;
3704 if (usr_cmd_cris_version_valid
)
3706 /* Trust the user's CRIS version setting. */
3707 cris_version
= usr_cmd_cris_version
;
3711 /* Assume it's CRIS version 10. */
3715 /* Make the current settings visible to the user. */
3716 usr_cmd_cris_version
= cris_version
;
3718 /* Find a candidate among the list of pre-declared architectures. Both
3719 CRIS version and ABI must match. */
3720 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3722 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3724 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
3725 == usr_cmd_cris_version
)
3726 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
3727 == usr_cmd_cris_dwarf2_cfi
))
3728 return arches
->gdbarch
;
3731 /* No matching architecture was found. Create a new one. */
3732 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3733 gdbarch
= gdbarch_alloc (&info
, tdep
);
3735 tdep
->cris_version
= usr_cmd_cris_version
;
3736 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
3738 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
3739 switch (info
.byte_order
)
3741 case BFD_ENDIAN_LITTLE
:
3745 case BFD_ENDIAN_BIG
:
3746 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: big endian byte order in info");
3750 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unknown byte order in info");
3753 set_gdbarch_return_value (gdbarch
, cris_return_value
);
3754 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
3755 cris_reg_struct_has_addr
);
3756 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
3758 /* There are 32 registers (some of which may not be implemented). */
3759 set_gdbarch_num_regs (gdbarch
, 32);
3760 set_gdbarch_sp_regnum (gdbarch
, 14);
3761 set_gdbarch_pc_regnum (gdbarch
, 15);
3762 set_gdbarch_register_name (gdbarch
, cris_register_name
);
3764 set_gdbarch_double_bit (gdbarch
, 64);
3765 /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
3766 which means we have to set this explicitly. */
3767 set_gdbarch_long_double_bit (gdbarch
, 64);
3768 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
3769 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
3771 /* The total amount of space needed to store (in an array called registers)
3772 GDB's copy of the machine's register state. Note: We can not use
3773 cris_register_size at this point, since it relies on current_gdbarch
3775 switch (tdep
->cris_version
)
3783 /* Old versions; not supported. */
3784 internal_error (__FILE__
, __LINE__
,
3785 "cris_gdbarch_init: unsupported CRIS version");
3790 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
3791 P7 (32 bits), and P15 (32 bits) have been implemented. */
3795 internal_error (__FILE__
, __LINE__
, "cris_gdbarch_init: unknown CRIS version");
3798 set_gdbarch_register_type (gdbarch
, cris_register_type
);
3800 /* Dummy frame functions. */
3801 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
3802 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
3803 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
3805 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
3806 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
3808 /* The stack grows downward. */
3809 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3811 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
3813 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
3814 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
3815 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
3817 if (tdep
->cris_dwarf2_cfi
== 1)
3819 /* Hook in the Dwarf-2 frame sniffer. */
3820 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
3821 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
3822 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
3825 frame_unwind_append_sniffer (gdbarch
, cris_sigtramp_frame_sniffer
);
3827 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
3828 frame_base_set_default (gdbarch
, &cris_frame_base
);
3830 /* Use target_specific function to define link map offsets. */
3831 set_solib_svr4_fetch_link_map_offsets
3832 (gdbarch
, cris_linux_svr4_fetch_link_map_offsets
);
3834 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3835 disassembler, even when there is no BFD. Does something like
3836 "gdb; target remote; disassmeble *0x123" work? */
3837 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);