1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
31 #include "dwarf2-frame.h"
39 #include "opcode/cris.h"
40 #include "arch-utils.h"
42 #include "gdb_assert.h"
44 /* To get entry_point_address. */
47 #include "solib.h" /* Support for shared libraries. */
48 #include "solib-svr4.h"
49 #include "gdb_string.h"
54 /* There are no floating point registers. Used in gdbserver low-linux.c. */
57 /* There are 16 general registers. */
60 /* There are 16 special registers. */
63 /* CRISv32 has a pseudo PC register, not noted here. */
65 /* CRISv32 has 16 support registers. */
69 /* Register numbers of various important registers.
70 CRIS_FP_REGNUM Contains address of executing stack frame.
71 STR_REGNUM Contains the address of structure return values.
72 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
73 ARG1_REGNUM Contains the first parameter to a function.
74 ARG2_REGNUM Contains the second parameter to a function.
75 ARG3_REGNUM Contains the third parameter to a function.
76 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
77 gdbarch_sp_regnum Contains address of top of stack.
78 gdbarch_pc_regnum Contains address of next instruction.
79 SRP_REGNUM Subroutine return pointer register.
80 BRP_REGNUM Breakpoint return pointer register. */
84 /* Enums with respect to the general registers, valid for all
85 CRIS versions. The frame pointer is always in R8. */
87 /* ABI related registers. */
95 /* Registers which happen to be common. */
100 /* CRISv10 et. al. specific registers. */
112 /* CRISv32 specific registers. */
125 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
127 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
147 extern const struct cris_spec_reg cris_spec_regs
[];
149 /* CRIS version, set via the user command 'set cris-version'. Affects
150 register names and sizes. */
151 static int usr_cmd_cris_version
;
153 /* Indicates whether to trust the above variable. */
154 static int usr_cmd_cris_version_valid
= 0;
156 static const char cris_mode_normal
[] = "normal";
157 static const char cris_mode_guru
[] = "guru";
158 static const char *cris_modes
[] = {
164 /* CRIS mode, set via the user command 'set cris-mode'. Affects
165 type of break instruction among other things. */
166 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
168 /* Whether to make use of Dwarf-2 CFI (default on). */
169 static int usr_cmd_cris_dwarf2_cfi
= 1;
171 /* CRIS architecture specific information. */
175 const char *cris_mode
;
179 /* Functions for accessing target dependent data. */
184 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
190 return (gdbarch_tdep (current_gdbarch
)->cris_mode
);
193 /* Sigtramp identification code copied from i386-linux-tdep.c. */
195 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
196 #define SIGTRAMP_OFFSET0 0
197 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
198 #define SIGTRAMP_OFFSET1 4
200 static const unsigned short sigtramp_code
[] =
202 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
203 SIGTRAMP_INSN1
/* break 13 */
206 #define SIGTRAMP_LEN (sizeof sigtramp_code)
208 /* Note: same length as normal sigtramp code. */
210 static const unsigned short rt_sigtramp_code
[] =
212 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
213 SIGTRAMP_INSN1
/* break 13 */
216 /* If PC is in a sigtramp routine, return the address of the start of
217 the routine. Otherwise, return 0. */
220 cris_sigtramp_start (struct frame_info
*next_frame
)
222 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
223 gdb_byte buf
[SIGTRAMP_LEN
];
225 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
228 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
230 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
233 pc
-= SIGTRAMP_OFFSET1
;
234 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
238 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
244 /* If PC is in a RT sigtramp routine, return the address of the start of
245 the routine. Otherwise, return 0. */
248 cris_rt_sigtramp_start (struct frame_info
*next_frame
)
250 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
251 gdb_byte buf
[SIGTRAMP_LEN
];
253 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
256 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
258 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
261 pc
-= SIGTRAMP_OFFSET1
;
262 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
266 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
272 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
273 routine, return the address of the associated sigcontext structure. */
276 cris_sigcontext_addr (struct frame_info
*next_frame
)
282 frame_unwind_register (next_frame
, gdbarch_sp_regnum (current_gdbarch
), buf
);
283 sp
= extract_unsigned_integer (buf
, 4);
285 /* Look for normal sigtramp frame first. */
286 pc
= cris_sigtramp_start (next_frame
);
289 /* struct signal_frame (arch/cris/kernel/signal.c) contains
290 struct sigcontext as its first member, meaning the SP points to
295 pc
= cris_rt_sigtramp_start (next_frame
);
298 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
299 a struct ucontext, which in turn contains a struct sigcontext.
301 4 + 4 + 128 to struct ucontext, then
302 4 + 4 + 12 to struct sigcontext. */
306 error (_("Couldn't recognize signal trampoline."));
310 struct cris_unwind_cache
312 /* The previous frame's inner most stack address. Used as this
313 frame ID's stack_addr. */
315 /* The frame's base, optionally used by the high-level debug info. */
318 /* How far the SP and r8 (FP) have been offset from the start of
319 the stack frame (as defined by the previous frame's stack
325 /* From old frame_extra_info struct. */
329 /* Table indicating the location of each and every register. */
330 struct trad_frame_saved_reg
*saved_regs
;
333 static struct cris_unwind_cache
*
334 cris_sigtramp_frame_unwind_cache (struct frame_info
*next_frame
,
337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
338 struct cris_unwind_cache
*info
;
346 return (*this_cache
);
348 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
349 (*this_cache
) = info
;
350 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
352 /* Zero all fields. */
358 info
->uses_frame
= 0;
360 info
->leaf_function
= 0;
362 frame_unwind_register (next_frame
, gdbarch_sp_regnum (current_gdbarch
), buf
);
363 info
->base
= extract_unsigned_integer (buf
, 4);
365 addr
= cris_sigcontext_addr (next_frame
);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep
->cris_version
== 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i
= 0; i
<= 13; i
++)
379 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
381 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
382 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
383 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
388 info
->saved_regs
[gdbarch_pc_regnum (current_gdbarch
)]
389 = info
->saved_regs
[IRP_REGNUM
];
390 info
->saved_regs
[gdbarch_sp_regnum (current_gdbarch
)].addr
396 /* R0 to R13 are stored in order at offset (1 * 4) in
398 for (i
= 0; i
<= 13; i
++)
399 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
401 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
402 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
403 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
404 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
405 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
406 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
407 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
408 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
409 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
411 /* FIXME: If ERP is in a delay slot at this point then the PC will
412 be wrong at this point. This problem manifests itself in the
413 sigaltstack.exp test case, which occasionally generates FAILs when
414 the signal is received while in a delay slot.
416 This could be solved by a couple of read_memory_unsigned_integer and a
417 trad_frame_set_value. */
418 info
->saved_regs
[gdbarch_pc_regnum (current_gdbarch
)]
419 = info
->saved_regs
[ERP_REGNUM
];
421 info
->saved_regs
[gdbarch_sp_regnum (current_gdbarch
)].addr
429 cris_sigtramp_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
430 struct frame_id
*this_id
)
432 struct cris_unwind_cache
*cache
=
433 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
434 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
437 /* Forward declaration. */
439 static void cris_frame_prev_register (struct frame_info
*next_frame
,
440 void **this_prologue_cache
,
441 int regnum
, int *optimizedp
,
442 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
443 int *realnump
, gdb_byte
*bufferp
);
445 cris_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
447 int regnum
, int *optimizedp
,
448 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
449 int *realnump
, gdb_byte
*valuep
)
451 /* Make sure we've initialized the cache. */
452 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
453 cris_frame_prev_register (next_frame
, this_cache
, regnum
,
454 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
457 static const struct frame_unwind cris_sigtramp_frame_unwind
=
460 cris_sigtramp_frame_this_id
,
461 cris_sigtramp_frame_prev_register
464 static const struct frame_unwind
*
465 cris_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
467 if (cris_sigtramp_start (next_frame
)
468 || cris_rt_sigtramp_start (next_frame
))
469 return &cris_sigtramp_frame_unwind
;
475 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
476 struct frame_info
*this_frame
)
478 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
483 if (cris_mode () == cris_mode_guru
)
485 frame_unwind_register (this_frame
, NRP_REGNUM
, buf
);
489 frame_unwind_register (this_frame
, ERP_REGNUM
, buf
);
492 erp
= extract_unsigned_integer (buf
, 4);
496 /* In delay slot - check if there's a breakpoint at the preceding
498 if (breakpoint_here_p (erp
& ~0x1))
504 /* Hardware watchpoint support. */
506 /* We support 6 hardware data watchpoints, but cannot trigger on execute
507 (any combination of read/write is fine). */
510 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
514 /* No bookkeeping is done here; it is handled by the remote debug agent. */
516 if (tdep
->cris_version
!= 32)
519 /* CRISv32: Six data watchpoints, one for instructions. */
520 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
521 || type
== bp_hardware_watchpoint
) && count
<= 6)
522 || (type
== bp_hardware_breakpoint
&& count
<= 1));
525 /* The CRISv32 hardware data watchpoints work by specifying ranges,
526 which have no alignment or length restrictions. */
529 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
534 /* If the inferior has some watchpoint that triggered, return the
535 address associated with that watchpoint. Otherwise, return
539 cris_stopped_data_address (void)
542 eda
= get_frame_register_unsigned (get_current_frame (), EDA_REGNUM
);
546 /* The instruction environment needed to find single-step breakpoints. */
549 struct instruction_environment
551 unsigned long reg
[NUM_GENREGS
];
552 unsigned long preg
[NUM_SPECREGS
];
553 unsigned long branch_break_address
;
554 unsigned long delay_slot_pc
;
555 unsigned long prefix_value
;
560 int delay_slot_pc_active
;
562 int disable_interrupt
;
565 /* Machine-dependencies in CRIS for opcodes. */
567 /* Instruction sizes. */
568 enum cris_instruction_sizes
575 /* Addressing modes. */
576 enum cris_addressing_modes
583 /* Prefix addressing modes. */
584 enum cris_prefix_addressing_modes
586 PREFIX_INDEX_MODE
= 2,
587 PREFIX_ASSIGN_MODE
= 3,
589 /* Handle immediate byte offset addressing mode prefix format. */
590 PREFIX_OFFSET_MODE
= 2
593 /* Masks for opcodes. */
594 enum cris_opcode_masks
596 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
597 SIGNED_EXTEND_BIT_MASK
= 0x2,
598 SIGNED_BYTE_MASK
= 0x80,
599 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
600 SIGNED_WORD_MASK
= 0x8000,
601 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
602 SIGNED_DWORD_MASK
= 0x80000000,
603 SIGNED_QUICK_VALUE_MASK
= 0x20,
604 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
607 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
615 cris_get_operand2 (unsigned short insn
)
617 return ((insn
& 0xF000) >> 12);
621 cris_get_mode (unsigned short insn
)
623 return ((insn
& 0x0C00) >> 10);
627 cris_get_opcode (unsigned short insn
)
629 return ((insn
& 0x03C0) >> 6);
633 cris_get_size (unsigned short insn
)
635 return ((insn
& 0x0030) >> 4);
639 cris_get_operand1 (unsigned short insn
)
641 return (insn
& 0x000F);
644 /* Additional functions in order to handle opcodes. */
647 cris_get_quick_value (unsigned short insn
)
649 return (insn
& 0x003F);
653 cris_get_bdap_quick_offset (unsigned short insn
)
655 return (insn
& 0x00FF);
659 cris_get_branch_short_offset (unsigned short insn
)
661 return (insn
& 0x00FF);
665 cris_get_asr_shift_steps (unsigned long value
)
667 return (value
& 0x3F);
671 cris_get_clear_size (unsigned short insn
)
673 return ((insn
) & 0xC000);
677 cris_is_signed_extend_bit_on (unsigned short insn
)
679 return (((insn
) & 0x20) == 0x20);
683 cris_is_xflag_bit_on (unsigned short insn
)
685 return (((insn
) & 0x1000) == 0x1000);
689 cris_set_size_to_dword (unsigned short *insn
)
696 cris_get_signed_offset (unsigned short insn
)
698 return ((signed char) (insn
& 0x00FF));
701 /* Calls an op function given the op-type, working on the insn and the
703 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
705 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
706 struct gdbarch_list
*);
708 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
710 static void set_cris_version (char *ignore_args
, int from_tty
,
711 struct cmd_list_element
*c
);
713 static void set_cris_mode (char *ignore_args
, int from_tty
,
714 struct cmd_list_element
*c
);
716 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
717 struct cmd_list_element
*c
);
719 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
720 struct frame_info
*next_frame
,
721 struct cris_unwind_cache
*info
);
723 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
724 struct frame_info
*next_frame
,
725 struct cris_unwind_cache
*info
);
727 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
728 struct frame_info
*next_frame
);
730 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
731 struct frame_info
*next_frame
);
733 /* When arguments must be pushed onto the stack, they go on in reverse
734 order. The below implements a FILO (stack) to do this.
735 Copied from d10v-tdep.c. */
740 struct stack_item
*prev
;
744 static struct stack_item
*
745 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
747 struct stack_item
*si
;
748 si
= xmalloc (sizeof (struct stack_item
));
749 si
->data
= xmalloc (len
);
752 memcpy (si
->data
, contents
, len
);
756 static struct stack_item
*
757 pop_stack_item (struct stack_item
*si
)
759 struct stack_item
*dead
= si
;
766 /* Put here the code to store, into fi->saved_regs, the addresses of
767 the saved registers of frame described by FRAME_INFO. This
768 includes special registers such as pc and fp saved in special ways
769 in the stack frame. sp is even more special: the address we return
770 for it IS the sp for the next frame. */
772 struct cris_unwind_cache
*
773 cris_frame_unwind_cache (struct frame_info
*next_frame
,
774 void **this_prologue_cache
)
777 struct cris_unwind_cache
*info
;
780 if ((*this_prologue_cache
))
781 return (*this_prologue_cache
);
783 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
784 (*this_prologue_cache
) = info
;
785 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
787 /* Zero all fields. */
793 info
->uses_frame
= 0;
795 info
->leaf_function
= 0;
797 /* Prologue analysis does the rest... */
798 if (cris_version () == 32)
799 crisv32_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
802 cris_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
808 /* Given a GDB frame, determine the address of the calling function's
809 frame. This will be used to create a new GDB frame struct. */
812 cris_frame_this_id (struct frame_info
*next_frame
,
813 void **this_prologue_cache
,
814 struct frame_id
*this_id
)
816 struct cris_unwind_cache
*info
817 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
822 /* The FUNC is easy. */
823 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
825 /* Hopefully the prologue analysis either correctly determined the
826 frame's base (which is the SP from the previous frame), or set
827 that base to "NULL". */
828 base
= info
->prev_sp
;
832 id
= frame_id_build (base
, func
);
838 cris_frame_prev_register (struct frame_info
*next_frame
,
839 void **this_prologue_cache
,
840 int regnum
, int *optimizedp
,
841 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
842 int *realnump
, gdb_byte
*bufferp
)
844 struct cris_unwind_cache
*info
845 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
846 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
847 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
850 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
851 dummy frame. The frame ID's base needs to match the TOS value
852 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
855 static struct frame_id
856 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
858 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
859 frame_pc_unwind (next_frame
));
863 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
865 /* Align to the size of an instruction (so that they can safely be
866 pushed onto the stack). */
871 cris_push_dummy_code (struct gdbarch
*gdbarch
,
872 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
873 struct value
**args
, int nargs
,
874 struct type
*value_type
,
875 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
876 struct regcache
*regcache
)
878 /* Allocate space sufficient for a breakpoint. */
880 /* Store the address of that breakpoint */
882 /* CRIS always starts the call at the callee's entry point. */
888 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
889 struct regcache
*regcache
, CORE_ADDR bp_addr
,
890 int nargs
, struct value
**args
, CORE_ADDR sp
,
891 int struct_return
, CORE_ADDR struct_addr
)
900 /* The function's arguments and memory allocated by gdb for the arguments to
901 point at reside in separate areas on the stack.
902 Both frame pointers grow toward higher addresses. */
906 struct stack_item
*si
= NULL
;
908 /* Push the return address. */
909 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
911 /* Are we returning a value using a structure return or a normal value
912 return? struct_addr is the address of the reserved space for the return
913 structure to be written on the stack. */
916 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
919 /* Now load as many as possible of the first arguments into registers,
920 and push the rest onto the stack. */
921 argreg
= ARG1_REGNUM
;
924 for (argnum
= 0; argnum
< nargs
; argnum
++)
931 len
= TYPE_LENGTH (value_type (args
[argnum
]));
932 val
= (char *) value_contents (args
[argnum
]);
934 /* How may registers worth of storage do we need for this argument? */
935 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
937 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
939 /* Data passed by value. Fits in available register(s). */
940 for (i
= 0; i
< reg_demand
; i
++)
942 regcache_cooked_write_unsigned (regcache
, argreg
,
943 *(unsigned long *) val
);
948 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
950 /* Data passed by value. Does not fit in available register(s).
951 Use the register(s) first, then the stack. */
952 for (i
= 0; i
< reg_demand
; i
++)
954 if (argreg
<= ARG4_REGNUM
)
956 regcache_cooked_write_unsigned (regcache
, argreg
,
957 *(unsigned long *) val
);
963 /* Push item for later so that pushed arguments
964 come in the right order. */
965 si
= push_stack_item (si
, val
, 4);
970 else if (len
> (2 * 4))
973 internal_error (__FILE__
, __LINE__
, _("We don't do this"));
977 /* Data passed by value. No available registers. Put it on
979 si
= push_stack_item (si
, val
, len
);
985 /* fp_arg must be word-aligned (i.e., don't += len) to match
986 the function prologue. */
987 sp
= (sp
- si
->len
) & ~3;
988 write_memory (sp
, si
->data
, si
->len
);
989 si
= pop_stack_item (si
);
992 /* Finally, update the SP register. */
993 regcache_cooked_write_unsigned (regcache
,
994 gdbarch_sp_regnum (current_gdbarch
), sp
);
999 static const struct frame_unwind cris_frame_unwind
=
1003 cris_frame_prev_register
1006 const struct frame_unwind
*
1007 cris_frame_sniffer (struct frame_info
*next_frame
)
1009 return &cris_frame_unwind
;
1013 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1015 struct cris_unwind_cache
*info
1016 = cris_frame_unwind_cache (next_frame
, this_cache
);
1020 static const struct frame_base cris_frame_base
=
1023 cris_frame_base_address
,
1024 cris_frame_base_address
,
1025 cris_frame_base_address
1028 /* Frames information. The definition of the struct frame_info is
1032 enum frame_type type;
1036 If the compilation option -fno-omit-frame-pointer is present the
1037 variable frame will be set to the content of R8 which is the frame
1040 The variable pc contains the address where execution is performed
1041 in the present frame. The innermost frame contains the current content
1042 of the register PC. All other frames contain the content of the
1043 register PC in the next frame.
1045 The variable `type' indicates the frame's type: normal, SIGTRAMP
1046 (associated with a signal handler), dummy (associated with a dummy
1049 The variable return_pc contains the address where execution should be
1050 resumed when the present frame has finished, the return address.
1052 The variable leaf_function is 1 if the return address is in the register
1053 SRP, and 0 if it is on the stack.
1055 Prologue instructions C-code.
1056 The prologue may consist of (-fno-omit-frame-pointer)
1060 move.d sp,r8 move.d sp,r8
1062 movem rY,[sp] movem rY,[sp]
1063 move.S rZ,[r8-U] move.S rZ,[r8-U]
1065 where 1 is a non-terminal function, and 2 is a leaf-function.
1067 Note that this assumption is extremely brittle, and will break at the
1068 slightest change in GCC's prologue.
1070 If local variables are declared or register contents are saved on stack
1071 the subq-instruction will be present with X as the number of bytes
1072 needed for storage. The reshuffle with respect to r8 may be performed
1073 with any size S (b, w, d) and any of the general registers Z={0..13}.
1074 The offset U should be representable by a signed 8-bit value in all cases.
1075 Thus, the prefix word is assumed to be immediate byte offset mode followed
1076 by another word containing the instruction.
1085 Prologue instructions C++-code.
1086 Case 1) and 2) in the C-code may be followed by
1088 move.d r10,rS ; this
1092 move.S [r8+U],rZ ; P4
1094 if any of the call parameters are stored. The host expects these
1095 instructions to be executed in order to get the call parameters right. */
1097 /* Examine the prologue of a function. The variable ip is the address of
1098 the first instruction of the prologue. The variable limit is the address
1099 of the first instruction after the prologue. The variable fi contains the
1100 information in struct frame_info. The variable frameless_p controls whether
1101 the entire prologue is examined (0) or just enough instructions to
1102 determine that it is a prologue (1). */
1105 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1106 struct cris_unwind_cache
*info
)
1108 /* Present instruction. */
1109 unsigned short insn
;
1111 /* Next instruction, lookahead. */
1112 unsigned short insn_next
;
1115 /* Is there a push fp? */
1118 /* Number of byte on stack used for local variables and movem. */
1121 /* Highest register number in a movem. */
1124 /* move.d r<source_register>,rS */
1125 short source_register
;
1130 /* This frame is with respect to a leaf until a push srp is found. */
1133 info
->leaf_function
= 1;
1136 /* Assume nothing on stack. */
1140 /* If we were called without a next_frame, that means we were called
1141 from cris_skip_prologue which already tried to find the end of the
1142 prologue through the symbol information. 64 instructions past current
1143 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1144 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
1146 /* Find the prologue instructions. */
1147 while (pc
> 0 && pc
< limit
)
1149 insn
= read_memory_unsigned_integer (pc
, 2);
1153 /* push <reg> 32 bit instruction */
1154 insn_next
= read_memory_unsigned_integer (pc
, 2);
1156 regno
= cris_get_operand2 (insn_next
);
1159 info
->sp_offset
+= 4;
1161 /* This check, meant to recognize srp, used to be regno ==
1162 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1163 if (insn_next
== 0xBE7E)
1167 info
->leaf_function
= 0;
1170 else if (insn_next
== 0x8FEE)
1175 info
->r8_offset
= info
->sp_offset
;
1179 else if (insn
== 0x866E)
1184 info
->uses_frame
= 1;
1188 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (current_gdbarch
)
1189 && cris_get_mode (insn
) == 0x0000
1190 && cris_get_opcode (insn
) == 0x000A)
1195 info
->sp_offset
+= cris_get_quick_value (insn
);
1198 else if (cris_get_mode (insn
) == 0x0002
1199 && cris_get_opcode (insn
) == 0x000F
1200 && cris_get_size (insn
) == 0x0003
1201 && cris_get_operand1 (insn
) == gdbarch_sp_regnum
1204 /* movem r<regsave>,[sp] */
1205 regsave
= cris_get_operand2 (insn
);
1207 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (current_gdbarch
)
1208 && ((insn
& 0x0F00) >> 8) == 0x0001
1209 && (cris_get_signed_offset (insn
) < 0))
1211 /* Immediate byte offset addressing prefix word with sp as base
1212 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1213 is between 64 and 128.
1214 movem r<regsave>,[sp=sp-<val>] */
1217 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1219 insn_next
= read_memory_unsigned_integer (pc
, 2);
1221 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1222 && cris_get_opcode (insn_next
) == 0x000F
1223 && cris_get_size (insn_next
) == 0x0003
1224 && cris_get_operand1 (insn_next
) == gdbarch_sp_regnum
1227 regsave
= cris_get_operand2 (insn_next
);
1231 /* The prologue ended before the limit was reached. */
1236 else if (cris_get_mode (insn
) == 0x0001
1237 && cris_get_opcode (insn
) == 0x0009
1238 && cris_get_size (insn
) == 0x0002)
1240 /* move.d r<10..13>,r<0..15> */
1241 source_register
= cris_get_operand1 (insn
);
1243 /* FIXME? In the glibc solibs, the prologue might contain something
1244 like (this example taken from relocate_doit):
1246 sub.d 0xfffef426,$r0
1247 which isn't covered by the source_register check below. Question
1248 is whether to add a check for this combo, or make better use of
1249 the limit variable instead. */
1250 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1252 /* The prologue ended before the limit was reached. */
1257 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1258 /* The size is a fixed-size. */
1259 && ((insn
& 0x0F00) >> 8) == 0x0001
1260 /* A negative offset. */
1261 && (cris_get_signed_offset (insn
) < 0))
1263 /* move.S rZ,[r8-U] (?) */
1264 insn_next
= read_memory_unsigned_integer (pc
, 2);
1266 regno
= cris_get_operand2 (insn_next
);
1267 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (current_gdbarch
))
1268 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1269 && cris_get_opcode (insn_next
) == 0x000F)
1271 /* move.S rZ,[r8-U] */
1276 /* The prologue ended before the limit was reached. */
1281 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1282 /* The size is a fixed-size. */
1283 && ((insn
& 0x0F00) >> 8) == 0x0001
1284 /* A positive offset. */
1285 && (cris_get_signed_offset (insn
) > 0))
1287 /* move.S [r8+U],rZ (?) */
1288 insn_next
= read_memory_unsigned_integer (pc
, 2);
1290 regno
= cris_get_operand2 (insn_next
);
1291 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (current_gdbarch
))
1292 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1293 && cris_get_opcode (insn_next
) == 0x0009
1294 && cris_get_operand1 (insn_next
) == regno
)
1296 /* move.S [r8+U],rZ */
1301 /* The prologue ended before the limit was reached. */
1308 /* The prologue ended before the limit was reached. */
1314 /* We only want to know the end of the prologue when next_frame and info
1315 are NULL (called from cris_skip_prologue i.e.). */
1316 if (next_frame
== NULL
&& info
== NULL
)
1321 info
->size
= info
->sp_offset
;
1323 /* Compute the previous frame's stack pointer (which is also the
1324 frame's ID's stack address), and this frame's base pointer. */
1325 if (info
->uses_frame
)
1328 /* The SP was moved to the FP. This indicates that a new frame
1329 was created. Get THIS frame's FP value by unwinding it from
1331 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
1333 info
->base
= this_base
;
1334 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1336 /* The FP points at the last saved register. Adjust the FP back
1337 to before the first saved register giving the SP. */
1338 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1343 /* Assume that the FP is this frame's SP but with that pushed
1344 stack space added back. */
1345 frame_unwind_unsigned_register (next_frame
,
1346 gdbarch_sp_regnum (current_gdbarch
),
1348 info
->base
= this_base
;
1349 info
->prev_sp
= info
->base
+ info
->size
;
1352 /* Calculate the addresses for the saved registers on the stack. */
1353 /* FIXME: The address calculation should really be done on the fly while
1354 we're analyzing the prologue (we only hold one regsave value as it is
1356 val
= info
->sp_offset
;
1358 for (regno
= regsave
; regno
>= 0; regno
--)
1360 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1364 /* The previous frame's SP needed to be computed. Save the computed
1366 trad_frame_set_value (info
->saved_regs
,
1367 gdbarch_sp_regnum (current_gdbarch
), info
->prev_sp
);
1369 if (!info
->leaf_function
)
1371 /* SRP saved on the stack. But where? */
1372 if (info
->r8_offset
== 0)
1374 /* R8 not pushed yet. */
1375 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1379 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1380 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1384 /* The PC is found in SRP (the actual register or located on the stack). */
1385 info
->saved_regs
[gdbarch_pc_regnum (current_gdbarch
)]
1386 = info
->saved_regs
[SRP_REGNUM
];
1392 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1393 struct cris_unwind_cache
*info
)
1397 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1398 meant to be a full-fledged prologue scanner. It is only needed for
1399 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1401 * PLT stubs (library calls)
1403 * signal trampolines
1405 For those cases, it is assumed that there is no actual prologue; that
1406 the stack pointer is not adjusted, and (as a consequence) the return
1407 address is not pushed onto the stack. */
1409 /* We only want to know the end of the prologue when next_frame and info
1410 are NULL (called from cris_skip_prologue i.e.). */
1411 if (next_frame
== NULL
&& info
== NULL
)
1416 /* The SP is assumed to be unaltered. */
1417 frame_unwind_unsigned_register (next_frame
,
1418 gdbarch_sp_regnum (current_gdbarch
),
1420 info
->base
= this_base
;
1421 info
->prev_sp
= this_base
;
1423 /* The PC is assumed to be found in SRP. */
1424 info
->saved_regs
[gdbarch_pc_regnum (current_gdbarch
)]
1425 = info
->saved_regs
[SRP_REGNUM
];
1430 /* Advance pc beyond any function entry prologue instructions at pc
1431 to reach some "real" code. */
1433 /* Given a PC value corresponding to the start of a function, return the PC
1434 of the first instruction after the function prologue. */
1437 cris_skip_prologue (CORE_ADDR pc
)
1439 CORE_ADDR func_addr
, func_end
;
1440 struct symtab_and_line sal
;
1441 CORE_ADDR pc_after_prologue
;
1443 /* If we have line debugging information, then the end of the prologue
1444 should the first assembly instruction of the first source line. */
1445 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1447 sal
= find_pc_line (func_addr
, 0);
1448 if (sal
.end
> 0 && sal
.end
< func_end
)
1452 if (cris_version () == 32)
1453 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1455 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1457 return pc_after_prologue
;
1461 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1464 frame_unwind_unsigned_register (next_frame
,
1465 gdbarch_pc_regnum (current_gdbarch
), &pc
);
1470 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1473 frame_unwind_unsigned_register (next_frame
,
1474 gdbarch_sp_regnum (current_gdbarch
), &sp
);
1478 /* Use the program counter to determine the contents and size of a breakpoint
1479 instruction. It returns a pointer to a string of bytes that encode a
1480 breakpoint instruction, stores the length of the string to *lenptr, and
1481 adjusts pcptr (if necessary) to point to the actual memory location where
1482 the breakpoint should be inserted. */
1484 static const unsigned char *
1485 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1487 static unsigned char break8_insn
[] = {0x38, 0xe9};
1488 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1491 if (cris_mode () == cris_mode_guru
)
1492 return break15_insn
;
1497 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1501 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1503 int version
= cris_version ();
1505 switch (spec_reg
.applicable_version
)
1507 case cris_ver_version_all
:
1509 case cris_ver_warning
:
1510 /* Indeterminate/obsolete. */
1513 return (version
>= 0 && version
<= 3);
1515 return (version
>= 3);
1517 return (version
== 8 || version
== 9);
1519 return (version
>= 8);
1520 case cris_ver_v0_10
:
1521 return (version
>= 0 && version
<= 10);
1522 case cris_ver_v3_10
:
1523 return (version
>= 3 && version
<= 10);
1524 case cris_ver_v8_10
:
1525 return (version
>= 8 && version
<= 10);
1527 return (version
== 10);
1529 return (version
>= 10);
1531 return (version
>= 32);
1533 /* Invalid cris version. */
1538 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1539 register, -1 for an invalid register. */
1542 cris_register_size (int regno
)
1544 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1548 if (regno
>= 0 && regno
< NUM_GENREGS
)
1550 /* General registers (R0 - R15) are 32 bits. */
1553 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1555 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1556 Adjust regno accordingly. */
1557 spec_regno
= regno
- NUM_GENREGS
;
1559 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1561 if (cris_spec_regs
[i
].number
== spec_regno
1562 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1563 /* Go with the first applicable register. */
1564 return cris_spec_regs
[i
].reg_size
;
1566 /* Special register not applicable to this CRIS version. */
1569 else if (regno
>= gdbarch_pc_regnum (current_gdbarch
)
1570 && regno
< gdbarch_num_regs (current_gdbarch
))
1572 /* This will apply to CRISv32 only where there are additional registers
1573 after the special registers (pseudo PC and support registers). */
1581 /* Nonzero if regno should not be fetched from the target. This is the case
1582 for unimplemented (size 0) and non-existant registers. */
1585 cris_cannot_fetch_register (int regno
)
1587 return ((regno
< 0 || regno
>= gdbarch_num_regs (current_gdbarch
))
1588 || (cris_register_size (regno
) == 0));
1591 /* Nonzero if regno should not be written to the target, for various
1595 cris_cannot_store_register (int regno
)
1597 /* There are three kinds of registers we refuse to write to.
1598 1. Those that not implemented.
1599 2. Those that are read-only (depends on the processor mode).
1600 3. Those registers to which a write has no effect.
1604 || regno
>= gdbarch_num_regs (current_gdbarch
)
1605 || cris_register_size (regno
) == 0)
1606 /* Not implemented. */
1609 else if (regno
== VR_REGNUM
)
1613 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1614 /* Writing has no effect. */
1617 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1618 agent decide whether they are writable. */
1623 /* Nonzero if regno should not be fetched from the target. This is the case
1624 for unimplemented (size 0) and non-existant registers. */
1627 crisv32_cannot_fetch_register (int regno
)
1629 return ((regno
< 0 || regno
>= gdbarch_num_regs (current_gdbarch
))
1630 || (cris_register_size (regno
) == 0));
1633 /* Nonzero if regno should not be written to the target, for various
1637 crisv32_cannot_store_register (int regno
)
1639 /* There are three kinds of registers we refuse to write to.
1640 1. Those that not implemented.
1641 2. Those that are read-only (depends on the processor mode).
1642 3. Those registers to which a write has no effect.
1646 || regno
>= gdbarch_num_regs (current_gdbarch
)
1647 || cris_register_size (regno
) == 0)
1648 /* Not implemented. */
1651 else if (regno
== VR_REGNUM
)
1655 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1656 /* Writing has no effect. */
1659 /* Many special registers are read-only in user mode. Let the debug
1660 agent decide whether they are writable. */
1665 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1666 of data in register regno. */
1668 static struct type
*
1669 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1671 if (regno
== gdbarch_pc_regnum (current_gdbarch
))
1672 return builtin_type_void_func_ptr
;
1673 else if (regno
== gdbarch_sp_regnum (current_gdbarch
)
1674 || regno
== CRIS_FP_REGNUM
)
1675 return builtin_type_void_data_ptr
;
1676 else if ((regno
>= 0 && regno
< gdbarch_sp_regnum (current_gdbarch
))
1677 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1678 /* Note: R8 taken care of previous clause. */
1679 return builtin_type_uint32
;
1680 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1681 return builtin_type_uint16
;
1682 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1683 return builtin_type_uint8
;
1685 /* Invalid (unimplemented) register. */
1686 return builtin_type_int0
;
1689 static struct type
*
1690 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1692 if (regno
== gdbarch_pc_regnum (current_gdbarch
))
1693 return builtin_type_void_func_ptr
;
1694 else if (regno
== gdbarch_sp_regnum (current_gdbarch
)
1695 || regno
== CRIS_FP_REGNUM
)
1696 return builtin_type_void_data_ptr
;
1697 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1698 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1699 || (regno
== PID_REGNUM
)
1700 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1701 /* Note: R8 and SP taken care of by previous clause. */
1702 return builtin_type_uint32
;
1703 else if (regno
== WZ_REGNUM
)
1704 return builtin_type_uint16
;
1705 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1706 return builtin_type_uint8
;
1709 /* Invalid (unimplemented) register. Should not happen as there are
1710 no unimplemented CRISv32 registers. */
1711 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1712 return builtin_type_int0
;
1716 /* Stores a function return value of type type, where valbuf is the address
1717 of the value to be stored. */
1719 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1722 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1726 int len
= TYPE_LENGTH (type
);
1730 /* Put the return value in R10. */
1731 val
= extract_unsigned_integer (valbuf
, len
);
1732 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1736 /* Put the return value in R10 and R11. */
1737 val
= extract_unsigned_integer (valbuf
, 4);
1738 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1739 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1740 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1743 error (_("cris_store_return_value: type length too large."));
1746 /* Return the name of register regno as a string. Return NULL for an invalid or
1747 unimplemented register. */
1750 cris_special_register_name (int regno
)
1755 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1756 Adjust regno accordingly. */
1757 spec_regno
= regno
- NUM_GENREGS
;
1759 /* Assume nothing about the layout of the cris_spec_regs struct
1761 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1763 if (cris_spec_regs
[i
].number
== spec_regno
1764 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1765 /* Go with the first applicable register. */
1766 return cris_spec_regs
[i
].name
;
1768 /* Special register not applicable to this CRIS version. */
1773 cris_register_name (int regno
)
1775 static char *cris_genreg_names
[] =
1776 { "r0", "r1", "r2", "r3", \
1777 "r4", "r5", "r6", "r7", \
1778 "r8", "r9", "r10", "r11", \
1779 "r12", "r13", "sp", "pc" };
1781 if (regno
>= 0 && regno
< NUM_GENREGS
)
1783 /* General register. */
1784 return cris_genreg_names
[regno
];
1786 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (current_gdbarch
))
1788 return cris_special_register_name (regno
);
1792 /* Invalid register. */
1798 crisv32_register_name (int regno
)
1800 static char *crisv32_genreg_names
[] =
1801 { "r0", "r1", "r2", "r3", \
1802 "r4", "r5", "r6", "r7", \
1803 "r8", "r9", "r10", "r11", \
1804 "r12", "r13", "sp", "acr"
1807 static char *crisv32_sreg_names
[] =
1808 { "s0", "s1", "s2", "s3", \
1809 "s4", "s5", "s6", "s7", \
1810 "s8", "s9", "s10", "s11", \
1811 "s12", "s13", "s14", "s15"
1814 if (regno
>= 0 && regno
< NUM_GENREGS
)
1816 /* General register. */
1817 return crisv32_genreg_names
[regno
];
1819 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1821 return cris_special_register_name (regno
);
1823 else if (regno
== gdbarch_pc_regnum (current_gdbarch
))
1827 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1829 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1833 /* Invalid register. */
1838 /* Convert DWARF register number REG to the appropriate register
1839 number used by GDB. */
1842 cris_dwarf2_reg_to_regnum (int reg
)
1844 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1845 numbering, MOF is 18).
1846 Adapted from gcc/config/cris/cris.h. */
1847 static int cris_dwarf_regmap
[] = {
1859 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1860 regnum
= cris_dwarf_regmap
[reg
];
1863 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
1868 /* DWARF-2 frame support. */
1871 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1872 struct dwarf2_frame_state_reg
*reg
,
1873 struct frame_info
*next_frame
)
1875 /* The return address column. */
1876 if (regnum
== gdbarch_pc_regnum (current_gdbarch
))
1877 reg
->how
= DWARF2_FRAME_REG_RA
;
1879 /* The call frame address. */
1880 else if (regnum
== gdbarch_sp_regnum (current_gdbarch
))
1881 reg
->how
= DWARF2_FRAME_REG_CFA
;
1884 /* Extract from an array regbuf containing the raw register state a function
1885 return value of type type, and copy that, in virtual format, into
1888 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1891 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1895 int len
= TYPE_LENGTH (type
);
1899 /* Get the return value from R10. */
1900 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1901 store_unsigned_integer (valbuf
, len
, val
);
1905 /* Get the return value from R10 and R11. */
1906 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1907 store_unsigned_integer (valbuf
, 4, val
);
1908 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1909 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1912 error (_("cris_extract_return_value: type length too large"));
1915 /* Handle the CRIS return value convention. */
1917 static enum return_value_convention
1918 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1919 struct regcache
*regcache
, gdb_byte
*readbuf
,
1920 const gdb_byte
*writebuf
)
1922 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1923 || TYPE_CODE (type
) == TYPE_CODE_UNION
1924 || TYPE_LENGTH (type
) > 8)
1925 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1926 goes on the stack. */
1927 return RETURN_VALUE_STRUCT_CONVENTION
;
1930 cris_extract_return_value (type
, regcache
, readbuf
);
1932 cris_store_return_value (type
, regcache
, writebuf
);
1934 return RETURN_VALUE_REGISTER_CONVENTION
;
1937 /* Returns 1 if the given type will be passed by pointer rather than
1940 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1944 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1946 return (TYPE_LENGTH (type
) > 8);
1949 /* Calculates a value that measures how good inst_args constraints an
1950 instruction. It stems from cris_constraint, found in cris-dis.c. */
1953 constraint (unsigned int insn
, const signed char *inst_args
,
1954 inst_env_type
*inst_env
)
1959 const char *s
= inst_args
;
1965 if ((insn
& 0x30) == 0x30)
1970 /* A prefix operand. */
1971 if (inst_env
->prefix_found
)
1977 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1978 valid "push" size. In case of special register, it may be != 4. */
1979 if (inst_env
->prefix_found
)
1985 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1993 tmp
= (insn
>> 0xC) & 0xF;
1995 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1997 /* Since we match four bits, we will give a value of
1998 4 - 1 = 3 in a match. If there is a corresponding
1999 exact match of a special register in another pattern, it
2000 will get a value of 4, which will be higher. This should
2001 be correct in that an exact pattern would match better that
2003 Note that there is a reason for not returning zero; the
2004 pattern for "clear" is partly matched in the bit-pattern
2005 (the two lower bits must be zero), while the bit-pattern
2006 for a move from a special register is matched in the
2007 register constraint.
2008 This also means we will will have a race condition if
2009 there is a partly match in three bits in the bit pattern. */
2010 if (tmp
== cris_spec_regs
[i
].number
)
2017 if (cris_spec_regs
[i
].name
== NULL
)
2024 /* Returns the number of bits set in the variable value. */
2027 number_of_bits (unsigned int value
)
2029 int number_of_bits
= 0;
2033 number_of_bits
+= 1;
2034 value
&= (value
- 1);
2036 return number_of_bits
;
2039 /* Finds the address that should contain the single step breakpoint(s).
2040 It stems from code in cris-dis.c. */
2043 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
2046 int max_level_of_match
= -1;
2047 int max_matched
= -1;
2050 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
2052 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
2053 && ((cris_opcodes
[i
].lose
& insn
) == 0)
2054 /* Only CRISv10 instructions, please. */
2055 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
2057 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
2058 if (level_of_match
>= 0)
2061 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
2062 if (level_of_match
> max_level_of_match
)
2065 max_level_of_match
= level_of_match
;
2066 if (level_of_match
== 16)
2068 /* All bits matched, cannot find better. */
2078 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2079 actually an internal error. */
2082 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
2086 unsigned short insn
;
2088 /* Create a local register image and set the initial state. */
2089 for (i
= 0; i
< NUM_GENREGS
; i
++)
2092 (unsigned long) get_frame_register_unsigned (frame
, i
);
2094 offset
= NUM_GENREGS
;
2095 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2098 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2100 inst_env
->branch_found
= 0;
2101 inst_env
->slot_needed
= 0;
2102 inst_env
->delay_slot_pc_active
= 0;
2103 inst_env
->prefix_found
= 0;
2104 inst_env
->invalid
= 0;
2105 inst_env
->xflag_found
= 0;
2106 inst_env
->disable_interrupt
= 0;
2108 /* Look for a step target. */
2111 /* Read an instruction from the client. */
2112 insn
= read_memory_unsigned_integer
2113 (inst_env
->reg
[gdbarch_pc_regnum (current_gdbarch
)], 2);
2115 /* If the instruction is not in a delay slot the new content of the
2116 PC is [PC] + 2. If the instruction is in a delay slot it is not
2117 that simple. Since a instruction in a delay slot cannot change
2118 the content of the PC, it does not matter what value PC will have.
2119 Just make sure it is a valid instruction. */
2120 if (!inst_env
->delay_slot_pc_active
)
2122 inst_env
->reg
[gdbarch_pc_regnum (current_gdbarch
)] += 2;
2126 inst_env
->delay_slot_pc_active
= 0;
2127 inst_env
->reg
[gdbarch_pc_regnum (current_gdbarch
)]
2128 = inst_env
->delay_slot_pc
;
2130 /* Analyse the present instruction. */
2131 i
= find_cris_op (insn
, inst_env
);
2134 inst_env
->invalid
= 1;
2138 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
2140 } while (!inst_env
->invalid
2141 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2142 || inst_env
->slot_needed
));
2146 /* There is no hardware single-step support. The function find_step_target
2147 digs through the opcodes in order to find all possible targets.
2148 Either one ordinary target or two targets for branches may be found. */
2151 cris_software_single_step (struct frame_info
*frame
)
2153 inst_env_type inst_env
;
2155 /* Analyse the present instruction environment and insert
2157 int status
= find_step_target (frame
, &inst_env
);
2160 /* Could not find a target. Things are likely to go downhill
2162 warning (_("CRIS software single step could not find a step target."));
2166 /* Insert at most two breakpoints. One for the next PC content
2167 and possibly another one for a branch, jump, etc. */
2169 (CORE_ADDR
) inst_env
.reg
[gdbarch_pc_regnum (current_gdbarch
)];
2170 insert_single_step_breakpoint (next_pc
);
2171 if (inst_env
.branch_found
2172 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2174 CORE_ADDR branch_target_address
2175 = (CORE_ADDR
) inst_env
.branch_break_address
;
2176 insert_single_step_breakpoint (branch_target_address
);
2183 /* Calculates the prefix value for quick offset addressing mode. */
2186 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2188 /* It's invalid to be in a delay slot. You can't have a prefix to this
2189 instruction (not 100% sure). */
2190 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2192 inst_env
->invalid
= 1;
2196 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2197 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2199 /* A prefix doesn't change the xflag_found. But the rest of the flags
2201 inst_env
->slot_needed
= 0;
2202 inst_env
->prefix_found
= 1;
2205 /* Updates the autoincrement register. The size of the increment is derived
2206 from the size of the operation. The PC is always kept aligned on even
2210 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2212 if (size
== INST_BYTE_SIZE
)
2214 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2216 /* The PC must be word aligned, so increase the PC with one
2217 word even if the size is byte. */
2218 if (cris_get_operand1 (inst
) == REG_PC
)
2220 inst_env
->reg
[REG_PC
] += 1;
2223 else if (size
== INST_WORD_SIZE
)
2225 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2227 else if (size
== INST_DWORD_SIZE
)
2229 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2234 inst_env
->invalid
= 1;
2238 /* Just a forward declaration. */
2240 static unsigned long get_data_from_address (unsigned short *inst
,
2243 /* Calculates the prefix value for the general case of offset addressing
2247 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2252 /* It's invalid to be in a delay slot. */
2253 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2255 inst_env
->invalid
= 1;
2259 /* The calculation of prefix_value used to be after process_autoincrement,
2260 but that fails for an instruction such as jsr [$r0+12] which is encoded
2261 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2262 mustn't be incremented until we have read it and what it points at. */
2263 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2265 /* The offset is an indirection of the contents of the operand1 register. */
2266 inst_env
->prefix_value
+=
2267 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
2269 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2271 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2274 /* A prefix doesn't change the xflag_found. But the rest of the flags
2276 inst_env
->slot_needed
= 0;
2277 inst_env
->prefix_found
= 1;
2280 /* Calculates the prefix value for the index addressing mode. */
2283 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2285 /* It's invalid to be in a delay slot. I can't see that it's possible to
2286 have a prefix to this instruction. So I will treat this as invalid. */
2287 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2289 inst_env
->invalid
= 1;
2293 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2295 /* The offset is the operand2 value shifted the size of the instruction
2297 inst_env
->prefix_value
+=
2298 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2300 /* If the PC is operand1 (base) the address used is the address after
2301 the main instruction, i.e. address + 2 (the PC is already compensated
2302 for the prefix operation). */
2303 if (cris_get_operand1 (inst
) == REG_PC
)
2305 inst_env
->prefix_value
+= 2;
2308 /* A prefix doesn't change the xflag_found. But the rest of the flags
2310 inst_env
->slot_needed
= 0;
2311 inst_env
->xflag_found
= 0;
2312 inst_env
->prefix_found
= 1;
2315 /* Calculates the prefix value for the double indirect addressing mode. */
2318 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2323 /* It's invalid to be in a delay slot. */
2324 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2326 inst_env
->invalid
= 1;
2330 /* The prefix value is one dereference of the contents of the operand1
2332 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2333 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
2335 /* Check if the mode is autoincrement. */
2336 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2338 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2341 /* A prefix doesn't change the xflag_found. But the rest of the flags
2343 inst_env
->slot_needed
= 0;
2344 inst_env
->xflag_found
= 0;
2345 inst_env
->prefix_found
= 1;
2348 /* Finds the destination for a branch with 8-bits offset. */
2351 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2356 /* If we have a prefix or are in a delay slot it's bad. */
2357 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2359 inst_env
->invalid
= 1;
2363 /* We have a branch, find out where the branch will land. */
2364 offset
= cris_get_branch_short_offset (inst
);
2366 /* Check if the offset is signed. */
2367 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2372 /* The offset ends with the sign bit, set it to zero. The address
2373 should always be word aligned. */
2374 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2376 inst_env
->branch_found
= 1;
2377 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2379 inst_env
->slot_needed
= 1;
2380 inst_env
->prefix_found
= 0;
2381 inst_env
->xflag_found
= 0;
2382 inst_env
->disable_interrupt
= 1;
2385 /* Finds the destination for a branch with 16-bits offset. */
2388 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2392 /* If we have a prefix or is in a delay slot it's bad. */
2393 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2395 inst_env
->invalid
= 1;
2399 /* We have a branch, find out the offset for the branch. */
2400 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2402 /* The instruction is one word longer than normal, so add one word
2404 inst_env
->reg
[REG_PC
] += 2;
2406 inst_env
->branch_found
= 1;
2407 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2410 inst_env
->slot_needed
= 1;
2411 inst_env
->prefix_found
= 0;
2412 inst_env
->xflag_found
= 0;
2413 inst_env
->disable_interrupt
= 1;
2416 /* Handles the ABS instruction. */
2419 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2424 /* ABS can't have a prefix, so it's bad if it does. */
2425 if (inst_env
->prefix_found
)
2427 inst_env
->invalid
= 1;
2431 /* Check if the operation affects the PC. */
2432 if (cris_get_operand2 (inst
) == REG_PC
)
2435 /* It's invalid to change to the PC if we are in a delay slot. */
2436 if (inst_env
->slot_needed
)
2438 inst_env
->invalid
= 1;
2442 value
= (long) inst_env
->reg
[REG_PC
];
2444 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2445 if (value
!= SIGNED_DWORD_MASK
)
2448 inst_env
->reg
[REG_PC
] = (long) value
;
2452 inst_env
->slot_needed
= 0;
2453 inst_env
->prefix_found
= 0;
2454 inst_env
->xflag_found
= 0;
2455 inst_env
->disable_interrupt
= 0;
2458 /* Handles the ADDI instruction. */
2461 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2463 /* It's invalid to have the PC as base register. And ADDI can't have
2465 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2467 inst_env
->invalid
= 1;
2471 inst_env
->slot_needed
= 0;
2472 inst_env
->prefix_found
= 0;
2473 inst_env
->xflag_found
= 0;
2474 inst_env
->disable_interrupt
= 0;
2477 /* Handles the ASR instruction. */
2480 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2483 unsigned long value
;
2484 unsigned long signed_extend_mask
= 0;
2486 /* ASR can't have a prefix, so check that it doesn't. */
2487 if (inst_env
->prefix_found
)
2489 inst_env
->invalid
= 1;
2493 /* Check if the PC is the target register. */
2494 if (cris_get_operand2 (inst
) == REG_PC
)
2496 /* It's invalid to change the PC in a delay slot. */
2497 if (inst_env
->slot_needed
)
2499 inst_env
->invalid
= 1;
2502 /* Get the number of bits to shift. */
2503 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2504 value
= inst_env
->reg
[REG_PC
];
2506 /* Find out how many bits the operation should apply to. */
2507 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2509 if (value
& SIGNED_BYTE_MASK
)
2511 signed_extend_mask
= 0xFF;
2512 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2513 signed_extend_mask
= ~signed_extend_mask
;
2515 value
= value
>> shift_steps
;
2516 value
|= signed_extend_mask
;
2518 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2519 inst_env
->reg
[REG_PC
] |= value
;
2521 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2523 if (value
& SIGNED_WORD_MASK
)
2525 signed_extend_mask
= 0xFFFF;
2526 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2527 signed_extend_mask
= ~signed_extend_mask
;
2529 value
= value
>> shift_steps
;
2530 value
|= signed_extend_mask
;
2532 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2533 inst_env
->reg
[REG_PC
] |= value
;
2535 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2537 if (value
& SIGNED_DWORD_MASK
)
2539 signed_extend_mask
= 0xFFFFFFFF;
2540 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2541 signed_extend_mask
= ~signed_extend_mask
;
2543 value
= value
>> shift_steps
;
2544 value
|= signed_extend_mask
;
2545 inst_env
->reg
[REG_PC
] = value
;
2548 inst_env
->slot_needed
= 0;
2549 inst_env
->prefix_found
= 0;
2550 inst_env
->xflag_found
= 0;
2551 inst_env
->disable_interrupt
= 0;
2554 /* Handles the ASRQ instruction. */
2557 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2561 unsigned long value
;
2562 unsigned long signed_extend_mask
= 0;
2564 /* ASRQ can't have a prefix, so check that it doesn't. */
2565 if (inst_env
->prefix_found
)
2567 inst_env
->invalid
= 1;
2571 /* Check if the PC is the target register. */
2572 if (cris_get_operand2 (inst
) == REG_PC
)
2575 /* It's invalid to change the PC in a delay slot. */
2576 if (inst_env
->slot_needed
)
2578 inst_env
->invalid
= 1;
2581 /* The shift size is given as a 5 bit quick value, i.e. we don't
2582 want the the sign bit of the quick value. */
2583 shift_steps
= cris_get_asr_shift_steps (inst
);
2584 value
= inst_env
->reg
[REG_PC
];
2585 if (value
& SIGNED_DWORD_MASK
)
2587 signed_extend_mask
= 0xFFFFFFFF;
2588 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2589 signed_extend_mask
= ~signed_extend_mask
;
2591 value
= value
>> shift_steps
;
2592 value
|= signed_extend_mask
;
2593 inst_env
->reg
[REG_PC
] = value
;
2595 inst_env
->slot_needed
= 0;
2596 inst_env
->prefix_found
= 0;
2597 inst_env
->xflag_found
= 0;
2598 inst_env
->disable_interrupt
= 0;
2601 /* Handles the AX, EI and SETF instruction. */
2604 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2606 if (inst_env
->prefix_found
)
2608 inst_env
->invalid
= 1;
2611 /* Check if the instruction is setting the X flag. */
2612 if (cris_is_xflag_bit_on (inst
))
2614 inst_env
->xflag_found
= 1;
2618 inst_env
->xflag_found
= 0;
2620 inst_env
->slot_needed
= 0;
2621 inst_env
->prefix_found
= 0;
2622 inst_env
->disable_interrupt
= 1;
2625 /* Checks if the instruction is in assign mode. If so, it updates the assign
2626 register. Note that check_assign assumes that the caller has checked that
2627 there is a prefix to this instruction. The mode check depends on this. */
2630 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2632 /* Check if it's an assign addressing mode. */
2633 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2635 /* Assign the prefix value to operand 1. */
2636 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2640 /* Handles the 2-operand BOUND instruction. */
2643 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2645 /* It's invalid to have the PC as the index operand. */
2646 if (cris_get_operand2 (inst
) == REG_PC
)
2648 inst_env
->invalid
= 1;
2651 /* Check if we have a prefix. */
2652 if (inst_env
->prefix_found
)
2654 check_assign (inst
, inst_env
);
2656 /* Check if this is an autoincrement mode. */
2657 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2659 /* It's invalid to change the PC in a delay slot. */
2660 if (inst_env
->slot_needed
)
2662 inst_env
->invalid
= 1;
2665 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2667 inst_env
->slot_needed
= 0;
2668 inst_env
->prefix_found
= 0;
2669 inst_env
->xflag_found
= 0;
2670 inst_env
->disable_interrupt
= 0;
2673 /* Handles the 3-operand BOUND instruction. */
2676 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2678 /* It's an error if we haven't got a prefix. And it's also an error
2679 if the PC is the destination register. */
2680 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2682 inst_env
->invalid
= 1;
2685 inst_env
->slot_needed
= 0;
2686 inst_env
->prefix_found
= 0;
2687 inst_env
->xflag_found
= 0;
2688 inst_env
->disable_interrupt
= 0;
2691 /* Clears the status flags in inst_env. */
2694 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2696 /* It's an error if we have got a prefix. */
2697 if (inst_env
->prefix_found
)
2699 inst_env
->invalid
= 1;
2703 inst_env
->slot_needed
= 0;
2704 inst_env
->prefix_found
= 0;
2705 inst_env
->xflag_found
= 0;
2706 inst_env
->disable_interrupt
= 0;
2709 /* Clears the status flags in inst_env. */
2712 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2714 /* It's an error if we have got a prefix. */
2715 if (inst_env
->prefix_found
)
2717 inst_env
->invalid
= 1;
2721 inst_env
->slot_needed
= 0;
2722 inst_env
->prefix_found
= 0;
2723 inst_env
->xflag_found
= 0;
2724 inst_env
->disable_interrupt
= 1;
2727 /* Handles the CLEAR instruction if it's in register mode. */
2730 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2732 /* Check if the target is the PC. */
2733 if (cris_get_operand2 (inst
) == REG_PC
)
2735 /* The instruction will clear the instruction's size bits. */
2736 int clear_size
= cris_get_clear_size (inst
);
2737 if (clear_size
== INST_BYTE_SIZE
)
2739 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2741 if (clear_size
== INST_WORD_SIZE
)
2743 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2745 if (clear_size
== INST_DWORD_SIZE
)
2747 inst_env
->delay_slot_pc
= 0x0;
2749 /* The jump will be delayed with one delay slot. So we need a delay
2751 inst_env
->slot_needed
= 1;
2752 inst_env
->delay_slot_pc_active
= 1;
2756 /* The PC will not change => no delay slot. */
2757 inst_env
->slot_needed
= 0;
2759 inst_env
->prefix_found
= 0;
2760 inst_env
->xflag_found
= 0;
2761 inst_env
->disable_interrupt
= 0;
2764 /* Handles the TEST instruction if it's in register mode. */
2767 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2769 /* It's an error if we have got a prefix. */
2770 if (inst_env
->prefix_found
)
2772 inst_env
->invalid
= 1;
2775 inst_env
->slot_needed
= 0;
2776 inst_env
->prefix_found
= 0;
2777 inst_env
->xflag_found
= 0;
2778 inst_env
->disable_interrupt
= 0;
2782 /* Handles the CLEAR and TEST instruction if the instruction isn't
2783 in register mode. */
2786 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2788 /* Check if we are in a prefix mode. */
2789 if (inst_env
->prefix_found
)
2791 /* The only way the PC can change is if this instruction is in
2792 assign addressing mode. */
2793 check_assign (inst
, inst_env
);
2795 /* Indirect mode can't change the PC so just check if the mode is
2797 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2799 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2801 inst_env
->slot_needed
= 0;
2802 inst_env
->prefix_found
= 0;
2803 inst_env
->xflag_found
= 0;
2804 inst_env
->disable_interrupt
= 0;
2807 /* Checks that the PC isn't the destination register or the instructions has
2811 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2813 /* It's invalid to have the PC as the destination. The instruction can't
2815 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2817 inst_env
->invalid
= 1;
2821 inst_env
->slot_needed
= 0;
2822 inst_env
->prefix_found
= 0;
2823 inst_env
->xflag_found
= 0;
2824 inst_env
->disable_interrupt
= 0;
2827 /* Checks that the instruction doesn't have a prefix. */
2830 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2832 /* The instruction can't have a prefix. */
2833 if (inst_env
->prefix_found
)
2835 inst_env
->invalid
= 1;
2839 inst_env
->slot_needed
= 0;
2840 inst_env
->prefix_found
= 0;
2841 inst_env
->xflag_found
= 0;
2842 inst_env
->disable_interrupt
= 1;
2845 /* Checks that the PC isn't the destination register and that the instruction
2846 doesn't have a prefix. */
2849 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2851 /* It's invalid to have the PC as the destination. The instruction can't
2853 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2855 inst_env
->invalid
= 1;
2859 inst_env
->slot_needed
= 0;
2860 inst_env
->prefix_found
= 0;
2861 inst_env
->xflag_found
= 0;
2862 inst_env
->disable_interrupt
= 1;
2865 /* Handles the register mode JUMP instruction. */
2868 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2870 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2871 you can't have a prefix. */
2872 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2874 inst_env
->invalid
= 1;
2878 /* Just change the PC. */
2879 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2880 inst_env
->slot_needed
= 0;
2881 inst_env
->prefix_found
= 0;
2882 inst_env
->xflag_found
= 0;
2883 inst_env
->disable_interrupt
= 1;
2886 /* Handles the JUMP instruction for all modes except register. */
2889 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2891 unsigned long newpc
;
2894 /* It's invalid to do a JUMP in a delay slot. */
2895 if (inst_env
->slot_needed
)
2897 inst_env
->invalid
= 1;
2901 /* Check if we have a prefix. */
2902 if (inst_env
->prefix_found
)
2904 check_assign (inst
, inst_env
);
2906 /* Get the new value for the the PC. */
2908 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2913 /* Get the new value for the PC. */
2914 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2915 newpc
= read_memory_unsigned_integer (address
, 4);
2917 /* Check if we should increment a register. */
2918 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2920 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2923 inst_env
->reg
[REG_PC
] = newpc
;
2925 inst_env
->slot_needed
= 0;
2926 inst_env
->prefix_found
= 0;
2927 inst_env
->xflag_found
= 0;
2928 inst_env
->disable_interrupt
= 1;
2931 /* Handles moves to special registers (aka P-register) for all modes. */
2934 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2936 if (inst_env
->prefix_found
)
2938 /* The instruction has a prefix that means we are only interested if
2939 the instruction is in assign mode. */
2940 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2942 /* The prefix handles the problem if we are in a delay slot. */
2943 if (cris_get_operand1 (inst
) == REG_PC
)
2945 /* Just take care of the assign. */
2946 check_assign (inst
, inst_env
);
2950 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2952 /* The instruction doesn't have a prefix, the only case left that we
2953 are interested in is the autoincrement mode. */
2954 if (cris_get_operand1 (inst
) == REG_PC
)
2956 /* If the PC is to be incremented it's invalid to be in a
2958 if (inst_env
->slot_needed
)
2960 inst_env
->invalid
= 1;
2964 /* The increment depends on the size of the special register. */
2965 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2967 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2969 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2971 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2975 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2979 inst_env
->slot_needed
= 0;
2980 inst_env
->prefix_found
= 0;
2981 inst_env
->xflag_found
= 0;
2982 inst_env
->disable_interrupt
= 1;
2985 /* Handles moves from special registers (aka P-register) for all modes
2989 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2991 if (inst_env
->prefix_found
)
2993 /* The instruction has a prefix that means we are only interested if
2994 the instruction is in assign mode. */
2995 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2997 /* The prefix handles the problem if we are in a delay slot. */
2998 if (cris_get_operand1 (inst
) == REG_PC
)
3000 /* Just take care of the assign. */
3001 check_assign (inst
, inst_env
);
3005 /* The instruction doesn't have a prefix, the only case left that we
3006 are interested in is the autoincrement mode. */
3007 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
3009 if (cris_get_operand1 (inst
) == REG_PC
)
3011 /* If the PC is to be incremented it's invalid to be in a
3013 if (inst_env
->slot_needed
)
3015 inst_env
->invalid
= 1;
3019 /* The increment depends on the size of the special register. */
3020 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
3022 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
3024 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
3026 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
3030 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
3034 inst_env
->slot_needed
= 0;
3035 inst_env
->prefix_found
= 0;
3036 inst_env
->xflag_found
= 0;
3037 inst_env
->disable_interrupt
= 1;
3040 /* Handles moves from special registers (aka P-register) when the mode
3044 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
3046 /* Register mode move from special register can't have a prefix. */
3047 if (inst_env
->prefix_found
)
3049 inst_env
->invalid
= 1;
3053 if (cris_get_operand1 (inst
) == REG_PC
)
3055 /* It's invalid to change the PC in a delay slot. */
3056 if (inst_env
->slot_needed
)
3058 inst_env
->invalid
= 1;
3061 /* The destination is the PC, the jump will have a delay slot. */
3062 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
3063 inst_env
->slot_needed
= 1;
3064 inst_env
->delay_slot_pc_active
= 1;
3068 /* If the destination isn't PC, there will be no jump. */
3069 inst_env
->slot_needed
= 0;
3071 inst_env
->prefix_found
= 0;
3072 inst_env
->xflag_found
= 0;
3073 inst_env
->disable_interrupt
= 1;
3076 /* Handles the MOVEM from memory to general register instruction. */
3079 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3081 if (inst_env
->prefix_found
)
3083 /* The prefix handles the problem if we are in a delay slot. Is the
3084 MOVEM instruction going to change the PC? */
3085 if (cris_get_operand2 (inst
) >= REG_PC
)
3087 inst_env
->reg
[REG_PC
] =
3088 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
3090 /* The assign value is the value after the increment. Normally, the
3091 assign value is the value before the increment. */
3092 if ((cris_get_operand1 (inst
) == REG_PC
)
3093 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3095 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3096 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3101 /* Is the MOVEM instruction going to change the PC? */
3102 if (cris_get_operand2 (inst
) == REG_PC
)
3104 /* It's invalid to change the PC in a delay slot. */
3105 if (inst_env
->slot_needed
)
3107 inst_env
->invalid
= 1;
3110 inst_env
->reg
[REG_PC
] =
3111 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3114 /* The increment is not depending on the size, instead it's depending
3115 on the number of registers loaded from memory. */
3116 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3118 /* It's invalid to change the PC in a delay slot. */
3119 if (inst_env
->slot_needed
)
3121 inst_env
->invalid
= 1;
3124 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3127 inst_env
->slot_needed
= 0;
3128 inst_env
->prefix_found
= 0;
3129 inst_env
->xflag_found
= 0;
3130 inst_env
->disable_interrupt
= 0;
3133 /* Handles the MOVEM to memory from general register instruction. */
3136 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3138 if (inst_env
->prefix_found
)
3140 /* The assign value is the value after the increment. Normally, the
3141 assign value is the value before the increment. */
3142 if ((cris_get_operand1 (inst
) == REG_PC
) &&
3143 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3145 /* The prefix handles the problem if we are in a delay slot. */
3146 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3147 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3152 /* The increment is not depending on the size, instead it's depending
3153 on the number of registers loaded to memory. */
3154 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3156 /* It's invalid to change the PC in a delay slot. */
3157 if (inst_env
->slot_needed
)
3159 inst_env
->invalid
= 1;
3162 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3165 inst_env
->slot_needed
= 0;
3166 inst_env
->prefix_found
= 0;
3167 inst_env
->xflag_found
= 0;
3168 inst_env
->disable_interrupt
= 0;
3171 /* Handles the intructions that's not yet implemented, by setting
3172 inst_env->invalid to true. */
3175 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3177 inst_env
->invalid
= 1;
3180 /* Handles the XOR instruction. */
3183 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3185 /* XOR can't have a prefix. */
3186 if (inst_env
->prefix_found
)
3188 inst_env
->invalid
= 1;
3192 /* Check if the PC is the target. */
3193 if (cris_get_operand2 (inst
) == REG_PC
)
3195 /* It's invalid to change the PC in a delay slot. */
3196 if (inst_env
->slot_needed
)
3198 inst_env
->invalid
= 1;
3201 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3203 inst_env
->slot_needed
= 0;
3204 inst_env
->prefix_found
= 0;
3205 inst_env
->xflag_found
= 0;
3206 inst_env
->disable_interrupt
= 0;
3209 /* Handles the MULS instruction. */
3212 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3214 /* MULS/U can't have a prefix. */
3215 if (inst_env
->prefix_found
)
3217 inst_env
->invalid
= 1;
3221 /* Consider it invalid if the PC is the target. */
3222 if (cris_get_operand2 (inst
) == REG_PC
)
3224 inst_env
->invalid
= 1;
3227 inst_env
->slot_needed
= 0;
3228 inst_env
->prefix_found
= 0;
3229 inst_env
->xflag_found
= 0;
3230 inst_env
->disable_interrupt
= 0;
3233 /* Handles the MULU instruction. */
3236 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3238 /* MULS/U can't have a prefix. */
3239 if (inst_env
->prefix_found
)
3241 inst_env
->invalid
= 1;
3245 /* Consider it invalid if the PC is the target. */
3246 if (cris_get_operand2 (inst
) == REG_PC
)
3248 inst_env
->invalid
= 1;
3251 inst_env
->slot_needed
= 0;
3252 inst_env
->prefix_found
= 0;
3253 inst_env
->xflag_found
= 0;
3254 inst_env
->disable_interrupt
= 0;
3257 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3258 The MOVE instruction is the move from source to register. */
3261 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3262 unsigned long source1
, unsigned long source2
)
3264 unsigned long pc_mask
;
3265 unsigned long operation_mask
;
3267 /* Find out how many bits the operation should apply to. */
3268 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3270 pc_mask
= 0xFFFFFF00;
3271 operation_mask
= 0xFF;
3273 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3275 pc_mask
= 0xFFFF0000;
3276 operation_mask
= 0xFFFF;
3278 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3281 operation_mask
= 0xFFFFFFFF;
3285 /* The size is out of range. */
3286 inst_env
->invalid
= 1;
3290 /* The instruction just works on uw_operation_mask bits. */
3291 source2
&= operation_mask
;
3292 source1
&= operation_mask
;
3294 /* Now calculate the result. The opcode's 3 first bits separates
3295 the different actions. */
3296 switch (cris_get_opcode (inst
) & 7)
3306 case 2: /* subtract */
3310 case 3: /* compare */
3322 inst_env
->invalid
= 1;
3328 /* Make sure that the result doesn't contain more than the instruction
3330 source2
&= operation_mask
;
3332 /* Calculate the new breakpoint address. */
3333 inst_env
->reg
[REG_PC
] &= pc_mask
;
3334 inst_env
->reg
[REG_PC
] |= source1
;
3338 /* Extends the value from either byte or word size to a dword. If the mode
3339 is zero extend then the value is extended with zero. If instead the mode
3340 is signed extend the sign bit of the value is taken into consideration. */
3342 static unsigned long
3343 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3345 /* The size can be either byte or word, check which one it is.
3346 Don't check the highest bit, it's indicating if it's a zero
3348 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3353 /* Check if the instruction is signed extend. If so, check if value has
3355 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3357 value
|= SIGNED_WORD_EXTEND_MASK
;
3365 /* Check if the instruction is signed extend. If so, check if value has
3367 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3369 value
|= SIGNED_BYTE_EXTEND_MASK
;
3372 /* The size should now be dword. */
3373 cris_set_size_to_dword (inst
);
3377 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3378 instruction. The MOVE instruction is the move from source to register. */
3381 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3382 inst_env_type
*inst_env
)
3384 unsigned long operand1
;
3385 unsigned long operand2
;
3387 /* It's invalid to have a prefix to the instruction. This is a register
3388 mode instruction and can't have a prefix. */
3389 if (inst_env
->prefix_found
)
3391 inst_env
->invalid
= 1;
3394 /* Check if the instruction has PC as its target. */
3395 if (cris_get_operand2 (inst
) == REG_PC
)
3397 if (inst_env
->slot_needed
)
3399 inst_env
->invalid
= 1;
3402 /* The instruction has the PC as its target register. */
3403 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3404 operand2
= inst_env
->reg
[REG_PC
];
3406 /* Check if it's a extend, signed or zero instruction. */
3407 if (cris_get_opcode (inst
) < 4)
3409 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3411 /* Calculate the PC value after the instruction, i.e. where the
3412 breakpoint should be. The order of the udw_operands is vital. */
3413 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3415 inst_env
->slot_needed
= 0;
3416 inst_env
->prefix_found
= 0;
3417 inst_env
->xflag_found
= 0;
3418 inst_env
->disable_interrupt
= 0;
3421 /* Returns the data contained at address. The size of the data is derived from
3422 the size of the operation. If the instruction is a zero or signed
3423 extend instruction, the size field is changed in instruction. */
3425 static unsigned long
3426 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3428 int size
= cris_get_size (*inst
);
3429 unsigned long value
;
3431 /* If it's an extend instruction we don't want the signed extend bit,
3432 because it influences the size. */
3433 if (cris_get_opcode (*inst
) < 4)
3435 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3437 /* Is there a need for checking the size? Size should contain the number of
3440 value
= read_memory_unsigned_integer (address
, size
);
3442 /* Check if it's an extend, signed or zero instruction. */
3443 if (cris_get_opcode (*inst
) < 4)
3445 value
= do_sign_or_zero_extend (value
, inst
);
3450 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3451 instructions. The MOVE instruction is the move from source to register. */
3454 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3455 inst_env_type
*inst_env
)
3457 unsigned long operand2
;
3458 unsigned long operand3
;
3460 check_assign (inst
, inst_env
);
3461 if (cris_get_operand2 (inst
) == REG_PC
)
3463 operand2
= inst_env
->reg
[REG_PC
];
3465 /* Get the value of the third operand. */
3466 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3468 /* Calculate the PC value after the instruction, i.e. where the
3469 breakpoint should be. The order of the udw_operands is vital. */
3470 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3472 inst_env
->slot_needed
= 0;
3473 inst_env
->prefix_found
= 0;
3474 inst_env
->xflag_found
= 0;
3475 inst_env
->disable_interrupt
= 0;
3478 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3479 OR instructions. Note that for this to work as expected, the calling
3480 function must have made sure that there is a prefix to this instruction. */
3483 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3484 inst_env_type
*inst_env
)
3486 unsigned long operand2
;
3487 unsigned long operand3
;
3489 if (cris_get_operand1 (inst
) == REG_PC
)
3491 /* The PC will be changed by the instruction. */
3492 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3494 /* Get the value of the third operand. */
3495 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3497 /* Calculate the PC value after the instruction, i.e. where the
3498 breakpoint should be. */
3499 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3501 inst_env
->slot_needed
= 0;
3502 inst_env
->prefix_found
= 0;
3503 inst_env
->xflag_found
= 0;
3504 inst_env
->disable_interrupt
= 0;
3507 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3508 instructions. The MOVE instruction is the move from source to register. */
3511 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3512 inst_env_type
*inst_env
)
3514 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3516 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3517 SUB, AND or OR something weird is going on (if everything works these
3518 instructions should end up in the three operand version). */
3519 inst_env
->invalid
= 1;
3524 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3526 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3528 inst_env
->slot_needed
= 0;
3529 inst_env
->prefix_found
= 0;
3530 inst_env
->xflag_found
= 0;
3531 inst_env
->disable_interrupt
= 0;
3534 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3535 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3536 source to register. */
3539 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3540 inst_env_type
*inst_env
)
3542 unsigned long operand1
;
3543 unsigned long operand2
;
3544 unsigned long operand3
;
3547 /* The instruction is either an indirect or autoincrement addressing mode.
3548 Check if the destination register is the PC. */
3549 if (cris_get_operand2 (inst
) == REG_PC
)
3551 /* Must be done here, get_data_from_address may change the size
3553 size
= cris_get_size (inst
);
3554 operand2
= inst_env
->reg
[REG_PC
];
3556 /* Get the value of the third operand, i.e. the indirect operand. */
3557 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3558 operand3
= get_data_from_address (&inst
, operand1
);
3560 /* Calculate the PC value after the instruction, i.e. where the
3561 breakpoint should be. The order of the udw_operands is vital. */
3562 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3564 /* If this is an autoincrement addressing mode, check if the increment
3566 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3568 /* Get the size field. */
3569 size
= cris_get_size (inst
);
3571 /* If it's an extend instruction we don't want the signed extend bit,
3572 because it influences the size. */
3573 if (cris_get_opcode (inst
) < 4)
3575 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3577 process_autoincrement (size
, inst
, inst_env
);
3579 inst_env
->slot_needed
= 0;
3580 inst_env
->prefix_found
= 0;
3581 inst_env
->xflag_found
= 0;
3582 inst_env
->disable_interrupt
= 0;
3585 /* Handles the two-operand addressing mode, all modes except register, for
3586 the ADD, SUB CMP, AND and OR instruction. */
3589 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3590 inst_env_type
*inst_env
)
3592 if (inst_env
->prefix_found
)
3594 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3596 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3598 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3600 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3604 /* The mode is invalid for a prefixed base instruction. */
3605 inst_env
->invalid
= 1;
3611 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3615 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3618 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3620 unsigned long operand1
;
3621 unsigned long operand2
;
3623 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3624 instruction and can't have a prefix. */
3625 if (inst_env
->prefix_found
)
3627 inst_env
->invalid
= 1;
3631 /* Check if the instruction has PC as its target. */
3632 if (cris_get_operand2 (inst
) == REG_PC
)
3634 if (inst_env
->slot_needed
)
3636 inst_env
->invalid
= 1;
3639 operand1
= cris_get_quick_value (inst
);
3640 operand2
= inst_env
->reg
[REG_PC
];
3642 /* The size should now be dword. */
3643 cris_set_size_to_dword (&inst
);
3645 /* Calculate the PC value after the instruction, i.e. where the
3646 breakpoint should be. */
3647 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3649 inst_env
->slot_needed
= 0;
3650 inst_env
->prefix_found
= 0;
3651 inst_env
->xflag_found
= 0;
3652 inst_env
->disable_interrupt
= 0;
3655 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3658 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3660 unsigned long operand1
;
3661 unsigned long operand2
;
3663 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3664 instruction and can't have a prefix. */
3665 if (inst_env
->prefix_found
)
3667 inst_env
->invalid
= 1;
3670 /* Check if the instruction has PC as its target. */
3671 if (cris_get_operand2 (inst
) == REG_PC
)
3673 if (inst_env
->slot_needed
)
3675 inst_env
->invalid
= 1;
3678 /* The instruction has the PC as its target register. */
3679 operand1
= cris_get_quick_value (inst
);
3680 operand2
= inst_env
->reg
[REG_PC
];
3682 /* The quick value is signed, so check if we must do a signed extend. */
3683 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3686 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3688 /* The size should now be dword. */
3689 cris_set_size_to_dword (&inst
);
3691 /* Calculate the PC value after the instruction, i.e. where the
3692 breakpoint should be. */
3693 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3695 inst_env
->slot_needed
= 0;
3696 inst_env
->prefix_found
= 0;
3697 inst_env
->xflag_found
= 0;
3698 inst_env
->disable_interrupt
= 0;
3701 /* Translate op_type to a function and call it. */
3704 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3705 inst_env_type
*inst_env
)
3709 case cris_not_implemented_op
:
3710 not_implemented_op (inst
, inst_env
);
3714 abs_op (inst
, inst_env
);
3718 addi_op (inst
, inst_env
);
3722 asr_op (inst
, inst_env
);
3726 asrq_op (inst
, inst_env
);
3729 case cris_ax_ei_setf_op
:
3730 ax_ei_setf_op (inst
, inst_env
);
3733 case cris_bdap_prefix
:
3734 bdap_prefix (inst
, inst_env
);
3737 case cris_biap_prefix
:
3738 biap_prefix (inst
, inst_env
);
3742 break_op (inst
, inst_env
);
3745 case cris_btst_nop_op
:
3746 btst_nop_op (inst
, inst_env
);
3749 case cris_clearf_di_op
:
3750 clearf_di_op (inst
, inst_env
);
3753 case cris_dip_prefix
:
3754 dip_prefix (inst
, inst_env
);
3757 case cris_dstep_logshift_mstep_neg_not_op
:
3758 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3761 case cris_eight_bit_offset_branch_op
:
3762 eight_bit_offset_branch_op (inst
, inst_env
);
3765 case cris_move_mem_to_reg_movem_op
:
3766 move_mem_to_reg_movem_op (inst
, inst_env
);
3769 case cris_move_reg_to_mem_movem_op
:
3770 move_reg_to_mem_movem_op (inst
, inst_env
);
3773 case cris_move_to_preg_op
:
3774 move_to_preg_op (inst
, inst_env
);
3778 muls_op (inst
, inst_env
);
3782 mulu_op (inst
, inst_env
);
3785 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3786 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3789 case cris_none_reg_mode_clear_test_op
:
3790 none_reg_mode_clear_test_op (inst
, inst_env
);
3793 case cris_none_reg_mode_jump_op
:
3794 none_reg_mode_jump_op (inst
, inst_env
);
3797 case cris_none_reg_mode_move_from_preg_op
:
3798 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3801 case cris_quick_mode_add_sub_op
:
3802 quick_mode_add_sub_op (inst
, inst_env
);
3805 case cris_quick_mode_and_cmp_move_or_op
:
3806 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3809 case cris_quick_mode_bdap_prefix
:
3810 quick_mode_bdap_prefix (inst
, inst_env
);
3813 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3814 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3817 case cris_reg_mode_clear_op
:
3818 reg_mode_clear_op (inst
, inst_env
);
3821 case cris_reg_mode_jump_op
:
3822 reg_mode_jump_op (inst
, inst_env
);
3825 case cris_reg_mode_move_from_preg_op
:
3826 reg_mode_move_from_preg_op (inst
, inst_env
);
3829 case cris_reg_mode_test_op
:
3830 reg_mode_test_op (inst
, inst_env
);
3834 scc_op (inst
, inst_env
);
3837 case cris_sixteen_bit_offset_branch_op
:
3838 sixteen_bit_offset_branch_op (inst
, inst_env
);
3841 case cris_three_operand_add_sub_cmp_and_or_op
:
3842 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3845 case cris_three_operand_bound_op
:
3846 three_operand_bound_op (inst
, inst_env
);
3849 case cris_two_operand_bound_op
:
3850 two_operand_bound_op (inst
, inst_env
);
3854 xor_op (inst
, inst_env
);
3859 /* This wrapper is to avoid cris_get_assembler being called before
3860 exec_bfd has been set. */
3863 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3865 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3866 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3867 disassembler, even when there is no BFD. Does something like
3868 "gdb; target remote; disassmeble *0x123" work? */
3869 gdb_assert (exec_bfd
!= NULL
);
3870 print_insn
= cris_get_disassembler (exec_bfd
);
3871 gdb_assert (print_insn
!= NULL
);
3872 return print_insn (addr
, info
);
3875 /* Copied from <asm/elf.h>. */
3876 typedef unsigned long elf_greg_t
;
3878 /* Same as user_regs_struct struct in <asm/user.h>. */
3879 #define CRISV10_ELF_NGREG 35
3880 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3882 #define CRISV32_ELF_NGREG 32
3883 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3885 /* Unpack an elf_gregset_t into GDB's register cache. */
3888 cris_supply_gregset (struct regcache
*regcache
, elf_gregset_t
*gregsetp
)
3890 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3892 elf_greg_t
*regp
= *gregsetp
;
3893 static char zerobuf
[4] = {0};
3895 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3896 knows about the actual size of each register so that's no problem. */
3897 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3899 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3902 if (tdep
->cris_version
== 32)
3904 /* Needed to set pseudo-register PC for CRISv32. */
3905 /* FIXME: If ERP is in a delay slot at this point then the PC will
3906 be wrong. Issue a warning to alert the user. */
3907 regcache_raw_supply (regcache
, gdbarch_pc_regnum (current_gdbarch
),
3908 (char *)®p
[ERP_REGNUM
]);
3910 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3911 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3915 /* Use a local version of this function to get the correct types for
3916 regsets, until multi-arch core support is ready. */
3919 fetch_core_registers (struct regcache
*regcache
,
3920 char *core_reg_sect
, unsigned core_reg_size
,
3921 int which
, CORE_ADDR reg_addr
)
3923 elf_gregset_t gregset
;
3928 if (core_reg_size
!= sizeof (elf_gregset_t
)
3929 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3931 warning (_("wrong size gregset struct in core file"));
3935 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3936 cris_supply_gregset (regcache
, &gregset
);
3940 /* We've covered all the kinds of registers we know about here,
3941 so this must be something we wouldn't know what to do with
3942 anyway. Just ignore it. */
3947 static struct core_fns cris_elf_core_fns
=
3949 bfd_target_elf_flavour
, /* core_flavour */
3950 default_check_format
, /* check_format */
3951 default_core_sniffer
, /* core_sniffer */
3952 fetch_core_registers
, /* core_read_registers */
3956 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3959 _initialize_cris_tdep (void)
3961 static struct cmd_list_element
*cris_set_cmdlist
;
3962 static struct cmd_list_element
*cris_show_cmdlist
;
3964 struct cmd_list_element
*c
;
3966 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3968 /* CRIS-specific user-commands. */
3969 add_setshow_uinteger_cmd ("cris-version", class_support
,
3970 &usr_cmd_cris_version
,
3971 _("Set the current CRIS version."),
3972 _("Show the current CRIS version."),
3974 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3977 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3978 &setlist
, &showlist
);
3980 add_setshow_enum_cmd ("cris-mode", class_support
,
3981 cris_modes
, &usr_cmd_cris_mode
,
3982 _("Set the current CRIS mode."),
3983 _("Show the current CRIS mode."),
3985 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3986 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3988 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3989 &setlist
, &showlist
);
3991 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3992 &usr_cmd_cris_dwarf2_cfi
,
3993 _("Set the usage of Dwarf-2 CFI for CRIS."),
3994 _("Show the usage of Dwarf-2 CFI for CRIS."),
3995 _("Set this to \"off\" if using gcc-cris < R59."),
3996 set_cris_dwarf2_cfi
,
3997 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3998 &setlist
, &showlist
);
4000 deprecated_add_core_fns (&cris_elf_core_fns
);
4003 /* Prints out all target specific values. */
4006 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
4008 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4011 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
4012 tdep
->cris_version
);
4013 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
4015 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4016 tdep
->cris_dwarf2_cfi
);
4021 set_cris_version (char *ignore_args
, int from_tty
,
4022 struct cmd_list_element
*c
)
4024 struct gdbarch_info info
;
4026 usr_cmd_cris_version_valid
= 1;
4028 /* Update the current architecture, if needed. */
4029 gdbarch_info_init (&info
);
4030 if (!gdbarch_update_p (info
))
4031 internal_error (__FILE__
, __LINE__
,
4032 _("cris_gdbarch_update: failed to update architecture."));
4036 set_cris_mode (char *ignore_args
, int from_tty
,
4037 struct cmd_list_element
*c
)
4039 struct gdbarch_info info
;
4041 /* Update the current architecture, if needed. */
4042 gdbarch_info_init (&info
);
4043 if (!gdbarch_update_p (info
))
4044 internal_error (__FILE__
, __LINE__
,
4045 "cris_gdbarch_update: failed to update architecture.");
4049 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
4050 struct cmd_list_element
*c
)
4052 struct gdbarch_info info
;
4054 /* Update the current architecture, if needed. */
4055 gdbarch_info_init (&info
);
4056 if (!gdbarch_update_p (info
))
4057 internal_error (__FILE__
, __LINE__
,
4058 _("cris_gdbarch_update: failed to update architecture."));
4061 static struct gdbarch
*
4062 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4064 struct gdbarch
*gdbarch
;
4065 struct gdbarch_tdep
*tdep
;
4068 if (usr_cmd_cris_version_valid
)
4070 /* Trust the user's CRIS version setting. */
4071 cris_version
= usr_cmd_cris_version
;
4073 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4079 /* Assume it's CRIS version 10. */
4083 /* Make the current settings visible to the user. */
4084 usr_cmd_cris_version
= cris_version
;
4086 /* Find a candidate among the list of pre-declared architectures. */
4087 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4089 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4091 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4092 == usr_cmd_cris_version
)
4093 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4094 == usr_cmd_cris_mode
)
4095 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4096 == usr_cmd_cris_dwarf2_cfi
))
4097 return arches
->gdbarch
;
4100 /* No matching architecture was found. Create a new one. */
4101 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4102 gdbarch
= gdbarch_alloc (&info
, tdep
);
4104 tdep
->cris_version
= usr_cmd_cris_version
;
4105 tdep
->cris_mode
= usr_cmd_cris_mode
;
4106 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4108 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4109 switch (info
.byte_order
)
4111 case BFD_ENDIAN_LITTLE
:
4115 case BFD_ENDIAN_BIG
:
4116 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: big endian byte order in info"));
4120 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: unknown byte order in info"));
4123 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4124 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
4125 cris_reg_struct_has_addr
);
4126 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
4128 set_gdbarch_sp_regnum (gdbarch
, 14);
4130 /* Length of ordinary registers used in push_word and a few other
4131 places. register_size() is the real way to know how big a
4134 set_gdbarch_double_bit (gdbarch
, 64);
4135 /* The default definition of a long double is 2 * gdbarch_double_bit,
4136 which means we have to set this explicitly. */
4137 set_gdbarch_long_double_bit (gdbarch
, 64);
4139 /* The total amount of space needed to store (in an array called registers)
4140 GDB's copy of the machine's register state. Note: We can not use
4141 cris_register_size at this point, since it relies on current_gdbarch
4143 switch (tdep
->cris_version
)
4151 /* Old versions; not supported. */
4152 internal_error (__FILE__
, __LINE__
,
4153 _("cris_gdbarch_init: unsupported CRIS version"));
4158 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4159 P7 (32 bits), and P15 (32 bits) have been implemented. */
4160 set_gdbarch_pc_regnum (gdbarch
, 15);
4161 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4162 /* There are 32 registers (some of which may not be implemented). */
4163 set_gdbarch_num_regs (gdbarch
, 32);
4164 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4165 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4166 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4168 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4172 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4173 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4174 and pseudo-register PC (32 bits). */
4175 set_gdbarch_pc_regnum (gdbarch
, 32);
4176 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4177 /* 32 registers + pseudo-register PC + 16 support registers. */
4178 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4179 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4181 set_gdbarch_cannot_store_register
4182 (gdbarch
, crisv32_cannot_store_register
);
4183 set_gdbarch_cannot_fetch_register
4184 (gdbarch
, crisv32_cannot_fetch_register
);
4186 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4188 set_gdbarch_single_step_through_delay
4189 (gdbarch
, crisv32_single_step_through_delay
);
4194 internal_error (__FILE__
, __LINE__
,
4195 _("cris_gdbarch_init: unknown CRIS version"));
4198 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4199 have the same ABI). */
4200 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4201 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4202 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4203 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4205 /* The stack grows downward. */
4206 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4208 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4210 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4211 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4212 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
4214 if (tdep
->cris_dwarf2_cfi
== 1)
4216 /* Hook in the Dwarf-2 frame sniffer. */
4217 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4218 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4219 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
4222 if (tdep
->cris_mode
!= cris_mode_guru
)
4224 frame_unwind_append_sniffer (gdbarch
, cris_sigtramp_frame_sniffer
);
4227 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
4228 frame_base_set_default (gdbarch
, &cris_frame_base
);
4230 set_solib_svr4_fetch_link_map_offsets
4231 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
4233 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4234 disassembler, even when there is no BFD. Does something like
4235 "gdb; target remote; disassmeble *0x123" work? */
4236 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);