1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
29 #include "dwarf2-frame.h"
37 #include "opcode/cris.h"
38 #include "arch-utils.h"
40 #include "gdb_assert.h"
42 /* To get entry_point_address. */
45 #include "solib.h" /* Support for shared libraries. */
46 #include "solib-svr4.h"
47 #include "gdb_string.h"
52 /* There are no floating point registers. Used in gdbserver low-linux.c. */
55 /* There are 16 general registers. */
58 /* There are 16 special registers. */
61 /* CRISv32 has a pseudo PC register, not noted here. */
63 /* CRISv32 has 16 support registers. */
67 /* Register numbers of various important registers.
68 CRIS_FP_REGNUM Contains address of executing stack frame.
69 STR_REGNUM Contains the address of structure return values.
70 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
71 ARG1_REGNUM Contains the first parameter to a function.
72 ARG2_REGNUM Contains the second parameter to a function.
73 ARG3_REGNUM Contains the third parameter to a function.
74 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75 gdbarch_sp_regnum Contains address of top of stack.
76 gdbarch_pc_regnum Contains address of next instruction.
77 SRP_REGNUM Subroutine return pointer register.
78 BRP_REGNUM Breakpoint return pointer register. */
82 /* Enums with respect to the general registers, valid for all
83 CRIS versions. The frame pointer is always in R8. */
85 /* ABI related registers. */
93 /* Registers which happen to be common. */
98 /* CRISv10 et. al. specific registers. */
110 /* CRISv32 specific registers. */
123 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
125 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
145 extern const struct cris_spec_reg cris_spec_regs
[];
147 /* CRIS version, set via the user command 'set cris-version'. Affects
148 register names and sizes. */
149 static int usr_cmd_cris_version
;
151 /* Indicates whether to trust the above variable. */
152 static int usr_cmd_cris_version_valid
= 0;
154 static const char cris_mode_normal
[] = "normal";
155 static const char cris_mode_guru
[] = "guru";
156 static const char *cris_modes
[] = {
162 /* CRIS mode, set via the user command 'set cris-mode'. Affects
163 type of break instruction among other things. */
164 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
166 /* Whether to make use of Dwarf-2 CFI (default on). */
167 static int usr_cmd_cris_dwarf2_cfi
= 1;
169 /* CRIS architecture specific information. */
173 const char *cris_mode
;
177 /* Functions for accessing target dependent data. */
182 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
188 return (gdbarch_tdep (current_gdbarch
)->cris_mode
);
191 /* Sigtramp identification code copied from i386-linux-tdep.c. */
193 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
194 #define SIGTRAMP_OFFSET0 0
195 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
196 #define SIGTRAMP_OFFSET1 4
198 static const unsigned short sigtramp_code
[] =
200 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
201 SIGTRAMP_INSN1
/* break 13 */
204 #define SIGTRAMP_LEN (sizeof sigtramp_code)
206 /* Note: same length as normal sigtramp code. */
208 static const unsigned short rt_sigtramp_code
[] =
210 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
211 SIGTRAMP_INSN1
/* break 13 */
214 /* If PC is in a sigtramp routine, return the address of the start of
215 the routine. Otherwise, return 0. */
218 cris_sigtramp_start (struct frame_info
*this_frame
)
220 CORE_ADDR pc
= get_frame_pc (this_frame
);
221 gdb_byte buf
[SIGTRAMP_LEN
];
223 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
226 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
228 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
231 pc
-= SIGTRAMP_OFFSET1
;
232 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
236 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
242 /* If PC is in a RT sigtramp routine, return the address of the start of
243 the routine. Otherwise, return 0. */
246 cris_rt_sigtramp_start (struct frame_info
*this_frame
)
248 CORE_ADDR pc
= get_frame_pc (this_frame
);
249 gdb_byte buf
[SIGTRAMP_LEN
];
251 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
254 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
256 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
259 pc
-= SIGTRAMP_OFFSET1
;
260 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
264 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
270 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
271 return the address of the associated sigcontext structure. */
274 cris_sigcontext_addr (struct frame_info
*this_frame
)
280 get_frame_register (this_frame
,
281 gdbarch_sp_regnum (get_frame_arch (this_frame
)), buf
);
282 sp
= extract_unsigned_integer (buf
, 4);
284 /* Look for normal sigtramp frame first. */
285 pc
= cris_sigtramp_start (this_frame
);
288 /* struct signal_frame (arch/cris/kernel/signal.c) contains
289 struct sigcontext as its first member, meaning the SP points to
294 pc
= cris_rt_sigtramp_start (this_frame
);
297 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
298 a struct ucontext, which in turn contains a struct sigcontext.
300 4 + 4 + 128 to struct ucontext, then
301 4 + 4 + 12 to struct sigcontext. */
305 error (_("Couldn't recognize signal trampoline."));
309 struct cris_unwind_cache
311 /* The previous frame's inner most stack address. Used as this
312 frame ID's stack_addr. */
314 /* The frame's base, optionally used by the high-level debug info. */
317 /* How far the SP and r8 (FP) have been offset from the start of
318 the stack frame (as defined by the previous frame's stack
324 /* From old frame_extra_info struct. */
328 /* Table indicating the location of each and every register. */
329 struct trad_frame_saved_reg
*saved_regs
;
332 static struct cris_unwind_cache
*
333 cris_sigtramp_frame_unwind_cache (struct frame_info
*this_frame
,
336 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
338 struct cris_unwind_cache
*info
;
346 return (*this_cache
);
348 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
349 (*this_cache
) = info
;
350 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
352 /* Zero all fields. */
358 info
->uses_frame
= 0;
360 info
->leaf_function
= 0;
362 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
363 info
->base
= extract_unsigned_integer (buf
, 4);
365 addr
= cris_sigcontext_addr (this_frame
);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep
->cris_version
== 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i
= 0; i
<= 13; i
++)
379 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
381 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
382 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
383 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
388 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
389 = info
->saved_regs
[IRP_REGNUM
];
390 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
= addr
+ (24 * 4);
395 /* R0 to R13 are stored in order at offset (1 * 4) in
397 for (i
= 0; i
<= 13; i
++)
398 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
400 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
401 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
402 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
403 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
404 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
405 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
406 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
407 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
408 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
410 /* FIXME: If ERP is in a delay slot at this point then the PC will
411 be wrong at this point. This problem manifests itself in the
412 sigaltstack.exp test case, which occasionally generates FAILs when
413 the signal is received while in a delay slot.
415 This could be solved by a couple of read_memory_unsigned_integer and a
416 trad_frame_set_value. */
417 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
418 = info
->saved_regs
[ERP_REGNUM
];
420 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
428 cris_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
429 struct frame_id
*this_id
)
431 struct cris_unwind_cache
*cache
=
432 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
433 (*this_id
) = frame_id_build (cache
->base
, get_frame_pc (this_frame
));
436 /* Forward declaration. */
438 static struct value
*cris_frame_prev_register (struct frame_info
*this_frame
,
439 void **this_cache
, int regnum
);
440 static struct value
*
441 cris_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
442 void **this_cache
, int regnum
)
444 /* Make sure we've initialized the cache. */
445 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
446 return cris_frame_prev_register (this_frame
, this_cache
, regnum
);
450 cris_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
451 struct frame_info
*this_frame
,
454 if (cris_sigtramp_start (this_frame
)
455 || cris_rt_sigtramp_start (this_frame
))
461 static const struct frame_unwind cris_sigtramp_frame_unwind
=
464 cris_sigtramp_frame_this_id
,
465 cris_sigtramp_frame_prev_register
,
467 cris_sigtramp_frame_sniffer
471 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
472 struct frame_info
*this_frame
)
474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
478 if (cris_mode () == cris_mode_guru
)
479 erp
= get_frame_register_unsigned (this_frame
, NRP_REGNUM
);
481 erp
= get_frame_register_unsigned (this_frame
, ERP_REGNUM
);
485 /* In delay slot - check if there's a breakpoint at the preceding
487 if (breakpoint_here_p (erp
& ~0x1))
493 /* Hardware watchpoint support. */
495 /* We support 6 hardware data watchpoints, but cannot trigger on execute
496 (any combination of read/write is fine). */
499 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
501 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
503 /* No bookkeeping is done here; it is handled by the remote debug agent. */
505 if (tdep
->cris_version
!= 32)
508 /* CRISv32: Six data watchpoints, one for instructions. */
509 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
510 || type
== bp_hardware_watchpoint
) && count
<= 6)
511 || (type
== bp_hardware_breakpoint
&& count
<= 1));
514 /* The CRISv32 hardware data watchpoints work by specifying ranges,
515 which have no alignment or length restrictions. */
518 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
523 /* If the inferior has some watchpoint that triggered, return the
524 address associated with that watchpoint. Otherwise, return
528 cris_stopped_data_address (void)
531 eda
= get_frame_register_unsigned (get_current_frame (), EDA_REGNUM
);
535 /* The instruction environment needed to find single-step breakpoints. */
538 struct instruction_environment
540 unsigned long reg
[NUM_GENREGS
];
541 unsigned long preg
[NUM_SPECREGS
];
542 unsigned long branch_break_address
;
543 unsigned long delay_slot_pc
;
544 unsigned long prefix_value
;
549 int delay_slot_pc_active
;
551 int disable_interrupt
;
554 /* Machine-dependencies in CRIS for opcodes. */
556 /* Instruction sizes. */
557 enum cris_instruction_sizes
564 /* Addressing modes. */
565 enum cris_addressing_modes
572 /* Prefix addressing modes. */
573 enum cris_prefix_addressing_modes
575 PREFIX_INDEX_MODE
= 2,
576 PREFIX_ASSIGN_MODE
= 3,
578 /* Handle immediate byte offset addressing mode prefix format. */
579 PREFIX_OFFSET_MODE
= 2
582 /* Masks for opcodes. */
583 enum cris_opcode_masks
585 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
586 SIGNED_EXTEND_BIT_MASK
= 0x2,
587 SIGNED_BYTE_MASK
= 0x80,
588 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
589 SIGNED_WORD_MASK
= 0x8000,
590 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
591 SIGNED_DWORD_MASK
= 0x80000000,
592 SIGNED_QUICK_VALUE_MASK
= 0x20,
593 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
596 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
604 cris_get_operand2 (unsigned short insn
)
606 return ((insn
& 0xF000) >> 12);
610 cris_get_mode (unsigned short insn
)
612 return ((insn
& 0x0C00) >> 10);
616 cris_get_opcode (unsigned short insn
)
618 return ((insn
& 0x03C0) >> 6);
622 cris_get_size (unsigned short insn
)
624 return ((insn
& 0x0030) >> 4);
628 cris_get_operand1 (unsigned short insn
)
630 return (insn
& 0x000F);
633 /* Additional functions in order to handle opcodes. */
636 cris_get_quick_value (unsigned short insn
)
638 return (insn
& 0x003F);
642 cris_get_bdap_quick_offset (unsigned short insn
)
644 return (insn
& 0x00FF);
648 cris_get_branch_short_offset (unsigned short insn
)
650 return (insn
& 0x00FF);
654 cris_get_asr_shift_steps (unsigned long value
)
656 return (value
& 0x3F);
660 cris_get_clear_size (unsigned short insn
)
662 return ((insn
) & 0xC000);
666 cris_is_signed_extend_bit_on (unsigned short insn
)
668 return (((insn
) & 0x20) == 0x20);
672 cris_is_xflag_bit_on (unsigned short insn
)
674 return (((insn
) & 0x1000) == 0x1000);
678 cris_set_size_to_dword (unsigned short *insn
)
685 cris_get_signed_offset (unsigned short insn
)
687 return ((signed char) (insn
& 0x00FF));
690 /* Calls an op function given the op-type, working on the insn and the
692 static void cris_gdb_func (struct gdbarch
*, enum cris_op_type
, unsigned short,
695 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
696 struct gdbarch_list
*);
698 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
700 static void set_cris_version (char *ignore_args
, int from_tty
,
701 struct cmd_list_element
*c
);
703 static void set_cris_mode (char *ignore_args
, int from_tty
,
704 struct cmd_list_element
*c
);
706 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
707 struct cmd_list_element
*c
);
709 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
710 struct frame_info
*this_frame
,
711 struct cris_unwind_cache
*info
);
713 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
714 struct frame_info
*this_frame
,
715 struct cris_unwind_cache
*info
);
717 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
718 struct frame_info
*next_frame
);
720 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
721 struct frame_info
*next_frame
);
723 /* When arguments must be pushed onto the stack, they go on in reverse
724 order. The below implements a FILO (stack) to do this.
725 Copied from d10v-tdep.c. */
730 struct stack_item
*prev
;
734 static struct stack_item
*
735 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
737 struct stack_item
*si
;
738 si
= xmalloc (sizeof (struct stack_item
));
739 si
->data
= xmalloc (len
);
742 memcpy (si
->data
, contents
, len
);
746 static struct stack_item
*
747 pop_stack_item (struct stack_item
*si
)
749 struct stack_item
*dead
= si
;
756 /* Put here the code to store, into fi->saved_regs, the addresses of
757 the saved registers of frame described by FRAME_INFO. This
758 includes special registers such as pc and fp saved in special ways
759 in the stack frame. sp is even more special: the address we return
760 for it IS the sp for the next frame. */
762 struct cris_unwind_cache
*
763 cris_frame_unwind_cache (struct frame_info
*this_frame
,
764 void **this_prologue_cache
)
767 struct cris_unwind_cache
*info
;
770 if ((*this_prologue_cache
))
771 return (*this_prologue_cache
);
773 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
774 (*this_prologue_cache
) = info
;
775 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
777 /* Zero all fields. */
783 info
->uses_frame
= 0;
785 info
->leaf_function
= 0;
787 /* Prologue analysis does the rest... */
788 if (cris_version () == 32)
789 crisv32_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
791 cris_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
796 /* Given a GDB frame, determine the address of the calling function's
797 frame. This will be used to create a new GDB frame struct. */
800 cris_frame_this_id (struct frame_info
*this_frame
,
801 void **this_prologue_cache
,
802 struct frame_id
*this_id
)
804 struct cris_unwind_cache
*info
805 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
810 /* The FUNC is easy. */
811 func
= get_frame_func (this_frame
);
813 /* Hopefully the prologue analysis either correctly determined the
814 frame's base (which is the SP from the previous frame), or set
815 that base to "NULL". */
816 base
= info
->prev_sp
;
820 id
= frame_id_build (base
, func
);
825 static struct value
*
826 cris_frame_prev_register (struct frame_info
*this_frame
,
827 void **this_prologue_cache
, int regnum
)
829 struct cris_unwind_cache
*info
830 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
831 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
834 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
835 frame. The frame ID's base needs to match the TOS value saved by
836 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
838 static struct frame_id
839 cris_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
842 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
843 return frame_id_build (sp
, get_frame_pc (this_frame
));
847 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
849 /* Align to the size of an instruction (so that they can safely be
850 pushed onto the stack). */
855 cris_push_dummy_code (struct gdbarch
*gdbarch
,
856 CORE_ADDR sp
, CORE_ADDR funaddr
,
857 struct value
**args
, int nargs
,
858 struct type
*value_type
,
859 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
860 struct regcache
*regcache
)
862 /* Allocate space sufficient for a breakpoint. */
864 /* Store the address of that breakpoint */
866 /* CRIS always starts the call at the callee's entry point. */
872 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
873 struct regcache
*regcache
, CORE_ADDR bp_addr
,
874 int nargs
, struct value
**args
, CORE_ADDR sp
,
875 int struct_return
, CORE_ADDR struct_addr
)
884 /* The function's arguments and memory allocated by gdb for the arguments to
885 point at reside in separate areas on the stack.
886 Both frame pointers grow toward higher addresses. */
890 struct stack_item
*si
= NULL
;
892 /* Push the return address. */
893 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
895 /* Are we returning a value using a structure return or a normal value
896 return? struct_addr is the address of the reserved space for the return
897 structure to be written on the stack. */
900 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
903 /* Now load as many as possible of the first arguments into registers,
904 and push the rest onto the stack. */
905 argreg
= ARG1_REGNUM
;
908 for (argnum
= 0; argnum
< nargs
; argnum
++)
915 len
= TYPE_LENGTH (value_type (args
[argnum
]));
916 val
= (char *) value_contents (args
[argnum
]);
918 /* How may registers worth of storage do we need for this argument? */
919 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
921 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
923 /* Data passed by value. Fits in available register(s). */
924 for (i
= 0; i
< reg_demand
; i
++)
926 regcache_cooked_write (regcache
, argreg
, val
);
931 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
933 /* Data passed by value. Does not fit in available register(s).
934 Use the register(s) first, then the stack. */
935 for (i
= 0; i
< reg_demand
; i
++)
937 if (argreg
<= ARG4_REGNUM
)
939 regcache_cooked_write (regcache
, argreg
, val
);
945 /* Push item for later so that pushed arguments
946 come in the right order. */
947 si
= push_stack_item (si
, val
, 4);
952 else if (len
> (2 * 4))
954 /* Data passed by reference. Push copy of data onto stack
955 and pass pointer to this copy as argument. */
956 sp
= (sp
- len
) & ~3;
957 write_memory (sp
, val
, len
);
959 if (argreg
<= ARG4_REGNUM
)
961 regcache_cooked_write_unsigned (regcache
, argreg
, sp
);
967 store_unsigned_integer (buf
, 4, sp
);
968 si
= push_stack_item (si
, buf
, 4);
973 /* Data passed by value. No available registers. Put it on
975 si
= push_stack_item (si
, val
, len
);
981 /* fp_arg must be word-aligned (i.e., don't += len) to match
982 the function prologue. */
983 sp
= (sp
- si
->len
) & ~3;
984 write_memory (sp
, si
->data
, si
->len
);
985 si
= pop_stack_item (si
);
988 /* Finally, update the SP register. */
989 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
994 static const struct frame_unwind cris_frame_unwind
=
998 cris_frame_prev_register
,
1000 default_frame_sniffer
1004 cris_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1006 struct cris_unwind_cache
*info
1007 = cris_frame_unwind_cache (this_frame
, this_cache
);
1011 static const struct frame_base cris_frame_base
=
1014 cris_frame_base_address
,
1015 cris_frame_base_address
,
1016 cris_frame_base_address
1019 /* Frames information. The definition of the struct frame_info is
1023 enum frame_type type;
1027 If the compilation option -fno-omit-frame-pointer is present the
1028 variable frame will be set to the content of R8 which is the frame
1031 The variable pc contains the address where execution is performed
1032 in the present frame. The innermost frame contains the current content
1033 of the register PC. All other frames contain the content of the
1034 register PC in the next frame.
1036 The variable `type' indicates the frame's type: normal, SIGTRAMP
1037 (associated with a signal handler), dummy (associated with a dummy
1040 The variable return_pc contains the address where execution should be
1041 resumed when the present frame has finished, the return address.
1043 The variable leaf_function is 1 if the return address is in the register
1044 SRP, and 0 if it is on the stack.
1046 Prologue instructions C-code.
1047 The prologue may consist of (-fno-omit-frame-pointer)
1051 move.d sp,r8 move.d sp,r8
1053 movem rY,[sp] movem rY,[sp]
1054 move.S rZ,[r8-U] move.S rZ,[r8-U]
1056 where 1 is a non-terminal function, and 2 is a leaf-function.
1058 Note that this assumption is extremely brittle, and will break at the
1059 slightest change in GCC's prologue.
1061 If local variables are declared or register contents are saved on stack
1062 the subq-instruction will be present with X as the number of bytes
1063 needed for storage. The reshuffle with respect to r8 may be performed
1064 with any size S (b, w, d) and any of the general registers Z={0..13}.
1065 The offset U should be representable by a signed 8-bit value in all cases.
1066 Thus, the prefix word is assumed to be immediate byte offset mode followed
1067 by another word containing the instruction.
1076 Prologue instructions C++-code.
1077 Case 1) and 2) in the C-code may be followed by
1079 move.d r10,rS ; this
1083 move.S [r8+U],rZ ; P4
1085 if any of the call parameters are stored. The host expects these
1086 instructions to be executed in order to get the call parameters right. */
1088 /* Examine the prologue of a function. The variable ip is the address of
1089 the first instruction of the prologue. The variable limit is the address
1090 of the first instruction after the prologue. The variable fi contains the
1091 information in struct frame_info. The variable frameless_p controls whether
1092 the entire prologue is examined (0) or just enough instructions to
1093 determine that it is a prologue (1). */
1096 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1097 struct cris_unwind_cache
*info
)
1099 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1100 /* Present instruction. */
1101 unsigned short insn
;
1103 /* Next instruction, lookahead. */
1104 unsigned short insn_next
;
1107 /* Is there a push fp? */
1110 /* Number of byte on stack used for local variables and movem. */
1113 /* Highest register number in a movem. */
1116 /* move.d r<source_register>,rS */
1117 short source_register
;
1122 /* This frame is with respect to a leaf until a push srp is found. */
1125 info
->leaf_function
= 1;
1128 /* Assume nothing on stack. */
1132 /* If we were called without a this_frame, that means we were called
1133 from cris_skip_prologue which already tried to find the end of the
1134 prologue through the symbol information. 64 instructions past current
1135 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1136 limit
= this_frame
? get_frame_pc (this_frame
) : pc
+ 64;
1138 /* Find the prologue instructions. */
1139 while (pc
> 0 && pc
< limit
)
1141 insn
= read_memory_unsigned_integer (pc
, 2);
1145 /* push <reg> 32 bit instruction */
1146 insn_next
= read_memory_unsigned_integer (pc
, 2);
1148 regno
= cris_get_operand2 (insn_next
);
1151 info
->sp_offset
+= 4;
1153 /* This check, meant to recognize srp, used to be regno ==
1154 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1155 if (insn_next
== 0xBE7E)
1159 info
->leaf_function
= 0;
1162 else if (insn_next
== 0x8FEE)
1167 info
->r8_offset
= info
->sp_offset
;
1171 else if (insn
== 0x866E)
1176 info
->uses_frame
= 1;
1180 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1181 && cris_get_mode (insn
) == 0x0000
1182 && cris_get_opcode (insn
) == 0x000A)
1187 info
->sp_offset
+= cris_get_quick_value (insn
);
1190 else if (cris_get_mode (insn
) == 0x0002
1191 && cris_get_opcode (insn
) == 0x000F
1192 && cris_get_size (insn
) == 0x0003
1193 && cris_get_operand1 (insn
) == gdbarch_sp_regnum (gdbarch
))
1195 /* movem r<regsave>,[sp] */
1196 regsave
= cris_get_operand2 (insn
);
1198 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1199 && ((insn
& 0x0F00) >> 8) == 0x0001
1200 && (cris_get_signed_offset (insn
) < 0))
1202 /* Immediate byte offset addressing prefix word with sp as base
1203 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1204 is between 64 and 128.
1205 movem r<regsave>,[sp=sp-<val>] */
1208 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1210 insn_next
= read_memory_unsigned_integer (pc
, 2);
1212 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1213 && cris_get_opcode (insn_next
) == 0x000F
1214 && cris_get_size (insn_next
) == 0x0003
1215 && cris_get_operand1 (insn_next
) == gdbarch_sp_regnum
1218 regsave
= cris_get_operand2 (insn_next
);
1222 /* The prologue ended before the limit was reached. */
1227 else if (cris_get_mode (insn
) == 0x0001
1228 && cris_get_opcode (insn
) == 0x0009
1229 && cris_get_size (insn
) == 0x0002)
1231 /* move.d r<10..13>,r<0..15> */
1232 source_register
= cris_get_operand1 (insn
);
1234 /* FIXME? In the glibc solibs, the prologue might contain something
1235 like (this example taken from relocate_doit):
1237 sub.d 0xfffef426,$r0
1238 which isn't covered by the source_register check below. Question
1239 is whether to add a check for this combo, or make better use of
1240 the limit variable instead. */
1241 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1243 /* The prologue ended before the limit was reached. */
1248 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1249 /* The size is a fixed-size. */
1250 && ((insn
& 0x0F00) >> 8) == 0x0001
1251 /* A negative offset. */
1252 && (cris_get_signed_offset (insn
) < 0))
1254 /* move.S rZ,[r8-U] (?) */
1255 insn_next
= read_memory_unsigned_integer (pc
, 2);
1257 regno
= cris_get_operand2 (insn_next
);
1258 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1259 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1260 && cris_get_opcode (insn_next
) == 0x000F)
1262 /* move.S rZ,[r8-U] */
1267 /* The prologue ended before the limit was reached. */
1272 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1273 /* The size is a fixed-size. */
1274 && ((insn
& 0x0F00) >> 8) == 0x0001
1275 /* A positive offset. */
1276 && (cris_get_signed_offset (insn
) > 0))
1278 /* move.S [r8+U],rZ (?) */
1279 insn_next
= read_memory_unsigned_integer (pc
, 2);
1281 regno
= cris_get_operand2 (insn_next
);
1282 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1283 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1284 && cris_get_opcode (insn_next
) == 0x0009
1285 && cris_get_operand1 (insn_next
) == regno
)
1287 /* move.S [r8+U],rZ */
1292 /* The prologue ended before the limit was reached. */
1299 /* The prologue ended before the limit was reached. */
1305 /* We only want to know the end of the prologue when this_frame and info
1306 are NULL (called from cris_skip_prologue i.e.). */
1307 if (this_frame
== NULL
&& info
== NULL
)
1312 info
->size
= info
->sp_offset
;
1314 /* Compute the previous frame's stack pointer (which is also the
1315 frame's ID's stack address), and this frame's base pointer. */
1316 if (info
->uses_frame
)
1319 /* The SP was moved to the FP. This indicates that a new frame
1320 was created. Get THIS frame's FP value by unwinding it from
1322 this_base
= get_frame_register_unsigned (this_frame
, CRIS_FP_REGNUM
);
1323 info
->base
= this_base
;
1324 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1326 /* The FP points at the last saved register. Adjust the FP back
1327 to before the first saved register giving the SP. */
1328 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1333 /* Assume that the FP is this frame's SP but with that pushed
1334 stack space added back. */
1335 this_base
= get_frame_register_unsigned (this_frame
,
1336 gdbarch_sp_regnum (gdbarch
));
1337 info
->base
= this_base
;
1338 info
->prev_sp
= info
->base
+ info
->size
;
1341 /* Calculate the addresses for the saved registers on the stack. */
1342 /* FIXME: The address calculation should really be done on the fly while
1343 we're analyzing the prologue (we only hold one regsave value as it is
1345 val
= info
->sp_offset
;
1347 for (regno
= regsave
; regno
>= 0; regno
--)
1349 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1353 /* The previous frame's SP needed to be computed. Save the computed
1355 trad_frame_set_value (info
->saved_regs
,
1356 gdbarch_sp_regnum (gdbarch
), info
->prev_sp
);
1358 if (!info
->leaf_function
)
1360 /* SRP saved on the stack. But where? */
1361 if (info
->r8_offset
== 0)
1363 /* R8 not pushed yet. */
1364 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1368 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1369 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1373 /* The PC is found in SRP (the actual register or located on the stack). */
1374 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1375 = info
->saved_regs
[SRP_REGNUM
];
1381 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1382 struct cris_unwind_cache
*info
)
1384 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1387 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1388 meant to be a full-fledged prologue scanner. It is only needed for
1389 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1391 * PLT stubs (library calls)
1393 * signal trampolines
1395 For those cases, it is assumed that there is no actual prologue; that
1396 the stack pointer is not adjusted, and (as a consequence) the return
1397 address is not pushed onto the stack. */
1399 /* We only want to know the end of the prologue when this_frame and info
1400 are NULL (called from cris_skip_prologue i.e.). */
1401 if (this_frame
== NULL
&& info
== NULL
)
1406 /* The SP is assumed to be unaltered. */
1407 this_base
= get_frame_register_unsigned (this_frame
,
1408 gdbarch_sp_regnum (gdbarch
));
1409 info
->base
= this_base
;
1410 info
->prev_sp
= this_base
;
1412 /* The PC is assumed to be found in SRP. */
1413 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1414 = info
->saved_regs
[SRP_REGNUM
];
1419 /* Advance pc beyond any function entry prologue instructions at pc
1420 to reach some "real" code. */
1422 /* Given a PC value corresponding to the start of a function, return the PC
1423 of the first instruction after the function prologue. */
1426 cris_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1428 CORE_ADDR func_addr
, func_end
;
1429 struct symtab_and_line sal
;
1430 CORE_ADDR pc_after_prologue
;
1432 /* If we have line debugging information, then the end of the prologue
1433 should the first assembly instruction of the first source line. */
1434 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1436 sal
= find_pc_line (func_addr
, 0);
1437 if (sal
.end
> 0 && sal
.end
< func_end
)
1441 if (cris_version () == 32)
1442 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1444 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1446 return pc_after_prologue
;
1450 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1453 pc
= frame_unwind_register_unsigned (next_frame
,
1454 gdbarch_pc_regnum (gdbarch
));
1459 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1462 sp
= frame_unwind_register_unsigned (next_frame
,
1463 gdbarch_sp_regnum (gdbarch
));
1467 /* Use the program counter to determine the contents and size of a breakpoint
1468 instruction. It returns a pointer to a string of bytes that encode a
1469 breakpoint instruction, stores the length of the string to *lenptr, and
1470 adjusts pcptr (if necessary) to point to the actual memory location where
1471 the breakpoint should be inserted. */
1473 static const unsigned char *
1474 cris_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
1476 static unsigned char break8_insn
[] = {0x38, 0xe9};
1477 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1480 if (cris_mode () == cris_mode_guru
)
1481 return break15_insn
;
1486 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1490 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1492 int version
= cris_version ();
1494 switch (spec_reg
.applicable_version
)
1496 case cris_ver_version_all
:
1498 case cris_ver_warning
:
1499 /* Indeterminate/obsolete. */
1502 return (version
>= 0 && version
<= 3);
1504 return (version
>= 3);
1506 return (version
== 8 || version
== 9);
1508 return (version
>= 8);
1509 case cris_ver_v0_10
:
1510 return (version
>= 0 && version
<= 10);
1511 case cris_ver_v3_10
:
1512 return (version
>= 3 && version
<= 10);
1513 case cris_ver_v8_10
:
1514 return (version
>= 8 && version
<= 10);
1516 return (version
== 10);
1518 return (version
>= 10);
1520 return (version
>= 32);
1522 /* Invalid cris version. */
1527 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1528 register, -1 for an invalid register. */
1531 cris_register_size (struct gdbarch
*gdbarch
, int regno
)
1533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1537 if (regno
>= 0 && regno
< NUM_GENREGS
)
1539 /* General registers (R0 - R15) are 32 bits. */
1542 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1544 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1545 Adjust regno accordingly. */
1546 spec_regno
= regno
- NUM_GENREGS
;
1548 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1550 if (cris_spec_regs
[i
].number
== spec_regno
1551 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1552 /* Go with the first applicable register. */
1553 return cris_spec_regs
[i
].reg_size
;
1555 /* Special register not applicable to this CRIS version. */
1558 else if (regno
>= gdbarch_pc_regnum (gdbarch
)
1559 && regno
< gdbarch_num_regs (gdbarch
))
1561 /* This will apply to CRISv32 only where there are additional registers
1562 after the special registers (pseudo PC and support registers). */
1570 /* Nonzero if regno should not be fetched from the target. This is the case
1571 for unimplemented (size 0) and non-existant registers. */
1574 cris_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1576 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1577 || (cris_register_size (gdbarch
, regno
) == 0));
1580 /* Nonzero if regno should not be written to the target, for various
1584 cris_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1586 /* There are three kinds of registers we refuse to write to.
1587 1. Those that not implemented.
1588 2. Those that are read-only (depends on the processor mode).
1589 3. Those registers to which a write has no effect.
1593 || regno
>= gdbarch_num_regs (gdbarch
)
1594 || cris_register_size (gdbarch
, regno
) == 0)
1595 /* Not implemented. */
1598 else if (regno
== VR_REGNUM
)
1602 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1603 /* Writing has no effect. */
1606 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1607 agent decide whether they are writable. */
1612 /* Nonzero if regno should not be fetched from the target. This is the case
1613 for unimplemented (size 0) and non-existant registers. */
1616 crisv32_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1618 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1619 || (cris_register_size (gdbarch
, regno
) == 0));
1622 /* Nonzero if regno should not be written to the target, for various
1626 crisv32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1628 /* There are three kinds of registers we refuse to write to.
1629 1. Those that not implemented.
1630 2. Those that are read-only (depends on the processor mode).
1631 3. Those registers to which a write has no effect.
1635 || regno
>= gdbarch_num_regs (gdbarch
)
1636 || cris_register_size (gdbarch
, regno
) == 0)
1637 /* Not implemented. */
1640 else if (regno
== VR_REGNUM
)
1644 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1645 /* Writing has no effect. */
1648 /* Many special registers are read-only in user mode. Let the debug
1649 agent decide whether they are writable. */
1654 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1655 of data in register regno. */
1657 static struct type
*
1658 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1660 if (regno
== gdbarch_pc_regnum (gdbarch
))
1661 return builtin_type_void_func_ptr
;
1662 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1663 || regno
== CRIS_FP_REGNUM
)
1664 return builtin_type_void_data_ptr
;
1665 else if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1666 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1667 /* Note: R8 taken care of previous clause. */
1668 return builtin_type_uint32
;
1669 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1670 return builtin_type_uint16
;
1671 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1672 return builtin_type_uint8
;
1674 /* Invalid (unimplemented) register. */
1675 return builtin_type_int0
;
1678 static struct type
*
1679 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1681 if (regno
== gdbarch_pc_regnum (gdbarch
))
1682 return builtin_type_void_func_ptr
;
1683 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1684 || regno
== CRIS_FP_REGNUM
)
1685 return builtin_type_void_data_ptr
;
1686 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1687 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1688 || (regno
== PID_REGNUM
)
1689 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1690 /* Note: R8 and SP taken care of by previous clause. */
1691 return builtin_type_uint32
;
1692 else if (regno
== WZ_REGNUM
)
1693 return builtin_type_uint16
;
1694 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1695 return builtin_type_uint8
;
1698 /* Invalid (unimplemented) register. Should not happen as there are
1699 no unimplemented CRISv32 registers. */
1700 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1701 return builtin_type_int0
;
1705 /* Stores a function return value of type type, where valbuf is the address
1706 of the value to be stored. */
1708 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1711 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1715 int len
= TYPE_LENGTH (type
);
1719 /* Put the return value in R10. */
1720 val
= extract_unsigned_integer (valbuf
, len
);
1721 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1725 /* Put the return value in R10 and R11. */
1726 val
= extract_unsigned_integer (valbuf
, 4);
1727 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1728 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1729 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1732 error (_("cris_store_return_value: type length too large."));
1735 /* Return the name of register regno as a string. Return NULL for an invalid or
1736 unimplemented register. */
1739 cris_special_register_name (int regno
)
1744 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1745 Adjust regno accordingly. */
1746 spec_regno
= regno
- NUM_GENREGS
;
1748 /* Assume nothing about the layout of the cris_spec_regs struct
1750 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1752 if (cris_spec_regs
[i
].number
== spec_regno
1753 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1754 /* Go with the first applicable register. */
1755 return cris_spec_regs
[i
].name
;
1757 /* Special register not applicable to this CRIS version. */
1762 cris_register_name (struct gdbarch
*gdbarch
, int regno
)
1764 static char *cris_genreg_names
[] =
1765 { "r0", "r1", "r2", "r3", \
1766 "r4", "r5", "r6", "r7", \
1767 "r8", "r9", "r10", "r11", \
1768 "r12", "r13", "sp", "pc" };
1770 if (regno
>= 0 && regno
< NUM_GENREGS
)
1772 /* General register. */
1773 return cris_genreg_names
[regno
];
1775 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (gdbarch
))
1777 return cris_special_register_name (regno
);
1781 /* Invalid register. */
1787 crisv32_register_name (struct gdbarch
*gdbarch
, int regno
)
1789 static char *crisv32_genreg_names
[] =
1790 { "r0", "r1", "r2", "r3", \
1791 "r4", "r5", "r6", "r7", \
1792 "r8", "r9", "r10", "r11", \
1793 "r12", "r13", "sp", "acr"
1796 static char *crisv32_sreg_names
[] =
1797 { "s0", "s1", "s2", "s3", \
1798 "s4", "s5", "s6", "s7", \
1799 "s8", "s9", "s10", "s11", \
1800 "s12", "s13", "s14", "s15"
1803 if (regno
>= 0 && regno
< NUM_GENREGS
)
1805 /* General register. */
1806 return crisv32_genreg_names
[regno
];
1808 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1810 return cris_special_register_name (regno
);
1812 else if (regno
== gdbarch_pc_regnum (gdbarch
))
1816 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1818 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1822 /* Invalid register. */
1827 /* Convert DWARF register number REG to the appropriate register
1828 number used by GDB. */
1831 cris_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1833 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1834 numbering, MOF is 18).
1835 Adapted from gcc/config/cris/cris.h. */
1836 static int cris_dwarf_regmap
[] = {
1848 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1849 regnum
= cris_dwarf_regmap
[reg
];
1852 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
1857 /* DWARF-2 frame support. */
1860 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1861 struct dwarf2_frame_state_reg
*reg
,
1862 struct frame_info
*this_frame
)
1864 /* The return address column. */
1865 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1866 reg
->how
= DWARF2_FRAME_REG_RA
;
1868 /* The call frame address. */
1869 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1870 reg
->how
= DWARF2_FRAME_REG_CFA
;
1873 /* Extract from an array regbuf containing the raw register state a function
1874 return value of type type, and copy that, in virtual format, into
1877 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1880 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1884 int len
= TYPE_LENGTH (type
);
1888 /* Get the return value from R10. */
1889 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1890 store_unsigned_integer (valbuf
, len
, val
);
1894 /* Get the return value from R10 and R11. */
1895 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1896 store_unsigned_integer (valbuf
, 4, val
);
1897 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1898 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1901 error (_("cris_extract_return_value: type length too large"));
1904 /* Handle the CRIS return value convention. */
1906 static enum return_value_convention
1907 cris_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1908 struct type
*type
, struct regcache
*regcache
,
1909 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1911 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1912 || TYPE_CODE (type
) == TYPE_CODE_UNION
1913 || TYPE_LENGTH (type
) > 8)
1914 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1915 goes on the stack. */
1916 return RETURN_VALUE_STRUCT_CONVENTION
;
1919 cris_extract_return_value (type
, regcache
, readbuf
);
1921 cris_store_return_value (type
, regcache
, writebuf
);
1923 return RETURN_VALUE_REGISTER_CONVENTION
;
1926 /* Calculates a value that measures how good inst_args constraints an
1927 instruction. It stems from cris_constraint, found in cris-dis.c. */
1930 constraint (unsigned int insn
, const signed char *inst_args
,
1931 inst_env_type
*inst_env
)
1936 const char *s
= inst_args
;
1942 if ((insn
& 0x30) == 0x30)
1947 /* A prefix operand. */
1948 if (inst_env
->prefix_found
)
1954 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1955 valid "push" size. In case of special register, it may be != 4. */
1956 if (inst_env
->prefix_found
)
1962 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1970 tmp
= (insn
>> 0xC) & 0xF;
1972 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1974 /* Since we match four bits, we will give a value of
1975 4 - 1 = 3 in a match. If there is a corresponding
1976 exact match of a special register in another pattern, it
1977 will get a value of 4, which will be higher. This should
1978 be correct in that an exact pattern would match better that
1980 Note that there is a reason for not returning zero; the
1981 pattern for "clear" is partly matched in the bit-pattern
1982 (the two lower bits must be zero), while the bit-pattern
1983 for a move from a special register is matched in the
1984 register constraint.
1985 This also means we will will have a race condition if
1986 there is a partly match in three bits in the bit pattern. */
1987 if (tmp
== cris_spec_regs
[i
].number
)
1994 if (cris_spec_regs
[i
].name
== NULL
)
2001 /* Returns the number of bits set in the variable value. */
2004 number_of_bits (unsigned int value
)
2006 int number_of_bits
= 0;
2010 number_of_bits
+= 1;
2011 value
&= (value
- 1);
2013 return number_of_bits
;
2016 /* Finds the address that should contain the single step breakpoint(s).
2017 It stems from code in cris-dis.c. */
2020 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
2023 int max_level_of_match
= -1;
2024 int max_matched
= -1;
2027 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
2029 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
2030 && ((cris_opcodes
[i
].lose
& insn
) == 0)
2031 /* Only CRISv10 instructions, please. */
2032 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
2034 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
2035 if (level_of_match
>= 0)
2038 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
2039 if (level_of_match
> max_level_of_match
)
2042 max_level_of_match
= level_of_match
;
2043 if (level_of_match
== 16)
2045 /* All bits matched, cannot find better. */
2055 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2056 actually an internal error. */
2059 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
2063 unsigned short insn
;
2064 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2066 /* Create a local register image and set the initial state. */
2067 for (i
= 0; i
< NUM_GENREGS
; i
++)
2070 (unsigned long) get_frame_register_unsigned (frame
, i
);
2072 offset
= NUM_GENREGS
;
2073 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2076 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2078 inst_env
->branch_found
= 0;
2079 inst_env
->slot_needed
= 0;
2080 inst_env
->delay_slot_pc_active
= 0;
2081 inst_env
->prefix_found
= 0;
2082 inst_env
->invalid
= 0;
2083 inst_env
->xflag_found
= 0;
2084 inst_env
->disable_interrupt
= 0;
2086 /* Look for a step target. */
2089 /* Read an instruction from the client. */
2090 insn
= read_memory_unsigned_integer
2091 (inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)], 2);
2093 /* If the instruction is not in a delay slot the new content of the
2094 PC is [PC] + 2. If the instruction is in a delay slot it is not
2095 that simple. Since a instruction in a delay slot cannot change
2096 the content of the PC, it does not matter what value PC will have.
2097 Just make sure it is a valid instruction. */
2098 if (!inst_env
->delay_slot_pc_active
)
2100 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)] += 2;
2104 inst_env
->delay_slot_pc_active
= 0;
2105 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)]
2106 = inst_env
->delay_slot_pc
;
2108 /* Analyse the present instruction. */
2109 i
= find_cris_op (insn
, inst_env
);
2112 inst_env
->invalid
= 1;
2116 cris_gdb_func (gdbarch
, cris_opcodes
[i
].op
, insn
, inst_env
);
2118 } while (!inst_env
->invalid
2119 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2120 || inst_env
->slot_needed
));
2124 /* There is no hardware single-step support. The function find_step_target
2125 digs through the opcodes in order to find all possible targets.
2126 Either one ordinary target or two targets for branches may be found. */
2129 cris_software_single_step (struct frame_info
*frame
)
2131 inst_env_type inst_env
;
2133 /* Analyse the present instruction environment and insert
2135 int status
= find_step_target (frame
, &inst_env
);
2138 /* Could not find a target. Things are likely to go downhill
2140 warning (_("CRIS software single step could not find a step target."));
2144 /* Insert at most two breakpoints. One for the next PC content
2145 and possibly another one for a branch, jump, etc. */
2147 (CORE_ADDR
) inst_env
.reg
[gdbarch_pc_regnum (get_frame_arch (frame
))];
2148 insert_single_step_breakpoint (next_pc
);
2149 if (inst_env
.branch_found
2150 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2152 CORE_ADDR branch_target_address
2153 = (CORE_ADDR
) inst_env
.branch_break_address
;
2154 insert_single_step_breakpoint (branch_target_address
);
2161 /* Calculates the prefix value for quick offset addressing mode. */
2164 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2166 /* It's invalid to be in a delay slot. You can't have a prefix to this
2167 instruction (not 100% sure). */
2168 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2170 inst_env
->invalid
= 1;
2174 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2175 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2177 /* A prefix doesn't change the xflag_found. But the rest of the flags
2179 inst_env
->slot_needed
= 0;
2180 inst_env
->prefix_found
= 1;
2183 /* Updates the autoincrement register. The size of the increment is derived
2184 from the size of the operation. The PC is always kept aligned on even
2188 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2190 if (size
== INST_BYTE_SIZE
)
2192 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2194 /* The PC must be word aligned, so increase the PC with one
2195 word even if the size is byte. */
2196 if (cris_get_operand1 (inst
) == REG_PC
)
2198 inst_env
->reg
[REG_PC
] += 1;
2201 else if (size
== INST_WORD_SIZE
)
2203 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2205 else if (size
== INST_DWORD_SIZE
)
2207 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2212 inst_env
->invalid
= 1;
2216 /* Just a forward declaration. */
2218 static unsigned long get_data_from_address (unsigned short *inst
,
2221 /* Calculates the prefix value for the general case of offset addressing
2225 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2230 /* It's invalid to be in a delay slot. */
2231 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2233 inst_env
->invalid
= 1;
2237 /* The calculation of prefix_value used to be after process_autoincrement,
2238 but that fails for an instruction such as jsr [$r0+12] which is encoded
2239 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2240 mustn't be incremented until we have read it and what it points at. */
2241 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2243 /* The offset is an indirection of the contents of the operand1 register. */
2244 inst_env
->prefix_value
+=
2245 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
2247 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2249 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2252 /* A prefix doesn't change the xflag_found. But the rest of the flags
2254 inst_env
->slot_needed
= 0;
2255 inst_env
->prefix_found
= 1;
2258 /* Calculates the prefix value for the index addressing mode. */
2261 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2263 /* It's invalid to be in a delay slot. I can't see that it's possible to
2264 have a prefix to this instruction. So I will treat this as invalid. */
2265 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2267 inst_env
->invalid
= 1;
2271 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2273 /* The offset is the operand2 value shifted the size of the instruction
2275 inst_env
->prefix_value
+=
2276 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2278 /* If the PC is operand1 (base) the address used is the address after
2279 the main instruction, i.e. address + 2 (the PC is already compensated
2280 for the prefix operation). */
2281 if (cris_get_operand1 (inst
) == REG_PC
)
2283 inst_env
->prefix_value
+= 2;
2286 /* A prefix doesn't change the xflag_found. But the rest of the flags
2288 inst_env
->slot_needed
= 0;
2289 inst_env
->xflag_found
= 0;
2290 inst_env
->prefix_found
= 1;
2293 /* Calculates the prefix value for the double indirect addressing mode. */
2296 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2301 /* It's invalid to be in a delay slot. */
2302 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2304 inst_env
->invalid
= 1;
2308 /* The prefix value is one dereference of the contents of the operand1
2310 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2311 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
2313 /* Check if the mode is autoincrement. */
2314 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2316 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2319 /* A prefix doesn't change the xflag_found. But the rest of the flags
2321 inst_env
->slot_needed
= 0;
2322 inst_env
->xflag_found
= 0;
2323 inst_env
->prefix_found
= 1;
2326 /* Finds the destination for a branch with 8-bits offset. */
2329 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2334 /* If we have a prefix or are in a delay slot it's bad. */
2335 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2337 inst_env
->invalid
= 1;
2341 /* We have a branch, find out where the branch will land. */
2342 offset
= cris_get_branch_short_offset (inst
);
2344 /* Check if the offset is signed. */
2345 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2350 /* The offset ends with the sign bit, set it to zero. The address
2351 should always be word aligned. */
2352 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2354 inst_env
->branch_found
= 1;
2355 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2357 inst_env
->slot_needed
= 1;
2358 inst_env
->prefix_found
= 0;
2359 inst_env
->xflag_found
= 0;
2360 inst_env
->disable_interrupt
= 1;
2363 /* Finds the destination for a branch with 16-bits offset. */
2366 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2370 /* If we have a prefix or is in a delay slot it's bad. */
2371 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2373 inst_env
->invalid
= 1;
2377 /* We have a branch, find out the offset for the branch. */
2378 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2380 /* The instruction is one word longer than normal, so add one word
2382 inst_env
->reg
[REG_PC
] += 2;
2384 inst_env
->branch_found
= 1;
2385 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2388 inst_env
->slot_needed
= 1;
2389 inst_env
->prefix_found
= 0;
2390 inst_env
->xflag_found
= 0;
2391 inst_env
->disable_interrupt
= 1;
2394 /* Handles the ABS instruction. */
2397 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2402 /* ABS can't have a prefix, so it's bad if it does. */
2403 if (inst_env
->prefix_found
)
2405 inst_env
->invalid
= 1;
2409 /* Check if the operation affects the PC. */
2410 if (cris_get_operand2 (inst
) == REG_PC
)
2413 /* It's invalid to change to the PC if we are in a delay slot. */
2414 if (inst_env
->slot_needed
)
2416 inst_env
->invalid
= 1;
2420 value
= (long) inst_env
->reg
[REG_PC
];
2422 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2423 if (value
!= SIGNED_DWORD_MASK
)
2426 inst_env
->reg
[REG_PC
] = (long) value
;
2430 inst_env
->slot_needed
= 0;
2431 inst_env
->prefix_found
= 0;
2432 inst_env
->xflag_found
= 0;
2433 inst_env
->disable_interrupt
= 0;
2436 /* Handles the ADDI instruction. */
2439 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2441 /* It's invalid to have the PC as base register. And ADDI can't have
2443 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2445 inst_env
->invalid
= 1;
2449 inst_env
->slot_needed
= 0;
2450 inst_env
->prefix_found
= 0;
2451 inst_env
->xflag_found
= 0;
2452 inst_env
->disable_interrupt
= 0;
2455 /* Handles the ASR instruction. */
2458 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2461 unsigned long value
;
2462 unsigned long signed_extend_mask
= 0;
2464 /* ASR can't have a prefix, so check that it doesn't. */
2465 if (inst_env
->prefix_found
)
2467 inst_env
->invalid
= 1;
2471 /* Check if the PC is the target register. */
2472 if (cris_get_operand2 (inst
) == REG_PC
)
2474 /* It's invalid to change the PC in a delay slot. */
2475 if (inst_env
->slot_needed
)
2477 inst_env
->invalid
= 1;
2480 /* Get the number of bits to shift. */
2481 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2482 value
= inst_env
->reg
[REG_PC
];
2484 /* Find out how many bits the operation should apply to. */
2485 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2487 if (value
& SIGNED_BYTE_MASK
)
2489 signed_extend_mask
= 0xFF;
2490 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2491 signed_extend_mask
= ~signed_extend_mask
;
2493 value
= value
>> shift_steps
;
2494 value
|= signed_extend_mask
;
2496 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2497 inst_env
->reg
[REG_PC
] |= value
;
2499 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2501 if (value
& SIGNED_WORD_MASK
)
2503 signed_extend_mask
= 0xFFFF;
2504 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2505 signed_extend_mask
= ~signed_extend_mask
;
2507 value
= value
>> shift_steps
;
2508 value
|= signed_extend_mask
;
2510 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2511 inst_env
->reg
[REG_PC
] |= value
;
2513 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2515 if (value
& SIGNED_DWORD_MASK
)
2517 signed_extend_mask
= 0xFFFFFFFF;
2518 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2519 signed_extend_mask
= ~signed_extend_mask
;
2521 value
= value
>> shift_steps
;
2522 value
|= signed_extend_mask
;
2523 inst_env
->reg
[REG_PC
] = value
;
2526 inst_env
->slot_needed
= 0;
2527 inst_env
->prefix_found
= 0;
2528 inst_env
->xflag_found
= 0;
2529 inst_env
->disable_interrupt
= 0;
2532 /* Handles the ASRQ instruction. */
2535 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2539 unsigned long value
;
2540 unsigned long signed_extend_mask
= 0;
2542 /* ASRQ can't have a prefix, so check that it doesn't. */
2543 if (inst_env
->prefix_found
)
2545 inst_env
->invalid
= 1;
2549 /* Check if the PC is the target register. */
2550 if (cris_get_operand2 (inst
) == REG_PC
)
2553 /* It's invalid to change the PC in a delay slot. */
2554 if (inst_env
->slot_needed
)
2556 inst_env
->invalid
= 1;
2559 /* The shift size is given as a 5 bit quick value, i.e. we don't
2560 want the the sign bit of the quick value. */
2561 shift_steps
= cris_get_asr_shift_steps (inst
);
2562 value
= inst_env
->reg
[REG_PC
];
2563 if (value
& SIGNED_DWORD_MASK
)
2565 signed_extend_mask
= 0xFFFFFFFF;
2566 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2567 signed_extend_mask
= ~signed_extend_mask
;
2569 value
= value
>> shift_steps
;
2570 value
|= signed_extend_mask
;
2571 inst_env
->reg
[REG_PC
] = value
;
2573 inst_env
->slot_needed
= 0;
2574 inst_env
->prefix_found
= 0;
2575 inst_env
->xflag_found
= 0;
2576 inst_env
->disable_interrupt
= 0;
2579 /* Handles the AX, EI and SETF instruction. */
2582 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2584 if (inst_env
->prefix_found
)
2586 inst_env
->invalid
= 1;
2589 /* Check if the instruction is setting the X flag. */
2590 if (cris_is_xflag_bit_on (inst
))
2592 inst_env
->xflag_found
= 1;
2596 inst_env
->xflag_found
= 0;
2598 inst_env
->slot_needed
= 0;
2599 inst_env
->prefix_found
= 0;
2600 inst_env
->disable_interrupt
= 1;
2603 /* Checks if the instruction is in assign mode. If so, it updates the assign
2604 register. Note that check_assign assumes that the caller has checked that
2605 there is a prefix to this instruction. The mode check depends on this. */
2608 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2610 /* Check if it's an assign addressing mode. */
2611 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2613 /* Assign the prefix value to operand 1. */
2614 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2618 /* Handles the 2-operand BOUND instruction. */
2621 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2623 /* It's invalid to have the PC as the index operand. */
2624 if (cris_get_operand2 (inst
) == REG_PC
)
2626 inst_env
->invalid
= 1;
2629 /* Check if we have a prefix. */
2630 if (inst_env
->prefix_found
)
2632 check_assign (inst
, inst_env
);
2634 /* Check if this is an autoincrement mode. */
2635 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2637 /* It's invalid to change the PC in a delay slot. */
2638 if (inst_env
->slot_needed
)
2640 inst_env
->invalid
= 1;
2643 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2645 inst_env
->slot_needed
= 0;
2646 inst_env
->prefix_found
= 0;
2647 inst_env
->xflag_found
= 0;
2648 inst_env
->disable_interrupt
= 0;
2651 /* Handles the 3-operand BOUND instruction. */
2654 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2656 /* It's an error if we haven't got a prefix. And it's also an error
2657 if the PC is the destination register. */
2658 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2660 inst_env
->invalid
= 1;
2663 inst_env
->slot_needed
= 0;
2664 inst_env
->prefix_found
= 0;
2665 inst_env
->xflag_found
= 0;
2666 inst_env
->disable_interrupt
= 0;
2669 /* Clears the status flags in inst_env. */
2672 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2674 /* It's an error if we have got a prefix. */
2675 if (inst_env
->prefix_found
)
2677 inst_env
->invalid
= 1;
2681 inst_env
->slot_needed
= 0;
2682 inst_env
->prefix_found
= 0;
2683 inst_env
->xflag_found
= 0;
2684 inst_env
->disable_interrupt
= 0;
2687 /* Clears the status flags in inst_env. */
2690 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2692 /* It's an error if we have got a prefix. */
2693 if (inst_env
->prefix_found
)
2695 inst_env
->invalid
= 1;
2699 inst_env
->slot_needed
= 0;
2700 inst_env
->prefix_found
= 0;
2701 inst_env
->xflag_found
= 0;
2702 inst_env
->disable_interrupt
= 1;
2705 /* Handles the CLEAR instruction if it's in register mode. */
2708 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2710 /* Check if the target is the PC. */
2711 if (cris_get_operand2 (inst
) == REG_PC
)
2713 /* The instruction will clear the instruction's size bits. */
2714 int clear_size
= cris_get_clear_size (inst
);
2715 if (clear_size
== INST_BYTE_SIZE
)
2717 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2719 if (clear_size
== INST_WORD_SIZE
)
2721 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2723 if (clear_size
== INST_DWORD_SIZE
)
2725 inst_env
->delay_slot_pc
= 0x0;
2727 /* The jump will be delayed with one delay slot. So we need a delay
2729 inst_env
->slot_needed
= 1;
2730 inst_env
->delay_slot_pc_active
= 1;
2734 /* The PC will not change => no delay slot. */
2735 inst_env
->slot_needed
= 0;
2737 inst_env
->prefix_found
= 0;
2738 inst_env
->xflag_found
= 0;
2739 inst_env
->disable_interrupt
= 0;
2742 /* Handles the TEST instruction if it's in register mode. */
2745 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2747 /* It's an error if we have got a prefix. */
2748 if (inst_env
->prefix_found
)
2750 inst_env
->invalid
= 1;
2753 inst_env
->slot_needed
= 0;
2754 inst_env
->prefix_found
= 0;
2755 inst_env
->xflag_found
= 0;
2756 inst_env
->disable_interrupt
= 0;
2760 /* Handles the CLEAR and TEST instruction if the instruction isn't
2761 in register mode. */
2764 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2766 /* Check if we are in a prefix mode. */
2767 if (inst_env
->prefix_found
)
2769 /* The only way the PC can change is if this instruction is in
2770 assign addressing mode. */
2771 check_assign (inst
, inst_env
);
2773 /* Indirect mode can't change the PC so just check if the mode is
2775 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2777 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2779 inst_env
->slot_needed
= 0;
2780 inst_env
->prefix_found
= 0;
2781 inst_env
->xflag_found
= 0;
2782 inst_env
->disable_interrupt
= 0;
2785 /* Checks that the PC isn't the destination register or the instructions has
2789 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2791 /* It's invalid to have the PC as the destination. The instruction can't
2793 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2795 inst_env
->invalid
= 1;
2799 inst_env
->slot_needed
= 0;
2800 inst_env
->prefix_found
= 0;
2801 inst_env
->xflag_found
= 0;
2802 inst_env
->disable_interrupt
= 0;
2805 /* Checks that the instruction doesn't have a prefix. */
2808 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2810 /* The instruction can't have a prefix. */
2811 if (inst_env
->prefix_found
)
2813 inst_env
->invalid
= 1;
2817 inst_env
->slot_needed
= 0;
2818 inst_env
->prefix_found
= 0;
2819 inst_env
->xflag_found
= 0;
2820 inst_env
->disable_interrupt
= 1;
2823 /* Checks that the PC isn't the destination register and that the instruction
2824 doesn't have a prefix. */
2827 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2829 /* It's invalid to have the PC as the destination. The instruction can't
2831 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2833 inst_env
->invalid
= 1;
2837 inst_env
->slot_needed
= 0;
2838 inst_env
->prefix_found
= 0;
2839 inst_env
->xflag_found
= 0;
2840 inst_env
->disable_interrupt
= 1;
2843 /* Handles the register mode JUMP instruction. */
2846 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2848 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2849 you can't have a prefix. */
2850 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2852 inst_env
->invalid
= 1;
2856 /* Just change the PC. */
2857 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2858 inst_env
->slot_needed
= 0;
2859 inst_env
->prefix_found
= 0;
2860 inst_env
->xflag_found
= 0;
2861 inst_env
->disable_interrupt
= 1;
2864 /* Handles the JUMP instruction for all modes except register. */
2867 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2869 unsigned long newpc
;
2872 /* It's invalid to do a JUMP in a delay slot. */
2873 if (inst_env
->slot_needed
)
2875 inst_env
->invalid
= 1;
2879 /* Check if we have a prefix. */
2880 if (inst_env
->prefix_found
)
2882 check_assign (inst
, inst_env
);
2884 /* Get the new value for the the PC. */
2886 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2891 /* Get the new value for the PC. */
2892 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2893 newpc
= read_memory_unsigned_integer (address
, 4);
2895 /* Check if we should increment a register. */
2896 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2898 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2901 inst_env
->reg
[REG_PC
] = newpc
;
2903 inst_env
->slot_needed
= 0;
2904 inst_env
->prefix_found
= 0;
2905 inst_env
->xflag_found
= 0;
2906 inst_env
->disable_interrupt
= 1;
2909 /* Handles moves to special registers (aka P-register) for all modes. */
2912 move_to_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2913 inst_env_type
*inst_env
)
2915 if (inst_env
->prefix_found
)
2917 /* The instruction has a prefix that means we are only interested if
2918 the instruction is in assign mode. */
2919 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2921 /* The prefix handles the problem if we are in a delay slot. */
2922 if (cris_get_operand1 (inst
) == REG_PC
)
2924 /* Just take care of the assign. */
2925 check_assign (inst
, inst_env
);
2929 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2931 /* The instruction doesn't have a prefix, the only case left that we
2932 are interested in is the autoincrement mode. */
2933 if (cris_get_operand1 (inst
) == REG_PC
)
2935 /* If the PC is to be incremented it's invalid to be in a
2937 if (inst_env
->slot_needed
)
2939 inst_env
->invalid
= 1;
2943 /* The increment depends on the size of the special register. */
2944 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2946 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2948 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2950 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2954 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2958 inst_env
->slot_needed
= 0;
2959 inst_env
->prefix_found
= 0;
2960 inst_env
->xflag_found
= 0;
2961 inst_env
->disable_interrupt
= 1;
2964 /* Handles moves from special registers (aka P-register) for all modes
2968 none_reg_mode_move_from_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2969 inst_env_type
*inst_env
)
2971 if (inst_env
->prefix_found
)
2973 /* The instruction has a prefix that means we are only interested if
2974 the instruction is in assign mode. */
2975 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2977 /* The prefix handles the problem if we are in a delay slot. */
2978 if (cris_get_operand1 (inst
) == REG_PC
)
2980 /* Just take care of the assign. */
2981 check_assign (inst
, inst_env
);
2985 /* The instruction doesn't have a prefix, the only case left that we
2986 are interested in is the autoincrement mode. */
2987 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2989 if (cris_get_operand1 (inst
) == REG_PC
)
2991 /* If the PC is to be incremented it's invalid to be in a
2993 if (inst_env
->slot_needed
)
2995 inst_env
->invalid
= 1;
2999 /* The increment depends on the size of the special register. */
3000 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
3002 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
3004 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
3006 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
3010 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
3014 inst_env
->slot_needed
= 0;
3015 inst_env
->prefix_found
= 0;
3016 inst_env
->xflag_found
= 0;
3017 inst_env
->disable_interrupt
= 1;
3020 /* Handles moves from special registers (aka P-register) when the mode
3024 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
3026 /* Register mode move from special register can't have a prefix. */
3027 if (inst_env
->prefix_found
)
3029 inst_env
->invalid
= 1;
3033 if (cris_get_operand1 (inst
) == REG_PC
)
3035 /* It's invalid to change the PC in a delay slot. */
3036 if (inst_env
->slot_needed
)
3038 inst_env
->invalid
= 1;
3041 /* The destination is the PC, the jump will have a delay slot. */
3042 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
3043 inst_env
->slot_needed
= 1;
3044 inst_env
->delay_slot_pc_active
= 1;
3048 /* If the destination isn't PC, there will be no jump. */
3049 inst_env
->slot_needed
= 0;
3051 inst_env
->prefix_found
= 0;
3052 inst_env
->xflag_found
= 0;
3053 inst_env
->disable_interrupt
= 1;
3056 /* Handles the MOVEM from memory to general register instruction. */
3059 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3061 if (inst_env
->prefix_found
)
3063 /* The prefix handles the problem if we are in a delay slot. Is the
3064 MOVEM instruction going to change the PC? */
3065 if (cris_get_operand2 (inst
) >= REG_PC
)
3067 inst_env
->reg
[REG_PC
] =
3068 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
3070 /* The assign value is the value after the increment. Normally, the
3071 assign value is the value before the increment. */
3072 if ((cris_get_operand1 (inst
) == REG_PC
)
3073 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3075 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3076 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3081 /* Is the MOVEM instruction going to change the PC? */
3082 if (cris_get_operand2 (inst
) == REG_PC
)
3084 /* It's invalid to change the PC in a delay slot. */
3085 if (inst_env
->slot_needed
)
3087 inst_env
->invalid
= 1;
3090 inst_env
->reg
[REG_PC
] =
3091 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3094 /* The increment is not depending on the size, instead it's depending
3095 on the number of registers loaded from memory. */
3096 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3098 /* It's invalid to change the PC in a delay slot. */
3099 if (inst_env
->slot_needed
)
3101 inst_env
->invalid
= 1;
3104 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3107 inst_env
->slot_needed
= 0;
3108 inst_env
->prefix_found
= 0;
3109 inst_env
->xflag_found
= 0;
3110 inst_env
->disable_interrupt
= 0;
3113 /* Handles the MOVEM to memory from general register instruction. */
3116 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3118 if (inst_env
->prefix_found
)
3120 /* The assign value is the value after the increment. Normally, the
3121 assign value is the value before the increment. */
3122 if ((cris_get_operand1 (inst
) == REG_PC
) &&
3123 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3125 /* The prefix handles the problem if we are in a delay slot. */
3126 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3127 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3132 /* The increment is not depending on the size, instead it's depending
3133 on the number of registers loaded to memory. */
3134 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3136 /* It's invalid to change the PC in a delay slot. */
3137 if (inst_env
->slot_needed
)
3139 inst_env
->invalid
= 1;
3142 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3145 inst_env
->slot_needed
= 0;
3146 inst_env
->prefix_found
= 0;
3147 inst_env
->xflag_found
= 0;
3148 inst_env
->disable_interrupt
= 0;
3151 /* Handles the intructions that's not yet implemented, by setting
3152 inst_env->invalid to true. */
3155 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3157 inst_env
->invalid
= 1;
3160 /* Handles the XOR instruction. */
3163 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3165 /* XOR can't have a prefix. */
3166 if (inst_env
->prefix_found
)
3168 inst_env
->invalid
= 1;
3172 /* Check if the PC is the target. */
3173 if (cris_get_operand2 (inst
) == REG_PC
)
3175 /* It's invalid to change the PC in a delay slot. */
3176 if (inst_env
->slot_needed
)
3178 inst_env
->invalid
= 1;
3181 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3183 inst_env
->slot_needed
= 0;
3184 inst_env
->prefix_found
= 0;
3185 inst_env
->xflag_found
= 0;
3186 inst_env
->disable_interrupt
= 0;
3189 /* Handles the MULS instruction. */
3192 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3194 /* MULS/U can't have a prefix. */
3195 if (inst_env
->prefix_found
)
3197 inst_env
->invalid
= 1;
3201 /* Consider it invalid if the PC is the target. */
3202 if (cris_get_operand2 (inst
) == REG_PC
)
3204 inst_env
->invalid
= 1;
3207 inst_env
->slot_needed
= 0;
3208 inst_env
->prefix_found
= 0;
3209 inst_env
->xflag_found
= 0;
3210 inst_env
->disable_interrupt
= 0;
3213 /* Handles the MULU instruction. */
3216 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3218 /* MULS/U can't have a prefix. */
3219 if (inst_env
->prefix_found
)
3221 inst_env
->invalid
= 1;
3225 /* Consider it invalid if the PC is the target. */
3226 if (cris_get_operand2 (inst
) == REG_PC
)
3228 inst_env
->invalid
= 1;
3231 inst_env
->slot_needed
= 0;
3232 inst_env
->prefix_found
= 0;
3233 inst_env
->xflag_found
= 0;
3234 inst_env
->disable_interrupt
= 0;
3237 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3238 The MOVE instruction is the move from source to register. */
3241 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3242 unsigned long source1
, unsigned long source2
)
3244 unsigned long pc_mask
;
3245 unsigned long operation_mask
;
3247 /* Find out how many bits the operation should apply to. */
3248 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3250 pc_mask
= 0xFFFFFF00;
3251 operation_mask
= 0xFF;
3253 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3255 pc_mask
= 0xFFFF0000;
3256 operation_mask
= 0xFFFF;
3258 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3261 operation_mask
= 0xFFFFFFFF;
3265 /* The size is out of range. */
3266 inst_env
->invalid
= 1;
3270 /* The instruction just works on uw_operation_mask bits. */
3271 source2
&= operation_mask
;
3272 source1
&= operation_mask
;
3274 /* Now calculate the result. The opcode's 3 first bits separates
3275 the different actions. */
3276 switch (cris_get_opcode (inst
) & 7)
3286 case 2: /* subtract */
3290 case 3: /* compare */
3302 inst_env
->invalid
= 1;
3308 /* Make sure that the result doesn't contain more than the instruction
3310 source2
&= operation_mask
;
3312 /* Calculate the new breakpoint address. */
3313 inst_env
->reg
[REG_PC
] &= pc_mask
;
3314 inst_env
->reg
[REG_PC
] |= source1
;
3318 /* Extends the value from either byte or word size to a dword. If the mode
3319 is zero extend then the value is extended with zero. If instead the mode
3320 is signed extend the sign bit of the value is taken into consideration. */
3322 static unsigned long
3323 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3325 /* The size can be either byte or word, check which one it is.
3326 Don't check the highest bit, it's indicating if it's a zero
3328 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3333 /* Check if the instruction is signed extend. If so, check if value has
3335 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3337 value
|= SIGNED_WORD_EXTEND_MASK
;
3345 /* Check if the instruction is signed extend. If so, check if value has
3347 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3349 value
|= SIGNED_BYTE_EXTEND_MASK
;
3352 /* The size should now be dword. */
3353 cris_set_size_to_dword (inst
);
3357 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3358 instruction. The MOVE instruction is the move from source to register. */
3361 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3362 inst_env_type
*inst_env
)
3364 unsigned long operand1
;
3365 unsigned long operand2
;
3367 /* It's invalid to have a prefix to the instruction. This is a register
3368 mode instruction and can't have a prefix. */
3369 if (inst_env
->prefix_found
)
3371 inst_env
->invalid
= 1;
3374 /* Check if the instruction has PC as its target. */
3375 if (cris_get_operand2 (inst
) == REG_PC
)
3377 if (inst_env
->slot_needed
)
3379 inst_env
->invalid
= 1;
3382 /* The instruction has the PC as its target register. */
3383 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3384 operand2
= inst_env
->reg
[REG_PC
];
3386 /* Check if it's a extend, signed or zero instruction. */
3387 if (cris_get_opcode (inst
) < 4)
3389 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3391 /* Calculate the PC value after the instruction, i.e. where the
3392 breakpoint should be. The order of the udw_operands is vital. */
3393 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3395 inst_env
->slot_needed
= 0;
3396 inst_env
->prefix_found
= 0;
3397 inst_env
->xflag_found
= 0;
3398 inst_env
->disable_interrupt
= 0;
3401 /* Returns the data contained at address. The size of the data is derived from
3402 the size of the operation. If the instruction is a zero or signed
3403 extend instruction, the size field is changed in instruction. */
3405 static unsigned long
3406 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3408 int size
= cris_get_size (*inst
);
3409 unsigned long value
;
3411 /* If it's an extend instruction we don't want the signed extend bit,
3412 because it influences the size. */
3413 if (cris_get_opcode (*inst
) < 4)
3415 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3417 /* Is there a need for checking the size? Size should contain the number of
3420 value
= read_memory_unsigned_integer (address
, size
);
3422 /* Check if it's an extend, signed or zero instruction. */
3423 if (cris_get_opcode (*inst
) < 4)
3425 value
= do_sign_or_zero_extend (value
, inst
);
3430 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3431 instructions. The MOVE instruction is the move from source to register. */
3434 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3435 inst_env_type
*inst_env
)
3437 unsigned long operand2
;
3438 unsigned long operand3
;
3440 check_assign (inst
, inst_env
);
3441 if (cris_get_operand2 (inst
) == REG_PC
)
3443 operand2
= inst_env
->reg
[REG_PC
];
3445 /* Get the value of the third operand. */
3446 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3448 /* Calculate the PC value after the instruction, i.e. where the
3449 breakpoint should be. The order of the udw_operands is vital. */
3450 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3452 inst_env
->slot_needed
= 0;
3453 inst_env
->prefix_found
= 0;
3454 inst_env
->xflag_found
= 0;
3455 inst_env
->disable_interrupt
= 0;
3458 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3459 OR instructions. Note that for this to work as expected, the calling
3460 function must have made sure that there is a prefix to this instruction. */
3463 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3464 inst_env_type
*inst_env
)
3466 unsigned long operand2
;
3467 unsigned long operand3
;
3469 if (cris_get_operand1 (inst
) == REG_PC
)
3471 /* The PC will be changed by the instruction. */
3472 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3474 /* Get the value of the third operand. */
3475 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3477 /* Calculate the PC value after the instruction, i.e. where the
3478 breakpoint should be. */
3479 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3481 inst_env
->slot_needed
= 0;
3482 inst_env
->prefix_found
= 0;
3483 inst_env
->xflag_found
= 0;
3484 inst_env
->disable_interrupt
= 0;
3487 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3488 instructions. The MOVE instruction is the move from source to register. */
3491 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3492 inst_env_type
*inst_env
)
3494 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3496 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3497 SUB, AND or OR something weird is going on (if everything works these
3498 instructions should end up in the three operand version). */
3499 inst_env
->invalid
= 1;
3504 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3506 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3508 inst_env
->slot_needed
= 0;
3509 inst_env
->prefix_found
= 0;
3510 inst_env
->xflag_found
= 0;
3511 inst_env
->disable_interrupt
= 0;
3514 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3515 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3516 source to register. */
3519 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3520 inst_env_type
*inst_env
)
3522 unsigned long operand1
;
3523 unsigned long operand2
;
3524 unsigned long operand3
;
3527 /* The instruction is either an indirect or autoincrement addressing mode.
3528 Check if the destination register is the PC. */
3529 if (cris_get_operand2 (inst
) == REG_PC
)
3531 /* Must be done here, get_data_from_address may change the size
3533 size
= cris_get_size (inst
);
3534 operand2
= inst_env
->reg
[REG_PC
];
3536 /* Get the value of the third operand, i.e. the indirect operand. */
3537 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3538 operand3
= get_data_from_address (&inst
, operand1
);
3540 /* Calculate the PC value after the instruction, i.e. where the
3541 breakpoint should be. The order of the udw_operands is vital. */
3542 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3544 /* If this is an autoincrement addressing mode, check if the increment
3546 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3548 /* Get the size field. */
3549 size
= cris_get_size (inst
);
3551 /* If it's an extend instruction we don't want the signed extend bit,
3552 because it influences the size. */
3553 if (cris_get_opcode (inst
) < 4)
3555 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3557 process_autoincrement (size
, inst
, inst_env
);
3559 inst_env
->slot_needed
= 0;
3560 inst_env
->prefix_found
= 0;
3561 inst_env
->xflag_found
= 0;
3562 inst_env
->disable_interrupt
= 0;
3565 /* Handles the two-operand addressing mode, all modes except register, for
3566 the ADD, SUB CMP, AND and OR instruction. */
3569 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3570 inst_env_type
*inst_env
)
3572 if (inst_env
->prefix_found
)
3574 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3576 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3578 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3580 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3584 /* The mode is invalid for a prefixed base instruction. */
3585 inst_env
->invalid
= 1;
3591 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3595 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3598 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3600 unsigned long operand1
;
3601 unsigned long operand2
;
3603 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3604 instruction and can't have a prefix. */
3605 if (inst_env
->prefix_found
)
3607 inst_env
->invalid
= 1;
3611 /* Check if the instruction has PC as its target. */
3612 if (cris_get_operand2 (inst
) == REG_PC
)
3614 if (inst_env
->slot_needed
)
3616 inst_env
->invalid
= 1;
3619 operand1
= cris_get_quick_value (inst
);
3620 operand2
= inst_env
->reg
[REG_PC
];
3622 /* The size should now be dword. */
3623 cris_set_size_to_dword (&inst
);
3625 /* Calculate the PC value after the instruction, i.e. where the
3626 breakpoint should be. */
3627 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3629 inst_env
->slot_needed
= 0;
3630 inst_env
->prefix_found
= 0;
3631 inst_env
->xflag_found
= 0;
3632 inst_env
->disable_interrupt
= 0;
3635 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3638 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3640 unsigned long operand1
;
3641 unsigned long operand2
;
3643 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3644 instruction and can't have a prefix. */
3645 if (inst_env
->prefix_found
)
3647 inst_env
->invalid
= 1;
3650 /* Check if the instruction has PC as its target. */
3651 if (cris_get_operand2 (inst
) == REG_PC
)
3653 if (inst_env
->slot_needed
)
3655 inst_env
->invalid
= 1;
3658 /* The instruction has the PC as its target register. */
3659 operand1
= cris_get_quick_value (inst
);
3660 operand2
= inst_env
->reg
[REG_PC
];
3662 /* The quick value is signed, so check if we must do a signed extend. */
3663 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3666 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3668 /* The size should now be dword. */
3669 cris_set_size_to_dword (&inst
);
3671 /* Calculate the PC value after the instruction, i.e. where the
3672 breakpoint should be. */
3673 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3675 inst_env
->slot_needed
= 0;
3676 inst_env
->prefix_found
= 0;
3677 inst_env
->xflag_found
= 0;
3678 inst_env
->disable_interrupt
= 0;
3681 /* Translate op_type to a function and call it. */
3684 cris_gdb_func (struct gdbarch
*gdbarch
, enum cris_op_type op_type
,
3685 unsigned short inst
, inst_env_type
*inst_env
)
3689 case cris_not_implemented_op
:
3690 not_implemented_op (inst
, inst_env
);
3694 abs_op (inst
, inst_env
);
3698 addi_op (inst
, inst_env
);
3702 asr_op (inst
, inst_env
);
3706 asrq_op (inst
, inst_env
);
3709 case cris_ax_ei_setf_op
:
3710 ax_ei_setf_op (inst
, inst_env
);
3713 case cris_bdap_prefix
:
3714 bdap_prefix (inst
, inst_env
);
3717 case cris_biap_prefix
:
3718 biap_prefix (inst
, inst_env
);
3722 break_op (inst
, inst_env
);
3725 case cris_btst_nop_op
:
3726 btst_nop_op (inst
, inst_env
);
3729 case cris_clearf_di_op
:
3730 clearf_di_op (inst
, inst_env
);
3733 case cris_dip_prefix
:
3734 dip_prefix (inst
, inst_env
);
3737 case cris_dstep_logshift_mstep_neg_not_op
:
3738 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3741 case cris_eight_bit_offset_branch_op
:
3742 eight_bit_offset_branch_op (inst
, inst_env
);
3745 case cris_move_mem_to_reg_movem_op
:
3746 move_mem_to_reg_movem_op (inst
, inst_env
);
3749 case cris_move_reg_to_mem_movem_op
:
3750 move_reg_to_mem_movem_op (inst
, inst_env
);
3753 case cris_move_to_preg_op
:
3754 move_to_preg_op (gdbarch
, inst
, inst_env
);
3758 muls_op (inst
, inst_env
);
3762 mulu_op (inst
, inst_env
);
3765 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3766 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3769 case cris_none_reg_mode_clear_test_op
:
3770 none_reg_mode_clear_test_op (inst
, inst_env
);
3773 case cris_none_reg_mode_jump_op
:
3774 none_reg_mode_jump_op (inst
, inst_env
);
3777 case cris_none_reg_mode_move_from_preg_op
:
3778 none_reg_mode_move_from_preg_op (gdbarch
, inst
, inst_env
);
3781 case cris_quick_mode_add_sub_op
:
3782 quick_mode_add_sub_op (inst
, inst_env
);
3785 case cris_quick_mode_and_cmp_move_or_op
:
3786 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3789 case cris_quick_mode_bdap_prefix
:
3790 quick_mode_bdap_prefix (inst
, inst_env
);
3793 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3794 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3797 case cris_reg_mode_clear_op
:
3798 reg_mode_clear_op (inst
, inst_env
);
3801 case cris_reg_mode_jump_op
:
3802 reg_mode_jump_op (inst
, inst_env
);
3805 case cris_reg_mode_move_from_preg_op
:
3806 reg_mode_move_from_preg_op (inst
, inst_env
);
3809 case cris_reg_mode_test_op
:
3810 reg_mode_test_op (inst
, inst_env
);
3814 scc_op (inst
, inst_env
);
3817 case cris_sixteen_bit_offset_branch_op
:
3818 sixteen_bit_offset_branch_op (inst
, inst_env
);
3821 case cris_three_operand_add_sub_cmp_and_or_op
:
3822 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3825 case cris_three_operand_bound_op
:
3826 three_operand_bound_op (inst
, inst_env
);
3829 case cris_two_operand_bound_op
:
3830 two_operand_bound_op (inst
, inst_env
);
3834 xor_op (inst
, inst_env
);
3839 /* This wrapper is to avoid cris_get_assembler being called before
3840 exec_bfd has been set. */
3843 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3845 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3846 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3847 disassembler, even when there is no BFD. Does something like
3848 "gdb; target remote; disassmeble *0x123" work? */
3849 gdb_assert (exec_bfd
!= NULL
);
3850 print_insn
= cris_get_disassembler (exec_bfd
);
3851 gdb_assert (print_insn
!= NULL
);
3852 return print_insn (addr
, info
);
3855 /* Copied from <asm/elf.h>. */
3856 typedef unsigned long elf_greg_t
;
3858 /* Same as user_regs_struct struct in <asm/user.h>. */
3859 #define CRISV10_ELF_NGREG 35
3860 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3862 #define CRISV32_ELF_NGREG 32
3863 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3865 /* Unpack an elf_gregset_t into GDB's register cache. */
3868 cris_supply_gregset (struct regcache
*regcache
, elf_gregset_t
*gregsetp
)
3870 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3871 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3873 elf_greg_t
*regp
= *gregsetp
;
3874 static char zerobuf
[4] = {0};
3876 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3877 knows about the actual size of each register so that's no problem. */
3878 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3880 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3883 if (tdep
->cris_version
== 32)
3885 /* Needed to set pseudo-register PC for CRISv32. */
3886 /* FIXME: If ERP is in a delay slot at this point then the PC will
3887 be wrong. Issue a warning to alert the user. */
3888 regcache_raw_supply (regcache
, gdbarch_pc_regnum (gdbarch
),
3889 (char *)®p
[ERP_REGNUM
]);
3891 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3892 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3896 /* Use a local version of this function to get the correct types for
3897 regsets, until multi-arch core support is ready. */
3900 fetch_core_registers (struct regcache
*regcache
,
3901 char *core_reg_sect
, unsigned core_reg_size
,
3902 int which
, CORE_ADDR reg_addr
)
3904 elf_gregset_t gregset
;
3909 if (core_reg_size
!= sizeof (elf_gregset_t
)
3910 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3912 warning (_("wrong size gregset struct in core file"));
3916 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3917 cris_supply_gregset (regcache
, &gregset
);
3921 /* We've covered all the kinds of registers we know about here,
3922 so this must be something we wouldn't know what to do with
3923 anyway. Just ignore it. */
3928 static struct core_fns cris_elf_core_fns
=
3930 bfd_target_elf_flavour
, /* core_flavour */
3931 default_check_format
, /* check_format */
3932 default_core_sniffer
, /* core_sniffer */
3933 fetch_core_registers
, /* core_read_registers */
3937 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3940 _initialize_cris_tdep (void)
3942 static struct cmd_list_element
*cris_set_cmdlist
;
3943 static struct cmd_list_element
*cris_show_cmdlist
;
3945 struct cmd_list_element
*c
;
3947 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3949 /* CRIS-specific user-commands. */
3950 add_setshow_uinteger_cmd ("cris-version", class_support
,
3951 &usr_cmd_cris_version
,
3952 _("Set the current CRIS version."),
3953 _("Show the current CRIS version."),
3955 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3958 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3959 &setlist
, &showlist
);
3961 add_setshow_enum_cmd ("cris-mode", class_support
,
3962 cris_modes
, &usr_cmd_cris_mode
,
3963 _("Set the current CRIS mode."),
3964 _("Show the current CRIS mode."),
3966 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3967 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3969 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3970 &setlist
, &showlist
);
3972 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3973 &usr_cmd_cris_dwarf2_cfi
,
3974 _("Set the usage of Dwarf-2 CFI for CRIS."),
3975 _("Show the usage of Dwarf-2 CFI for CRIS."),
3976 _("Set this to \"off\" if using gcc-cris < R59."),
3977 set_cris_dwarf2_cfi
,
3978 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3979 &setlist
, &showlist
);
3981 deprecated_add_core_fns (&cris_elf_core_fns
);
3984 /* Prints out all target specific values. */
3987 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3989 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3992 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3993 tdep
->cris_version
);
3994 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3996 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3997 tdep
->cris_dwarf2_cfi
);
4002 set_cris_version (char *ignore_args
, int from_tty
,
4003 struct cmd_list_element
*c
)
4005 struct gdbarch_info info
;
4007 usr_cmd_cris_version_valid
= 1;
4009 /* Update the current architecture, if needed. */
4010 gdbarch_info_init (&info
);
4011 if (!gdbarch_update_p (info
))
4012 internal_error (__FILE__
, __LINE__
,
4013 _("cris_gdbarch_update: failed to update architecture."));
4017 set_cris_mode (char *ignore_args
, int from_tty
,
4018 struct cmd_list_element
*c
)
4020 struct gdbarch_info info
;
4022 /* Update the current architecture, if needed. */
4023 gdbarch_info_init (&info
);
4024 if (!gdbarch_update_p (info
))
4025 internal_error (__FILE__
, __LINE__
,
4026 "cris_gdbarch_update: failed to update architecture.");
4030 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
4031 struct cmd_list_element
*c
)
4033 struct gdbarch_info info
;
4035 /* Update the current architecture, if needed. */
4036 gdbarch_info_init (&info
);
4037 if (!gdbarch_update_p (info
))
4038 internal_error (__FILE__
, __LINE__
,
4039 _("cris_gdbarch_update: failed to update architecture."));
4042 static struct gdbarch
*
4043 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4045 struct gdbarch
*gdbarch
;
4046 struct gdbarch_tdep
*tdep
;
4049 if (usr_cmd_cris_version_valid
)
4051 /* Trust the user's CRIS version setting. */
4052 cris_version
= usr_cmd_cris_version
;
4054 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4060 /* Assume it's CRIS version 10. */
4064 /* Make the current settings visible to the user. */
4065 usr_cmd_cris_version
= cris_version
;
4067 /* Find a candidate among the list of pre-declared architectures. */
4068 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4070 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4072 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4073 == usr_cmd_cris_version
)
4074 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4075 == usr_cmd_cris_mode
)
4076 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4077 == usr_cmd_cris_dwarf2_cfi
))
4078 return arches
->gdbarch
;
4081 /* No matching architecture was found. Create a new one. */
4082 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4083 gdbarch
= gdbarch_alloc (&info
, tdep
);
4085 tdep
->cris_version
= usr_cmd_cris_version
;
4086 tdep
->cris_mode
= usr_cmd_cris_mode
;
4087 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4089 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4090 switch (info
.byte_order
)
4092 case BFD_ENDIAN_LITTLE
:
4096 case BFD_ENDIAN_BIG
:
4097 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: big endian byte order in info"));
4101 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: unknown byte order in info"));
4104 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4106 set_gdbarch_sp_regnum (gdbarch
, 14);
4108 /* Length of ordinary registers used in push_word and a few other
4109 places. register_size() is the real way to know how big a
4112 set_gdbarch_double_bit (gdbarch
, 64);
4113 /* The default definition of a long double is 2 * gdbarch_double_bit,
4114 which means we have to set this explicitly. */
4115 set_gdbarch_long_double_bit (gdbarch
, 64);
4117 /* The total amount of space needed to store (in an array called registers)
4118 GDB's copy of the machine's register state. Note: We can not use
4119 cris_register_size at this point, since it relies on gdbarch
4121 switch (tdep
->cris_version
)
4129 /* Old versions; not supported. */
4130 internal_error (__FILE__
, __LINE__
,
4131 _("cris_gdbarch_init: unsupported CRIS version"));
4136 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4137 P7 (32 bits), and P15 (32 bits) have been implemented. */
4138 set_gdbarch_pc_regnum (gdbarch
, 15);
4139 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4140 /* There are 32 registers (some of which may not be implemented). */
4141 set_gdbarch_num_regs (gdbarch
, 32);
4142 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4143 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4144 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4146 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4150 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4151 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4152 and pseudo-register PC (32 bits). */
4153 set_gdbarch_pc_regnum (gdbarch
, 32);
4154 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4155 /* 32 registers + pseudo-register PC + 16 support registers. */
4156 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4157 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4159 set_gdbarch_cannot_store_register
4160 (gdbarch
, crisv32_cannot_store_register
);
4161 set_gdbarch_cannot_fetch_register
4162 (gdbarch
, crisv32_cannot_fetch_register
);
4164 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4166 set_gdbarch_single_step_through_delay
4167 (gdbarch
, crisv32_single_step_through_delay
);
4172 internal_error (__FILE__
, __LINE__
,
4173 _("cris_gdbarch_init: unknown CRIS version"));
4176 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4177 have the same ABI). */
4178 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4179 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4180 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4181 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4183 /* The stack grows downward. */
4184 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4186 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4188 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4189 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4190 set_gdbarch_dummy_id (gdbarch
, cris_dummy_id
);
4192 if (tdep
->cris_dwarf2_cfi
== 1)
4194 /* Hook in the Dwarf-2 frame sniffer. */
4195 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4196 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4197 dwarf2_append_unwinders (gdbarch
);
4200 if (tdep
->cris_mode
!= cris_mode_guru
)
4202 frame_unwind_append_unwinder (gdbarch
, &cris_sigtramp_frame_unwind
);
4205 frame_unwind_append_unwinder (gdbarch
, &cris_frame_unwind
);
4206 frame_base_set_default (gdbarch
, &cris_frame_base
);
4208 set_solib_svr4_fetch_link_map_offsets
4209 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
4211 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4212 disassembler, even when there is no BFD. Does something like
4213 "gdb; target remote; disassmeble *0x123" work? */
4214 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);