1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2012 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
37 #include "arch-utils.h"
39 #include "gdb_assert.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
45 #include "gdb_string.h"
50 /* There are no floating point registers. Used in gdbserver low-linux.c. */
53 /* There are 16 general registers. */
56 /* There are 16 special registers. */
59 /* CRISv32 has a pseudo PC register, not noted here. */
61 /* CRISv32 has 16 support registers. */
65 /* Register numbers of various important registers.
66 CRIS_FP_REGNUM Contains address of executing stack frame.
67 STR_REGNUM Contains the address of structure return values.
68 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
69 ARG1_REGNUM Contains the first parameter to a function.
70 ARG2_REGNUM Contains the second parameter to a function.
71 ARG3_REGNUM Contains the third parameter to a function.
72 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
73 gdbarch_sp_regnum Contains address of top of stack.
74 gdbarch_pc_regnum Contains address of next instruction.
75 SRP_REGNUM Subroutine return pointer register.
76 BRP_REGNUM Breakpoint return pointer register. */
80 /* Enums with respect to the general registers, valid for all
81 CRIS versions. The frame pointer is always in R8. */
83 /* ABI related registers. */
91 /* Registers which happen to be common. */
96 /* CRISv10 et al. specific registers. */
108 /* CRISv32 specific registers. */
121 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
123 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
143 extern const struct cris_spec_reg cris_spec_regs
[];
145 /* CRIS version, set via the user command 'set cris-version'. Affects
146 register names and sizes. */
147 static int usr_cmd_cris_version
;
149 /* Indicates whether to trust the above variable. */
150 static int usr_cmd_cris_version_valid
= 0;
152 static const char cris_mode_normal
[] = "normal";
153 static const char cris_mode_guru
[] = "guru";
154 static const char *const cris_modes
[] = {
160 /* CRIS mode, set via the user command 'set cris-mode'. Affects
161 type of break instruction among other things. */
162 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
164 /* Whether to make use of Dwarf-2 CFI (default on). */
165 static int usr_cmd_cris_dwarf2_cfi
= 1;
167 /* CRIS architecture specific information. */
171 const char *cris_mode
;
175 /* Sigtramp identification code copied from i386-linux-tdep.c. */
177 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
178 #define SIGTRAMP_OFFSET0 0
179 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
180 #define SIGTRAMP_OFFSET1 4
182 static const unsigned short sigtramp_code
[] =
184 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
185 SIGTRAMP_INSN1
/* break 13 */
188 #define SIGTRAMP_LEN (sizeof sigtramp_code)
190 /* Note: same length as normal sigtramp code. */
192 static const unsigned short rt_sigtramp_code
[] =
194 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
195 SIGTRAMP_INSN1
/* break 13 */
198 /* If PC is in a sigtramp routine, return the address of the start of
199 the routine. Otherwise, return 0. */
202 cris_sigtramp_start (struct frame_info
*this_frame
)
204 CORE_ADDR pc
= get_frame_pc (this_frame
);
205 gdb_byte buf
[SIGTRAMP_LEN
];
207 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
210 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
212 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
215 pc
-= SIGTRAMP_OFFSET1
;
216 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
220 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
226 /* If PC is in a RT sigtramp routine, return the address of the start of
227 the routine. Otherwise, return 0. */
230 cris_rt_sigtramp_start (struct frame_info
*this_frame
)
232 CORE_ADDR pc
= get_frame_pc (this_frame
);
233 gdb_byte buf
[SIGTRAMP_LEN
];
235 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
238 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
240 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
243 pc
-= SIGTRAMP_OFFSET1
;
244 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
248 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
254 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
255 return the address of the associated sigcontext structure. */
258 cris_sigcontext_addr (struct frame_info
*this_frame
)
260 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
261 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
266 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
267 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
269 /* Look for normal sigtramp frame first. */
270 pc
= cris_sigtramp_start (this_frame
);
273 /* struct signal_frame (arch/cris/kernel/signal.c) contains
274 struct sigcontext as its first member, meaning the SP points to
279 pc
= cris_rt_sigtramp_start (this_frame
);
282 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
283 a struct ucontext, which in turn contains a struct sigcontext.
285 4 + 4 + 128 to struct ucontext, then
286 4 + 4 + 12 to struct sigcontext. */
290 error (_("Couldn't recognize signal trampoline."));
294 struct cris_unwind_cache
296 /* The previous frame's inner most stack address. Used as this
297 frame ID's stack_addr. */
299 /* The frame's base, optionally used by the high-level debug info. */
302 /* How far the SP and r8 (FP) have been offset from the start of
303 the stack frame (as defined by the previous frame's stack
309 /* From old frame_extra_info struct. */
313 /* Table indicating the location of each and every register. */
314 struct trad_frame_saved_reg
*saved_regs
;
317 static struct cris_unwind_cache
*
318 cris_sigtramp_frame_unwind_cache (struct frame_info
*this_frame
,
321 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
322 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
323 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
324 struct cris_unwind_cache
*info
;
332 return (*this_cache
);
334 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
335 (*this_cache
) = info
;
336 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
338 /* Zero all fields. */
344 info
->uses_frame
= 0;
346 info
->leaf_function
= 0;
348 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
349 info
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
351 addr
= cris_sigcontext_addr (this_frame
);
353 /* Layout of the sigcontext struct:
356 unsigned long oldmask;
360 if (tdep
->cris_version
== 10)
362 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
364 for (i
= 0; i
<= 13; i
++)
365 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
367 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
368 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
369 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
370 /* Note: IRP is off by 2 at this point. There's no point in correcting
371 it though since that will mean that the backtrace will show a PC
372 different from what is shown when stopped. */
373 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
374 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
375 = info
->saved_regs
[IRP_REGNUM
];
376 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
= addr
+ (24 * 4);
381 /* R0 to R13 are stored in order at offset (1 * 4) in
383 for (i
= 0; i
<= 13; i
++)
384 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
386 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
387 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
388 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
389 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
390 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
391 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
392 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
393 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
394 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
396 /* FIXME: If ERP is in a delay slot at this point then the PC will
397 be wrong at this point. This problem manifests itself in the
398 sigaltstack.exp test case, which occasionally generates FAILs when
399 the signal is received while in a delay slot.
401 This could be solved by a couple of read_memory_unsigned_integer and a
402 trad_frame_set_value. */
403 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
404 = info
->saved_regs
[ERP_REGNUM
];
406 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
414 cris_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
415 struct frame_id
*this_id
)
417 struct cris_unwind_cache
*cache
=
418 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
419 (*this_id
) = frame_id_build (cache
->base
, get_frame_pc (this_frame
));
422 /* Forward declaration. */
424 static struct value
*cris_frame_prev_register (struct frame_info
*this_frame
,
425 void **this_cache
, int regnum
);
426 static struct value
*
427 cris_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
428 void **this_cache
, int regnum
)
430 /* Make sure we've initialized the cache. */
431 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
432 return cris_frame_prev_register (this_frame
, this_cache
, regnum
);
436 cris_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
437 struct frame_info
*this_frame
,
440 if (cris_sigtramp_start (this_frame
)
441 || cris_rt_sigtramp_start (this_frame
))
447 static const struct frame_unwind cris_sigtramp_frame_unwind
=
450 default_frame_unwind_stop_reason
,
451 cris_sigtramp_frame_this_id
,
452 cris_sigtramp_frame_prev_register
,
454 cris_sigtramp_frame_sniffer
458 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
459 struct frame_info
*this_frame
)
461 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
465 if (tdep
->cris_mode
== cris_mode_guru
)
466 erp
= get_frame_register_unsigned (this_frame
, NRP_REGNUM
);
468 erp
= get_frame_register_unsigned (this_frame
, ERP_REGNUM
);
472 /* In delay slot - check if there's a breakpoint at the preceding
474 if (breakpoint_here_p (get_frame_address_space (this_frame
), erp
& ~0x1))
480 /* Hardware watchpoint support. */
482 /* We support 6 hardware data watchpoints, but cannot trigger on execute
483 (any combination of read/write is fine). */
486 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
488 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
490 /* No bookkeeping is done here; it is handled by the remote debug agent. */
492 if (tdep
->cris_version
!= 32)
495 /* CRISv32: Six data watchpoints, one for instructions. */
496 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
497 || type
== bp_hardware_watchpoint
) && count
<= 6)
498 || (type
== bp_hardware_breakpoint
&& count
<= 1));
501 /* The CRISv32 hardware data watchpoints work by specifying ranges,
502 which have no alignment or length restrictions. */
505 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
510 /* If the inferior has some watchpoint that triggered, return the
511 address associated with that watchpoint. Otherwise, return
515 cris_stopped_data_address (void)
518 eda
= get_frame_register_unsigned (get_current_frame (), EDA_REGNUM
);
522 /* The instruction environment needed to find single-step breakpoints. */
525 struct instruction_environment
527 unsigned long reg
[NUM_GENREGS
];
528 unsigned long preg
[NUM_SPECREGS
];
529 unsigned long branch_break_address
;
530 unsigned long delay_slot_pc
;
531 unsigned long prefix_value
;
536 int delay_slot_pc_active
;
538 int disable_interrupt
;
542 /* Machine-dependencies in CRIS for opcodes. */
544 /* Instruction sizes. */
545 enum cris_instruction_sizes
552 /* Addressing modes. */
553 enum cris_addressing_modes
560 /* Prefix addressing modes. */
561 enum cris_prefix_addressing_modes
563 PREFIX_INDEX_MODE
= 2,
564 PREFIX_ASSIGN_MODE
= 3,
566 /* Handle immediate byte offset addressing mode prefix format. */
567 PREFIX_OFFSET_MODE
= 2
570 /* Masks for opcodes. */
571 enum cris_opcode_masks
573 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
574 SIGNED_EXTEND_BIT_MASK
= 0x2,
575 SIGNED_BYTE_MASK
= 0x80,
576 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
577 SIGNED_WORD_MASK
= 0x8000,
578 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
579 SIGNED_DWORD_MASK
= 0x80000000,
580 SIGNED_QUICK_VALUE_MASK
= 0x20,
581 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
584 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
592 cris_get_operand2 (unsigned short insn
)
594 return ((insn
& 0xF000) >> 12);
598 cris_get_mode (unsigned short insn
)
600 return ((insn
& 0x0C00) >> 10);
604 cris_get_opcode (unsigned short insn
)
606 return ((insn
& 0x03C0) >> 6);
610 cris_get_size (unsigned short insn
)
612 return ((insn
& 0x0030) >> 4);
616 cris_get_operand1 (unsigned short insn
)
618 return (insn
& 0x000F);
621 /* Additional functions in order to handle opcodes. */
624 cris_get_quick_value (unsigned short insn
)
626 return (insn
& 0x003F);
630 cris_get_bdap_quick_offset (unsigned short insn
)
632 return (insn
& 0x00FF);
636 cris_get_branch_short_offset (unsigned short insn
)
638 return (insn
& 0x00FF);
642 cris_get_asr_shift_steps (unsigned long value
)
644 return (value
& 0x3F);
648 cris_get_clear_size (unsigned short insn
)
650 return ((insn
) & 0xC000);
654 cris_is_signed_extend_bit_on (unsigned short insn
)
656 return (((insn
) & 0x20) == 0x20);
660 cris_is_xflag_bit_on (unsigned short insn
)
662 return (((insn
) & 0x1000) == 0x1000);
666 cris_set_size_to_dword (unsigned short *insn
)
673 cris_get_signed_offset (unsigned short insn
)
675 return ((signed char) (insn
& 0x00FF));
678 /* Calls an op function given the op-type, working on the insn and the
680 static void cris_gdb_func (struct gdbarch
*, enum cris_op_type
, unsigned short,
683 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
684 struct gdbarch_list
*);
686 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
688 static void set_cris_version (char *ignore_args
, int from_tty
,
689 struct cmd_list_element
*c
);
691 static void set_cris_mode (char *ignore_args
, int from_tty
,
692 struct cmd_list_element
*c
);
694 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
695 struct cmd_list_element
*c
);
697 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
698 struct frame_info
*this_frame
,
699 struct cris_unwind_cache
*info
);
701 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
702 struct frame_info
*this_frame
,
703 struct cris_unwind_cache
*info
);
705 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
706 struct frame_info
*next_frame
);
708 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
709 struct frame_info
*next_frame
);
711 /* When arguments must be pushed onto the stack, they go on in reverse
712 order. The below implements a FILO (stack) to do this.
713 Copied from d10v-tdep.c. */
718 struct stack_item
*prev
;
722 static struct stack_item
*
723 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
725 struct stack_item
*si
;
726 si
= xmalloc (sizeof (struct stack_item
));
727 si
->data
= xmalloc (len
);
730 memcpy (si
->data
, contents
, len
);
734 static struct stack_item
*
735 pop_stack_item (struct stack_item
*si
)
737 struct stack_item
*dead
= si
;
744 /* Put here the code to store, into fi->saved_regs, the addresses of
745 the saved registers of frame described by FRAME_INFO. This
746 includes special registers such as pc and fp saved in special ways
747 in the stack frame. sp is even more special: the address we return
748 for it IS the sp for the next frame. */
750 static struct cris_unwind_cache
*
751 cris_frame_unwind_cache (struct frame_info
*this_frame
,
752 void **this_prologue_cache
)
754 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
757 struct cris_unwind_cache
*info
;
760 if ((*this_prologue_cache
))
761 return (*this_prologue_cache
);
763 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
764 (*this_prologue_cache
) = info
;
765 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
767 /* Zero all fields. */
773 info
->uses_frame
= 0;
775 info
->leaf_function
= 0;
777 /* Prologue analysis does the rest... */
778 if (tdep
->cris_version
== 32)
779 crisv32_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
781 cris_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
786 /* Given a GDB frame, determine the address of the calling function's
787 frame. This will be used to create a new GDB frame struct. */
790 cris_frame_this_id (struct frame_info
*this_frame
,
791 void **this_prologue_cache
,
792 struct frame_id
*this_id
)
794 struct cris_unwind_cache
*info
795 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
800 /* The FUNC is easy. */
801 func
= get_frame_func (this_frame
);
803 /* Hopefully the prologue analysis either correctly determined the
804 frame's base (which is the SP from the previous frame), or set
805 that base to "NULL". */
806 base
= info
->prev_sp
;
810 id
= frame_id_build (base
, func
);
815 static struct value
*
816 cris_frame_prev_register (struct frame_info
*this_frame
,
817 void **this_prologue_cache
, int regnum
)
819 struct cris_unwind_cache
*info
820 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
821 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
824 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
825 frame. The frame ID's base needs to match the TOS value saved by
826 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
828 static struct frame_id
829 cris_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
832 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
833 return frame_id_build (sp
, get_frame_pc (this_frame
));
837 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
839 /* Align to the size of an instruction (so that they can safely be
840 pushed onto the stack). */
845 cris_push_dummy_code (struct gdbarch
*gdbarch
,
846 CORE_ADDR sp
, CORE_ADDR funaddr
,
847 struct value
**args
, int nargs
,
848 struct type
*value_type
,
849 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
850 struct regcache
*regcache
)
852 /* Allocate space sufficient for a breakpoint. */
854 /* Store the address of that breakpoint */
856 /* CRIS always starts the call at the callee's entry point. */
862 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
863 struct regcache
*regcache
, CORE_ADDR bp_addr
,
864 int nargs
, struct value
**args
, CORE_ADDR sp
,
865 int struct_return
, CORE_ADDR struct_addr
)
867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 /* The function's arguments and memory allocated by gdb for the arguments to
876 point at reside in separate areas on the stack.
877 Both frame pointers grow toward higher addresses. */
881 struct stack_item
*si
= NULL
;
883 /* Push the return address. */
884 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
886 /* Are we returning a value using a structure return or a normal value
887 return? struct_addr is the address of the reserved space for the return
888 structure to be written on the stack. */
891 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
894 /* Now load as many as possible of the first arguments into registers,
895 and push the rest onto the stack. */
896 argreg
= ARG1_REGNUM
;
899 for (argnum
= 0; argnum
< nargs
; argnum
++)
906 len
= TYPE_LENGTH (value_type (args
[argnum
]));
907 val
= (char *) value_contents (args
[argnum
]);
909 /* How may registers worth of storage do we need for this argument? */
910 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
912 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
914 /* Data passed by value. Fits in available register(s). */
915 for (i
= 0; i
< reg_demand
; i
++)
917 regcache_cooked_write (regcache
, argreg
, val
);
922 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
924 /* Data passed by value. Does not fit in available register(s).
925 Use the register(s) first, then the stack. */
926 for (i
= 0; i
< reg_demand
; i
++)
928 if (argreg
<= ARG4_REGNUM
)
930 regcache_cooked_write (regcache
, argreg
, val
);
936 /* Push item for later so that pushed arguments
937 come in the right order. */
938 si
= push_stack_item (si
, val
, 4);
943 else if (len
> (2 * 4))
945 /* Data passed by reference. Push copy of data onto stack
946 and pass pointer to this copy as argument. */
947 sp
= (sp
- len
) & ~3;
948 write_memory (sp
, val
, len
);
950 if (argreg
<= ARG4_REGNUM
)
952 regcache_cooked_write_unsigned (regcache
, argreg
, sp
);
958 store_unsigned_integer (buf
, 4, byte_order
, sp
);
959 si
= push_stack_item (si
, buf
, 4);
964 /* Data passed by value. No available registers. Put it on
966 si
= push_stack_item (si
, val
, len
);
972 /* fp_arg must be word-aligned (i.e., don't += len) to match
973 the function prologue. */
974 sp
= (sp
- si
->len
) & ~3;
975 write_memory (sp
, si
->data
, si
->len
);
976 si
= pop_stack_item (si
);
979 /* Finally, update the SP register. */
980 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
985 static const struct frame_unwind cris_frame_unwind
=
988 default_frame_unwind_stop_reason
,
990 cris_frame_prev_register
,
992 default_frame_sniffer
996 cris_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
998 struct cris_unwind_cache
*info
999 = cris_frame_unwind_cache (this_frame
, this_cache
);
1003 static const struct frame_base cris_frame_base
=
1006 cris_frame_base_address
,
1007 cris_frame_base_address
,
1008 cris_frame_base_address
1011 /* Frames information. The definition of the struct frame_info is
1015 enum frame_type type;
1019 If the compilation option -fno-omit-frame-pointer is present the
1020 variable frame will be set to the content of R8 which is the frame
1023 The variable pc contains the address where execution is performed
1024 in the present frame. The innermost frame contains the current content
1025 of the register PC. All other frames contain the content of the
1026 register PC in the next frame.
1028 The variable `type' indicates the frame's type: normal, SIGTRAMP
1029 (associated with a signal handler), dummy (associated with a dummy
1032 The variable return_pc contains the address where execution should be
1033 resumed when the present frame has finished, the return address.
1035 The variable leaf_function is 1 if the return address is in the register
1036 SRP, and 0 if it is on the stack.
1038 Prologue instructions C-code.
1039 The prologue may consist of (-fno-omit-frame-pointer)
1043 move.d sp,r8 move.d sp,r8
1045 movem rY,[sp] movem rY,[sp]
1046 move.S rZ,[r8-U] move.S rZ,[r8-U]
1048 where 1 is a non-terminal function, and 2 is a leaf-function.
1050 Note that this assumption is extremely brittle, and will break at the
1051 slightest change in GCC's prologue.
1053 If local variables are declared or register contents are saved on stack
1054 the subq-instruction will be present with X as the number of bytes
1055 needed for storage. The reshuffle with respect to r8 may be performed
1056 with any size S (b, w, d) and any of the general registers Z={0..13}.
1057 The offset U should be representable by a signed 8-bit value in all cases.
1058 Thus, the prefix word is assumed to be immediate byte offset mode followed
1059 by another word containing the instruction.
1068 Prologue instructions C++-code.
1069 Case 1) and 2) in the C-code may be followed by
1071 move.d r10,rS ; this
1075 move.S [r8+U],rZ ; P4
1077 if any of the call parameters are stored. The host expects these
1078 instructions to be executed in order to get the call parameters right. */
1080 /* Examine the prologue of a function. The variable ip is the address of
1081 the first instruction of the prologue. The variable limit is the address
1082 of the first instruction after the prologue. The variable fi contains the
1083 information in struct frame_info. The variable frameless_p controls whether
1084 the entire prologue is examined (0) or just enough instructions to
1085 determine that it is a prologue (1). */
1088 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1089 struct cris_unwind_cache
*info
)
1091 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1092 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1094 /* Present instruction. */
1095 unsigned short insn
;
1097 /* Next instruction, lookahead. */
1098 unsigned short insn_next
;
1101 /* Is there a push fp? */
1104 /* Number of byte on stack used for local variables and movem. */
1107 /* Highest register number in a movem. */
1110 /* move.d r<source_register>,rS */
1111 short source_register
;
1116 /* This frame is with respect to a leaf until a push srp is found. */
1119 info
->leaf_function
= 1;
1122 /* Assume nothing on stack. */
1126 /* If we were called without a this_frame, that means we were called
1127 from cris_skip_prologue which already tried to find the end of the
1128 prologue through the symbol information. 64 instructions past current
1129 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1130 limit
= this_frame
? get_frame_pc (this_frame
) : pc
+ 64;
1132 /* Find the prologue instructions. */
1133 while (pc
> 0 && pc
< limit
)
1135 insn
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1139 /* push <reg> 32 bit instruction. */
1140 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1142 regno
= cris_get_operand2 (insn_next
);
1145 info
->sp_offset
+= 4;
1147 /* This check, meant to recognize srp, used to be regno ==
1148 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1149 if (insn_next
== 0xBE7E)
1153 info
->leaf_function
= 0;
1156 else if (insn_next
== 0x8FEE)
1161 info
->r8_offset
= info
->sp_offset
;
1165 else if (insn
== 0x866E)
1170 info
->uses_frame
= 1;
1174 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1175 && cris_get_mode (insn
) == 0x0000
1176 && cris_get_opcode (insn
) == 0x000A)
1181 info
->sp_offset
+= cris_get_quick_value (insn
);
1184 else if (cris_get_mode (insn
) == 0x0002
1185 && cris_get_opcode (insn
) == 0x000F
1186 && cris_get_size (insn
) == 0x0003
1187 && cris_get_operand1 (insn
) == gdbarch_sp_regnum (gdbarch
))
1189 /* movem r<regsave>,[sp] */
1190 regsave
= cris_get_operand2 (insn
);
1192 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1193 && ((insn
& 0x0F00) >> 8) == 0x0001
1194 && (cris_get_signed_offset (insn
) < 0))
1196 /* Immediate byte offset addressing prefix word with sp as base
1197 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1198 is between 64 and 128.
1199 movem r<regsave>,[sp=sp-<val>] */
1202 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1204 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1206 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1207 && cris_get_opcode (insn_next
) == 0x000F
1208 && cris_get_size (insn_next
) == 0x0003
1209 && cris_get_operand1 (insn_next
) == gdbarch_sp_regnum
1212 regsave
= cris_get_operand2 (insn_next
);
1216 /* The prologue ended before the limit was reached. */
1221 else if (cris_get_mode (insn
) == 0x0001
1222 && cris_get_opcode (insn
) == 0x0009
1223 && cris_get_size (insn
) == 0x0002)
1225 /* move.d r<10..13>,r<0..15> */
1226 source_register
= cris_get_operand1 (insn
);
1228 /* FIXME? In the glibc solibs, the prologue might contain something
1229 like (this example taken from relocate_doit):
1231 sub.d 0xfffef426,$r0
1232 which isn't covered by the source_register check below. Question
1233 is whether to add a check for this combo, or make better use of
1234 the limit variable instead. */
1235 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1237 /* The prologue ended before the limit was reached. */
1242 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1243 /* The size is a fixed-size. */
1244 && ((insn
& 0x0F00) >> 8) == 0x0001
1245 /* A negative offset. */
1246 && (cris_get_signed_offset (insn
) < 0))
1248 /* move.S rZ,[r8-U] (?) */
1249 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1251 regno
= cris_get_operand2 (insn_next
);
1252 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1253 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1254 && cris_get_opcode (insn_next
) == 0x000F)
1256 /* move.S rZ,[r8-U] */
1261 /* The prologue ended before the limit was reached. */
1266 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1267 /* The size is a fixed-size. */
1268 && ((insn
& 0x0F00) >> 8) == 0x0001
1269 /* A positive offset. */
1270 && (cris_get_signed_offset (insn
) > 0))
1272 /* move.S [r8+U],rZ (?) */
1273 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1275 regno
= cris_get_operand2 (insn_next
);
1276 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1277 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1278 && cris_get_opcode (insn_next
) == 0x0009
1279 && cris_get_operand1 (insn_next
) == regno
)
1281 /* move.S [r8+U],rZ */
1286 /* The prologue ended before the limit was reached. */
1293 /* The prologue ended before the limit was reached. */
1299 /* We only want to know the end of the prologue when this_frame and info
1300 are NULL (called from cris_skip_prologue i.e.). */
1301 if (this_frame
== NULL
&& info
== NULL
)
1306 info
->size
= info
->sp_offset
;
1308 /* Compute the previous frame's stack pointer (which is also the
1309 frame's ID's stack address), and this frame's base pointer. */
1310 if (info
->uses_frame
)
1313 /* The SP was moved to the FP. This indicates that a new frame
1314 was created. Get THIS frame's FP value by unwinding it from
1316 this_base
= get_frame_register_unsigned (this_frame
, CRIS_FP_REGNUM
);
1317 info
->base
= this_base
;
1318 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1320 /* The FP points at the last saved register. Adjust the FP back
1321 to before the first saved register giving the SP. */
1322 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1327 /* Assume that the FP is this frame's SP but with that pushed
1328 stack space added back. */
1329 this_base
= get_frame_register_unsigned (this_frame
,
1330 gdbarch_sp_regnum (gdbarch
));
1331 info
->base
= this_base
;
1332 info
->prev_sp
= info
->base
+ info
->size
;
1335 /* Calculate the addresses for the saved registers on the stack. */
1336 /* FIXME: The address calculation should really be done on the fly while
1337 we're analyzing the prologue (we only hold one regsave value as it is
1339 val
= info
->sp_offset
;
1341 for (regno
= regsave
; regno
>= 0; regno
--)
1343 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1347 /* The previous frame's SP needed to be computed. Save the computed
1349 trad_frame_set_value (info
->saved_regs
,
1350 gdbarch_sp_regnum (gdbarch
), info
->prev_sp
);
1352 if (!info
->leaf_function
)
1354 /* SRP saved on the stack. But where? */
1355 if (info
->r8_offset
== 0)
1357 /* R8 not pushed yet. */
1358 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1362 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1363 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1367 /* The PC is found in SRP (the actual register or located on the stack). */
1368 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1369 = info
->saved_regs
[SRP_REGNUM
];
1375 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1376 struct cris_unwind_cache
*info
)
1378 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1381 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1382 meant to be a full-fledged prologue scanner. It is only needed for
1383 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1385 * PLT stubs (library calls)
1387 * signal trampolines
1389 For those cases, it is assumed that there is no actual prologue; that
1390 the stack pointer is not adjusted, and (as a consequence) the return
1391 address is not pushed onto the stack. */
1393 /* We only want to know the end of the prologue when this_frame and info
1394 are NULL (called from cris_skip_prologue i.e.). */
1395 if (this_frame
== NULL
&& info
== NULL
)
1400 /* The SP is assumed to be unaltered. */
1401 this_base
= get_frame_register_unsigned (this_frame
,
1402 gdbarch_sp_regnum (gdbarch
));
1403 info
->base
= this_base
;
1404 info
->prev_sp
= this_base
;
1406 /* The PC is assumed to be found in SRP. */
1407 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1408 = info
->saved_regs
[SRP_REGNUM
];
1413 /* Advance pc beyond any function entry prologue instructions at pc
1414 to reach some "real" code. */
1416 /* Given a PC value corresponding to the start of a function, return the PC
1417 of the first instruction after the function prologue. */
1420 cris_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1423 CORE_ADDR func_addr
, func_end
;
1424 struct symtab_and_line sal
;
1425 CORE_ADDR pc_after_prologue
;
1427 /* If we have line debugging information, then the end of the prologue
1428 should the first assembly instruction of the first source line. */
1429 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1431 sal
= find_pc_line (func_addr
, 0);
1432 if (sal
.end
> 0 && sal
.end
< func_end
)
1436 if (tdep
->cris_version
== 32)
1437 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1439 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1441 return pc_after_prologue
;
1445 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1448 pc
= frame_unwind_register_unsigned (next_frame
,
1449 gdbarch_pc_regnum (gdbarch
));
1454 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1457 sp
= frame_unwind_register_unsigned (next_frame
,
1458 gdbarch_sp_regnum (gdbarch
));
1462 /* Use the program counter to determine the contents and size of a breakpoint
1463 instruction. It returns a pointer to a string of bytes that encode a
1464 breakpoint instruction, stores the length of the string to *lenptr, and
1465 adjusts pcptr (if necessary) to point to the actual memory location where
1466 the breakpoint should be inserted. */
1468 static const unsigned char *
1469 cris_breakpoint_from_pc (struct gdbarch
*gdbarch
,
1470 CORE_ADDR
*pcptr
, int *lenptr
)
1472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1473 static unsigned char break8_insn
[] = {0x38, 0xe9};
1474 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1477 if (tdep
->cris_mode
== cris_mode_guru
)
1478 return break15_insn
;
1483 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1487 cris_spec_reg_applicable (struct gdbarch
*gdbarch
,
1488 struct cris_spec_reg spec_reg
)
1490 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1491 int version
= tdep
->cris_version
;
1493 switch (spec_reg
.applicable_version
)
1495 case cris_ver_version_all
:
1497 case cris_ver_warning
:
1498 /* Indeterminate/obsolete. */
1501 return (version
>= 0 && version
<= 3);
1503 return (version
>= 3);
1505 return (version
== 8 || version
== 9);
1507 return (version
>= 8);
1508 case cris_ver_v0_10
:
1509 return (version
>= 0 && version
<= 10);
1510 case cris_ver_v3_10
:
1511 return (version
>= 3 && version
<= 10);
1512 case cris_ver_v8_10
:
1513 return (version
>= 8 && version
<= 10);
1515 return (version
== 10);
1517 return (version
>= 10);
1519 return (version
>= 32);
1521 /* Invalid cris version. */
1526 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1527 register, -1 for an invalid register. */
1530 cris_register_size (struct gdbarch
*gdbarch
, int regno
)
1532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1536 if (regno
>= 0 && regno
< NUM_GENREGS
)
1538 /* General registers (R0 - R15) are 32 bits. */
1541 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1543 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1544 Adjust regno accordingly. */
1545 spec_regno
= regno
- NUM_GENREGS
;
1547 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1549 if (cris_spec_regs
[i
].number
== spec_regno
1550 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1551 /* Go with the first applicable register. */
1552 return cris_spec_regs
[i
].reg_size
;
1554 /* Special register not applicable to this CRIS version. */
1557 else if (regno
>= gdbarch_pc_regnum (gdbarch
)
1558 && regno
< gdbarch_num_regs (gdbarch
))
1560 /* This will apply to CRISv32 only where there are additional registers
1561 after the special registers (pseudo PC and support registers). */
1569 /* Nonzero if regno should not be fetched from the target. This is the case
1570 for unimplemented (size 0) and non-existant registers. */
1573 cris_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1575 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1576 || (cris_register_size (gdbarch
, regno
) == 0));
1579 /* Nonzero if regno should not be written to the target, for various
1583 cris_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1585 /* There are three kinds of registers we refuse to write to.
1586 1. Those that not implemented.
1587 2. Those that are read-only (depends on the processor mode).
1588 3. Those registers to which a write has no effect. */
1591 || regno
>= gdbarch_num_regs (gdbarch
)
1592 || cris_register_size (gdbarch
, regno
) == 0)
1593 /* Not implemented. */
1596 else if (regno
== VR_REGNUM
)
1600 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1601 /* Writing has no effect. */
1604 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1605 agent decide whether they are writable. */
1610 /* Nonzero if regno should not be fetched from the target. This is the case
1611 for unimplemented (size 0) and non-existant registers. */
1614 crisv32_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1616 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1617 || (cris_register_size (gdbarch
, regno
) == 0));
1620 /* Nonzero if regno should not be written to the target, for various
1624 crisv32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1626 /* There are three kinds of registers we refuse to write to.
1627 1. Those that not implemented.
1628 2. Those that are read-only (depends on the processor mode).
1629 3. Those registers to which a write has no effect. */
1632 || regno
>= gdbarch_num_regs (gdbarch
)
1633 || cris_register_size (gdbarch
, regno
) == 0)
1634 /* Not implemented. */
1637 else if (regno
== VR_REGNUM
)
1641 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1642 /* Writing has no effect. */
1645 /* Many special registers are read-only in user mode. Let the debug
1646 agent decide whether they are writable. */
1651 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1652 of data in register regno. */
1654 static struct type
*
1655 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1657 if (regno
== gdbarch_pc_regnum (gdbarch
))
1658 return builtin_type (gdbarch
)->builtin_func_ptr
;
1659 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1660 || regno
== CRIS_FP_REGNUM
)
1661 return builtin_type (gdbarch
)->builtin_data_ptr
;
1662 else if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1663 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1664 /* Note: R8 taken care of previous clause. */
1665 return builtin_type (gdbarch
)->builtin_uint32
;
1666 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1667 return builtin_type (gdbarch
)->builtin_uint16
;
1668 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1669 return builtin_type (gdbarch
)->builtin_uint8
;
1671 /* Invalid (unimplemented) register. */
1672 return builtin_type (gdbarch
)->builtin_int0
;
1675 static struct type
*
1676 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1678 if (regno
== gdbarch_pc_regnum (gdbarch
))
1679 return builtin_type (gdbarch
)->builtin_func_ptr
;
1680 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1681 || regno
== CRIS_FP_REGNUM
)
1682 return builtin_type (gdbarch
)->builtin_data_ptr
;
1683 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1684 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1685 || (regno
== PID_REGNUM
)
1686 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1687 /* Note: R8 and SP taken care of by previous clause. */
1688 return builtin_type (gdbarch
)->builtin_uint32
;
1689 else if (regno
== WZ_REGNUM
)
1690 return builtin_type (gdbarch
)->builtin_uint16
;
1691 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1692 return builtin_type (gdbarch
)->builtin_uint8
;
1695 /* Invalid (unimplemented) register. Should not happen as there are
1696 no unimplemented CRISv32 registers. */
1697 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1698 return builtin_type (gdbarch
)->builtin_int0
;
1702 /* Stores a function return value of type type, where valbuf is the address
1703 of the value to be stored. */
1705 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1708 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1711 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1712 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1714 int len
= TYPE_LENGTH (type
);
1718 /* Put the return value in R10. */
1719 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1720 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1724 /* Put the return value in R10 and R11. */
1725 val
= extract_unsigned_integer (valbuf
, 4, byte_order
);
1726 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1727 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4, byte_order
);
1728 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1731 error (_("cris_store_return_value: type length too large."));
1734 /* Return the name of register regno as a string. Return NULL for an
1735 invalid or unimplemented register. */
1738 cris_special_register_name (struct gdbarch
*gdbarch
, int regno
)
1743 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1744 Adjust regno accordingly. */
1745 spec_regno
= regno
- NUM_GENREGS
;
1747 /* Assume nothing about the layout of the cris_spec_regs struct
1749 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1751 if (cris_spec_regs
[i
].number
== spec_regno
1752 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1753 /* Go with the first applicable register. */
1754 return cris_spec_regs
[i
].name
;
1756 /* Special register not applicable to this CRIS version. */
1761 cris_register_name (struct gdbarch
*gdbarch
, int regno
)
1763 static char *cris_genreg_names
[] =
1764 { "r0", "r1", "r2", "r3", \
1765 "r4", "r5", "r6", "r7", \
1766 "r8", "r9", "r10", "r11", \
1767 "r12", "r13", "sp", "pc" };
1769 if (regno
>= 0 && regno
< NUM_GENREGS
)
1771 /* General register. */
1772 return cris_genreg_names
[regno
];
1774 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (gdbarch
))
1776 return cris_special_register_name (gdbarch
, regno
);
1780 /* Invalid register. */
1786 crisv32_register_name (struct gdbarch
*gdbarch
, int regno
)
1788 static char *crisv32_genreg_names
[] =
1789 { "r0", "r1", "r2", "r3", \
1790 "r4", "r5", "r6", "r7", \
1791 "r8", "r9", "r10", "r11", \
1792 "r12", "r13", "sp", "acr"
1795 static char *crisv32_sreg_names
[] =
1796 { "s0", "s1", "s2", "s3", \
1797 "s4", "s5", "s6", "s7", \
1798 "s8", "s9", "s10", "s11", \
1799 "s12", "s13", "s14", "s15"
1802 if (regno
>= 0 && regno
< NUM_GENREGS
)
1804 /* General register. */
1805 return crisv32_genreg_names
[regno
];
1807 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1809 return cris_special_register_name (gdbarch
, regno
);
1811 else if (regno
== gdbarch_pc_regnum (gdbarch
))
1815 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1817 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1821 /* Invalid register. */
1826 /* Convert DWARF register number REG to the appropriate register
1827 number used by GDB. */
1830 cris_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1832 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1833 numbering, MOF is 18).
1834 Adapted from gcc/config/cris/cris.h. */
1835 static int cris_dwarf_regmap
[] = {
1847 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1848 regnum
= cris_dwarf_regmap
[reg
];
1851 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
1856 /* DWARF-2 frame support. */
1859 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1860 struct dwarf2_frame_state_reg
*reg
,
1861 struct frame_info
*this_frame
)
1863 /* The return address column. */
1864 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1865 reg
->how
= DWARF2_FRAME_REG_RA
;
1867 /* The call frame address. */
1868 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1869 reg
->how
= DWARF2_FRAME_REG_CFA
;
1872 /* Extract from an array regbuf containing the raw register state a function
1873 return value of type type, and copy that, in virtual format, into
1876 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1879 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1882 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1885 int len
= TYPE_LENGTH (type
);
1889 /* Get the return value from R10. */
1890 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1891 store_unsigned_integer (valbuf
, len
, byte_order
, val
);
1895 /* Get the return value from R10 and R11. */
1896 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1897 store_unsigned_integer (valbuf
, 4, byte_order
, val
);
1898 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1899 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, byte_order
, val
);
1902 error (_("cris_extract_return_value: type length too large"));
1905 /* Handle the CRIS return value convention. */
1907 static enum return_value_convention
1908 cris_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1909 struct type
*type
, struct regcache
*regcache
,
1910 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1912 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1913 || TYPE_CODE (type
) == TYPE_CODE_UNION
1914 || TYPE_LENGTH (type
) > 8)
1915 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1916 goes on the stack. */
1917 return RETURN_VALUE_STRUCT_CONVENTION
;
1920 cris_extract_return_value (type
, regcache
, readbuf
);
1922 cris_store_return_value (type
, regcache
, writebuf
);
1924 return RETURN_VALUE_REGISTER_CONVENTION
;
1927 /* Calculates a value that measures how good inst_args constraints an
1928 instruction. It stems from cris_constraint, found in cris-dis.c. */
1931 constraint (unsigned int insn
, const signed char *inst_args
,
1932 inst_env_type
*inst_env
)
1937 const char *s
= inst_args
;
1943 if ((insn
& 0x30) == 0x30)
1948 /* A prefix operand. */
1949 if (inst_env
->prefix_found
)
1955 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1956 valid "push" size. In case of special register, it may be != 4. */
1957 if (inst_env
->prefix_found
)
1963 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1971 tmp
= (insn
>> 0xC) & 0xF;
1973 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1975 /* Since we match four bits, we will give a value of
1976 4 - 1 = 3 in a match. If there is a corresponding
1977 exact match of a special register in another pattern, it
1978 will get a value of 4, which will be higher. This should
1979 be correct in that an exact pattern would match better that
1981 Note that there is a reason for not returning zero; the
1982 pattern for "clear" is partly matched in the bit-pattern
1983 (the two lower bits must be zero), while the bit-pattern
1984 for a move from a special register is matched in the
1985 register constraint.
1986 This also means we will will have a race condition if
1987 there is a partly match in three bits in the bit pattern. */
1988 if (tmp
== cris_spec_regs
[i
].number
)
1995 if (cris_spec_regs
[i
].name
== NULL
)
2002 /* Returns the number of bits set in the variable value. */
2005 number_of_bits (unsigned int value
)
2007 int number_of_bits
= 0;
2011 number_of_bits
+= 1;
2012 value
&= (value
- 1);
2014 return number_of_bits
;
2017 /* Finds the address that should contain the single step breakpoint(s).
2018 It stems from code in cris-dis.c. */
2021 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
2024 int max_level_of_match
= -1;
2025 int max_matched
= -1;
2028 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
2030 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
2031 && ((cris_opcodes
[i
].lose
& insn
) == 0)
2032 /* Only CRISv10 instructions, please. */
2033 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
2035 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
2036 if (level_of_match
>= 0)
2039 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
2040 if (level_of_match
> max_level_of_match
)
2043 max_level_of_match
= level_of_match
;
2044 if (level_of_match
== 16)
2046 /* All bits matched, cannot find better. */
2056 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2057 actually an internal error. */
2060 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
2064 unsigned short insn
;
2065 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2066 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2068 /* Create a local register image and set the initial state. */
2069 for (i
= 0; i
< NUM_GENREGS
; i
++)
2072 (unsigned long) get_frame_register_unsigned (frame
, i
);
2074 offset
= NUM_GENREGS
;
2075 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2078 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2080 inst_env
->branch_found
= 0;
2081 inst_env
->slot_needed
= 0;
2082 inst_env
->delay_slot_pc_active
= 0;
2083 inst_env
->prefix_found
= 0;
2084 inst_env
->invalid
= 0;
2085 inst_env
->xflag_found
= 0;
2086 inst_env
->disable_interrupt
= 0;
2087 inst_env
->byte_order
= byte_order
;
2089 /* Look for a step target. */
2092 /* Read an instruction from the client. */
2093 insn
= read_memory_unsigned_integer
2094 (inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)], 2, byte_order
);
2096 /* If the instruction is not in a delay slot the new content of the
2097 PC is [PC] + 2. If the instruction is in a delay slot it is not
2098 that simple. Since a instruction in a delay slot cannot change
2099 the content of the PC, it does not matter what value PC will have.
2100 Just make sure it is a valid instruction. */
2101 if (!inst_env
->delay_slot_pc_active
)
2103 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)] += 2;
2107 inst_env
->delay_slot_pc_active
= 0;
2108 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)]
2109 = inst_env
->delay_slot_pc
;
2111 /* Analyse the present instruction. */
2112 i
= find_cris_op (insn
, inst_env
);
2115 inst_env
->invalid
= 1;
2119 cris_gdb_func (gdbarch
, cris_opcodes
[i
].op
, insn
, inst_env
);
2121 } while (!inst_env
->invalid
2122 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2123 || inst_env
->slot_needed
));
2127 /* There is no hardware single-step support. The function find_step_target
2128 digs through the opcodes in order to find all possible targets.
2129 Either one ordinary target or two targets for branches may be found. */
2132 cris_software_single_step (struct frame_info
*frame
)
2134 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2135 struct address_space
*aspace
= get_frame_address_space (frame
);
2136 inst_env_type inst_env
;
2138 /* Analyse the present instruction environment and insert
2140 int status
= find_step_target (frame
, &inst_env
);
2143 /* Could not find a target. Things are likely to go downhill
2145 warning (_("CRIS software single step could not find a step target."));
2149 /* Insert at most two breakpoints. One for the next PC content
2150 and possibly another one for a branch, jump, etc. */
2152 = (CORE_ADDR
) inst_env
.reg
[gdbarch_pc_regnum (gdbarch
)];
2153 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2154 if (inst_env
.branch_found
2155 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2157 CORE_ADDR branch_target_address
2158 = (CORE_ADDR
) inst_env
.branch_break_address
;
2159 insert_single_step_breakpoint (gdbarch
,
2160 aspace
, branch_target_address
);
2167 /* Calculates the prefix value for quick offset addressing mode. */
2170 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2172 /* It's invalid to be in a delay slot. You can't have a prefix to this
2173 instruction (not 100% sure). */
2174 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2176 inst_env
->invalid
= 1;
2180 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2181 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2183 /* A prefix doesn't change the xflag_found. But the rest of the flags
2185 inst_env
->slot_needed
= 0;
2186 inst_env
->prefix_found
= 1;
2189 /* Updates the autoincrement register. The size of the increment is derived
2190 from the size of the operation. The PC is always kept aligned on even
2194 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2196 if (size
== INST_BYTE_SIZE
)
2198 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2200 /* The PC must be word aligned, so increase the PC with one
2201 word even if the size is byte. */
2202 if (cris_get_operand1 (inst
) == REG_PC
)
2204 inst_env
->reg
[REG_PC
] += 1;
2207 else if (size
== INST_WORD_SIZE
)
2209 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2211 else if (size
== INST_DWORD_SIZE
)
2213 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2218 inst_env
->invalid
= 1;
2222 /* Just a forward declaration. */
2224 static unsigned long get_data_from_address (unsigned short *inst
,
2226 enum bfd_endian byte_order
);
2228 /* Calculates the prefix value for the general case of offset addressing
2232 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2237 /* It's invalid to be in a delay slot. */
2238 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2240 inst_env
->invalid
= 1;
2244 /* The calculation of prefix_value used to be after process_autoincrement,
2245 but that fails for an instruction such as jsr [$r0+12] which is encoded
2246 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2247 mustn't be incremented until we have read it and what it points at. */
2248 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2250 /* The offset is an indirection of the contents of the operand1 register. */
2251 inst_env
->prefix_value
+=
2252 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)],
2253 inst_env
->byte_order
);
2255 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2257 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2260 /* A prefix doesn't change the xflag_found. But the rest of the flags
2262 inst_env
->slot_needed
= 0;
2263 inst_env
->prefix_found
= 1;
2266 /* Calculates the prefix value for the index addressing mode. */
2269 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2271 /* It's invalid to be in a delay slot. I can't see that it's possible to
2272 have a prefix to this instruction. So I will treat this as invalid. */
2273 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2275 inst_env
->invalid
= 1;
2279 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2281 /* The offset is the operand2 value shifted the size of the instruction
2283 inst_env
->prefix_value
+=
2284 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2286 /* If the PC is operand1 (base) the address used is the address after
2287 the main instruction, i.e. address + 2 (the PC is already compensated
2288 for the prefix operation). */
2289 if (cris_get_operand1 (inst
) == REG_PC
)
2291 inst_env
->prefix_value
+= 2;
2294 /* A prefix doesn't change the xflag_found. But the rest of the flags
2296 inst_env
->slot_needed
= 0;
2297 inst_env
->xflag_found
= 0;
2298 inst_env
->prefix_found
= 1;
2301 /* Calculates the prefix value for the double indirect addressing mode. */
2304 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2309 /* It's invalid to be in a delay slot. */
2310 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2312 inst_env
->invalid
= 1;
2316 /* The prefix value is one dereference of the contents of the operand1
2318 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2319 inst_env
->prefix_value
2320 = read_memory_unsigned_integer (address
, 4, inst_env
->byte_order
);
2322 /* Check if the mode is autoincrement. */
2323 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2325 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2328 /* A prefix doesn't change the xflag_found. But the rest of the flags
2330 inst_env
->slot_needed
= 0;
2331 inst_env
->xflag_found
= 0;
2332 inst_env
->prefix_found
= 1;
2335 /* Finds the destination for a branch with 8-bits offset. */
2338 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2343 /* If we have a prefix or are in a delay slot it's bad. */
2344 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2346 inst_env
->invalid
= 1;
2350 /* We have a branch, find out where the branch will land. */
2351 offset
= cris_get_branch_short_offset (inst
);
2353 /* Check if the offset is signed. */
2354 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2359 /* The offset ends with the sign bit, set it to zero. The address
2360 should always be word aligned. */
2361 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2363 inst_env
->branch_found
= 1;
2364 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2366 inst_env
->slot_needed
= 1;
2367 inst_env
->prefix_found
= 0;
2368 inst_env
->xflag_found
= 0;
2369 inst_env
->disable_interrupt
= 1;
2372 /* Finds the destination for a branch with 16-bits offset. */
2375 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2379 /* If we have a prefix or is in a delay slot it's bad. */
2380 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2382 inst_env
->invalid
= 1;
2386 /* We have a branch, find out the offset for the branch. */
2387 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2,
2388 inst_env
->byte_order
);
2390 /* The instruction is one word longer than normal, so add one word
2392 inst_env
->reg
[REG_PC
] += 2;
2394 inst_env
->branch_found
= 1;
2395 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2398 inst_env
->slot_needed
= 1;
2399 inst_env
->prefix_found
= 0;
2400 inst_env
->xflag_found
= 0;
2401 inst_env
->disable_interrupt
= 1;
2404 /* Handles the ABS instruction. */
2407 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2412 /* ABS can't have a prefix, so it's bad if it does. */
2413 if (inst_env
->prefix_found
)
2415 inst_env
->invalid
= 1;
2419 /* Check if the operation affects the PC. */
2420 if (cris_get_operand2 (inst
) == REG_PC
)
2423 /* It's invalid to change to the PC if we are in a delay slot. */
2424 if (inst_env
->slot_needed
)
2426 inst_env
->invalid
= 1;
2430 value
= (long) inst_env
->reg
[REG_PC
];
2432 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2433 if (value
!= SIGNED_DWORD_MASK
)
2436 inst_env
->reg
[REG_PC
] = (long) value
;
2440 inst_env
->slot_needed
= 0;
2441 inst_env
->prefix_found
= 0;
2442 inst_env
->xflag_found
= 0;
2443 inst_env
->disable_interrupt
= 0;
2446 /* Handles the ADDI instruction. */
2449 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2451 /* It's invalid to have the PC as base register. And ADDI can't have
2453 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2455 inst_env
->invalid
= 1;
2459 inst_env
->slot_needed
= 0;
2460 inst_env
->prefix_found
= 0;
2461 inst_env
->xflag_found
= 0;
2462 inst_env
->disable_interrupt
= 0;
2465 /* Handles the ASR instruction. */
2468 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2471 unsigned long value
;
2472 unsigned long signed_extend_mask
= 0;
2474 /* ASR can't have a prefix, so check that it doesn't. */
2475 if (inst_env
->prefix_found
)
2477 inst_env
->invalid
= 1;
2481 /* Check if the PC is the target register. */
2482 if (cris_get_operand2 (inst
) == REG_PC
)
2484 /* It's invalid to change the PC in a delay slot. */
2485 if (inst_env
->slot_needed
)
2487 inst_env
->invalid
= 1;
2490 /* Get the number of bits to shift. */
2492 = cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2493 value
= inst_env
->reg
[REG_PC
];
2495 /* Find out how many bits the operation should apply to. */
2496 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2498 if (value
& SIGNED_BYTE_MASK
)
2500 signed_extend_mask
= 0xFF;
2501 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2502 signed_extend_mask
= ~signed_extend_mask
;
2504 value
= value
>> shift_steps
;
2505 value
|= signed_extend_mask
;
2507 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2508 inst_env
->reg
[REG_PC
] |= value
;
2510 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2512 if (value
& SIGNED_WORD_MASK
)
2514 signed_extend_mask
= 0xFFFF;
2515 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2516 signed_extend_mask
= ~signed_extend_mask
;
2518 value
= value
>> shift_steps
;
2519 value
|= signed_extend_mask
;
2521 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2522 inst_env
->reg
[REG_PC
] |= value
;
2524 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2526 if (value
& SIGNED_DWORD_MASK
)
2528 signed_extend_mask
= 0xFFFFFFFF;
2529 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2530 signed_extend_mask
= ~signed_extend_mask
;
2532 value
= value
>> shift_steps
;
2533 value
|= signed_extend_mask
;
2534 inst_env
->reg
[REG_PC
] = value
;
2537 inst_env
->slot_needed
= 0;
2538 inst_env
->prefix_found
= 0;
2539 inst_env
->xflag_found
= 0;
2540 inst_env
->disable_interrupt
= 0;
2543 /* Handles the ASRQ instruction. */
2546 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2550 unsigned long value
;
2551 unsigned long signed_extend_mask
= 0;
2553 /* ASRQ can't have a prefix, so check that it doesn't. */
2554 if (inst_env
->prefix_found
)
2556 inst_env
->invalid
= 1;
2560 /* Check if the PC is the target register. */
2561 if (cris_get_operand2 (inst
) == REG_PC
)
2564 /* It's invalid to change the PC in a delay slot. */
2565 if (inst_env
->slot_needed
)
2567 inst_env
->invalid
= 1;
2570 /* The shift size is given as a 5 bit quick value, i.e. we don't
2571 want the sign bit of the quick value. */
2572 shift_steps
= cris_get_asr_shift_steps (inst
);
2573 value
= inst_env
->reg
[REG_PC
];
2574 if (value
& SIGNED_DWORD_MASK
)
2576 signed_extend_mask
= 0xFFFFFFFF;
2577 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2578 signed_extend_mask
= ~signed_extend_mask
;
2580 value
= value
>> shift_steps
;
2581 value
|= signed_extend_mask
;
2582 inst_env
->reg
[REG_PC
] = value
;
2584 inst_env
->slot_needed
= 0;
2585 inst_env
->prefix_found
= 0;
2586 inst_env
->xflag_found
= 0;
2587 inst_env
->disable_interrupt
= 0;
2590 /* Handles the AX, EI and SETF instruction. */
2593 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2595 if (inst_env
->prefix_found
)
2597 inst_env
->invalid
= 1;
2600 /* Check if the instruction is setting the X flag. */
2601 if (cris_is_xflag_bit_on (inst
))
2603 inst_env
->xflag_found
= 1;
2607 inst_env
->xflag_found
= 0;
2609 inst_env
->slot_needed
= 0;
2610 inst_env
->prefix_found
= 0;
2611 inst_env
->disable_interrupt
= 1;
2614 /* Checks if the instruction is in assign mode. If so, it updates the assign
2615 register. Note that check_assign assumes that the caller has checked that
2616 there is a prefix to this instruction. The mode check depends on this. */
2619 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2621 /* Check if it's an assign addressing mode. */
2622 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2624 /* Assign the prefix value to operand 1. */
2625 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2629 /* Handles the 2-operand BOUND instruction. */
2632 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2634 /* It's invalid to have the PC as the index operand. */
2635 if (cris_get_operand2 (inst
) == REG_PC
)
2637 inst_env
->invalid
= 1;
2640 /* Check if we have a prefix. */
2641 if (inst_env
->prefix_found
)
2643 check_assign (inst
, inst_env
);
2645 /* Check if this is an autoincrement mode. */
2646 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2648 /* It's invalid to change the PC in a delay slot. */
2649 if (inst_env
->slot_needed
)
2651 inst_env
->invalid
= 1;
2654 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2656 inst_env
->slot_needed
= 0;
2657 inst_env
->prefix_found
= 0;
2658 inst_env
->xflag_found
= 0;
2659 inst_env
->disable_interrupt
= 0;
2662 /* Handles the 3-operand BOUND instruction. */
2665 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2667 /* It's an error if we haven't got a prefix. And it's also an error
2668 if the PC is the destination register. */
2669 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2671 inst_env
->invalid
= 1;
2674 inst_env
->slot_needed
= 0;
2675 inst_env
->prefix_found
= 0;
2676 inst_env
->xflag_found
= 0;
2677 inst_env
->disable_interrupt
= 0;
2680 /* Clears the status flags in inst_env. */
2683 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2685 /* It's an error if we have got a prefix. */
2686 if (inst_env
->prefix_found
)
2688 inst_env
->invalid
= 1;
2692 inst_env
->slot_needed
= 0;
2693 inst_env
->prefix_found
= 0;
2694 inst_env
->xflag_found
= 0;
2695 inst_env
->disable_interrupt
= 0;
2698 /* Clears the status flags in inst_env. */
2701 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2703 /* It's an error if we have got a prefix. */
2704 if (inst_env
->prefix_found
)
2706 inst_env
->invalid
= 1;
2710 inst_env
->slot_needed
= 0;
2711 inst_env
->prefix_found
= 0;
2712 inst_env
->xflag_found
= 0;
2713 inst_env
->disable_interrupt
= 1;
2716 /* Handles the CLEAR instruction if it's in register mode. */
2719 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2721 /* Check if the target is the PC. */
2722 if (cris_get_operand2 (inst
) == REG_PC
)
2724 /* The instruction will clear the instruction's size bits. */
2725 int clear_size
= cris_get_clear_size (inst
);
2726 if (clear_size
== INST_BYTE_SIZE
)
2728 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2730 if (clear_size
== INST_WORD_SIZE
)
2732 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2734 if (clear_size
== INST_DWORD_SIZE
)
2736 inst_env
->delay_slot_pc
= 0x0;
2738 /* The jump will be delayed with one delay slot. So we need a delay
2740 inst_env
->slot_needed
= 1;
2741 inst_env
->delay_slot_pc_active
= 1;
2745 /* The PC will not change => no delay slot. */
2746 inst_env
->slot_needed
= 0;
2748 inst_env
->prefix_found
= 0;
2749 inst_env
->xflag_found
= 0;
2750 inst_env
->disable_interrupt
= 0;
2753 /* Handles the TEST instruction if it's in register mode. */
2756 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2758 /* It's an error if we have got a prefix. */
2759 if (inst_env
->prefix_found
)
2761 inst_env
->invalid
= 1;
2764 inst_env
->slot_needed
= 0;
2765 inst_env
->prefix_found
= 0;
2766 inst_env
->xflag_found
= 0;
2767 inst_env
->disable_interrupt
= 0;
2771 /* Handles the CLEAR and TEST instruction if the instruction isn't
2772 in register mode. */
2775 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2777 /* Check if we are in a prefix mode. */
2778 if (inst_env
->prefix_found
)
2780 /* The only way the PC can change is if this instruction is in
2781 assign addressing mode. */
2782 check_assign (inst
, inst_env
);
2784 /* Indirect mode can't change the PC so just check if the mode is
2786 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2788 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2790 inst_env
->slot_needed
= 0;
2791 inst_env
->prefix_found
= 0;
2792 inst_env
->xflag_found
= 0;
2793 inst_env
->disable_interrupt
= 0;
2796 /* Checks that the PC isn't the destination register or the instructions has
2800 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2802 /* It's invalid to have the PC as the destination. The instruction can't
2804 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2806 inst_env
->invalid
= 1;
2810 inst_env
->slot_needed
= 0;
2811 inst_env
->prefix_found
= 0;
2812 inst_env
->xflag_found
= 0;
2813 inst_env
->disable_interrupt
= 0;
2816 /* Checks that the instruction doesn't have a prefix. */
2819 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2821 /* The instruction can't have a prefix. */
2822 if (inst_env
->prefix_found
)
2824 inst_env
->invalid
= 1;
2828 inst_env
->slot_needed
= 0;
2829 inst_env
->prefix_found
= 0;
2830 inst_env
->xflag_found
= 0;
2831 inst_env
->disable_interrupt
= 1;
2834 /* Checks that the PC isn't the destination register and that the instruction
2835 doesn't have a prefix. */
2838 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2840 /* It's invalid to have the PC as the destination. The instruction can't
2842 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2844 inst_env
->invalid
= 1;
2848 inst_env
->slot_needed
= 0;
2849 inst_env
->prefix_found
= 0;
2850 inst_env
->xflag_found
= 0;
2851 inst_env
->disable_interrupt
= 1;
2854 /* Handles the register mode JUMP instruction. */
2857 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2859 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2860 you can't have a prefix. */
2861 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2863 inst_env
->invalid
= 1;
2867 /* Just change the PC. */
2868 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2869 inst_env
->slot_needed
= 0;
2870 inst_env
->prefix_found
= 0;
2871 inst_env
->xflag_found
= 0;
2872 inst_env
->disable_interrupt
= 1;
2875 /* Handles the JUMP instruction for all modes except register. */
2878 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2880 unsigned long newpc
;
2883 /* It's invalid to do a JUMP in a delay slot. */
2884 if (inst_env
->slot_needed
)
2886 inst_env
->invalid
= 1;
2890 /* Check if we have a prefix. */
2891 if (inst_env
->prefix_found
)
2893 check_assign (inst
, inst_env
);
2895 /* Get the new value for the PC. */
2897 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2898 4, inst_env
->byte_order
);
2902 /* Get the new value for the PC. */
2903 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2904 newpc
= read_memory_unsigned_integer (address
,
2905 4, inst_env
->byte_order
);
2907 /* Check if we should increment a register. */
2908 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2910 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2913 inst_env
->reg
[REG_PC
] = newpc
;
2915 inst_env
->slot_needed
= 0;
2916 inst_env
->prefix_found
= 0;
2917 inst_env
->xflag_found
= 0;
2918 inst_env
->disable_interrupt
= 1;
2921 /* Handles moves to special registers (aka P-register) for all modes. */
2924 move_to_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2925 inst_env_type
*inst_env
)
2927 if (inst_env
->prefix_found
)
2929 /* The instruction has a prefix that means we are only interested if
2930 the instruction is in assign mode. */
2931 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2933 /* The prefix handles the problem if we are in a delay slot. */
2934 if (cris_get_operand1 (inst
) == REG_PC
)
2936 /* Just take care of the assign. */
2937 check_assign (inst
, inst_env
);
2941 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2943 /* The instruction doesn't have a prefix, the only case left that we
2944 are interested in is the autoincrement mode. */
2945 if (cris_get_operand1 (inst
) == REG_PC
)
2947 /* If the PC is to be incremented it's invalid to be in a
2949 if (inst_env
->slot_needed
)
2951 inst_env
->invalid
= 1;
2955 /* The increment depends on the size of the special register. */
2956 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2958 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2960 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2962 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2966 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2970 inst_env
->slot_needed
= 0;
2971 inst_env
->prefix_found
= 0;
2972 inst_env
->xflag_found
= 0;
2973 inst_env
->disable_interrupt
= 1;
2976 /* Handles moves from special registers (aka P-register) for all modes
2980 none_reg_mode_move_from_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2981 inst_env_type
*inst_env
)
2983 if (inst_env
->prefix_found
)
2985 /* The instruction has a prefix that means we are only interested if
2986 the instruction is in assign mode. */
2987 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2989 /* The prefix handles the problem if we are in a delay slot. */
2990 if (cris_get_operand1 (inst
) == REG_PC
)
2992 /* Just take care of the assign. */
2993 check_assign (inst
, inst_env
);
2997 /* The instruction doesn't have a prefix, the only case left that we
2998 are interested in is the autoincrement mode. */
2999 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
3001 if (cris_get_operand1 (inst
) == REG_PC
)
3003 /* If the PC is to be incremented it's invalid to be in a
3005 if (inst_env
->slot_needed
)
3007 inst_env
->invalid
= 1;
3011 /* The increment depends on the size of the special register. */
3012 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
3014 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
3016 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
3018 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
3022 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
3026 inst_env
->slot_needed
= 0;
3027 inst_env
->prefix_found
= 0;
3028 inst_env
->xflag_found
= 0;
3029 inst_env
->disable_interrupt
= 1;
3032 /* Handles moves from special registers (aka P-register) when the mode
3036 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
3038 /* Register mode move from special register can't have a prefix. */
3039 if (inst_env
->prefix_found
)
3041 inst_env
->invalid
= 1;
3045 if (cris_get_operand1 (inst
) == REG_PC
)
3047 /* It's invalid to change the PC in a delay slot. */
3048 if (inst_env
->slot_needed
)
3050 inst_env
->invalid
= 1;
3053 /* The destination is the PC, the jump will have a delay slot. */
3054 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
3055 inst_env
->slot_needed
= 1;
3056 inst_env
->delay_slot_pc_active
= 1;
3060 /* If the destination isn't PC, there will be no jump. */
3061 inst_env
->slot_needed
= 0;
3063 inst_env
->prefix_found
= 0;
3064 inst_env
->xflag_found
= 0;
3065 inst_env
->disable_interrupt
= 1;
3068 /* Handles the MOVEM from memory to general register instruction. */
3071 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3073 if (inst_env
->prefix_found
)
3075 /* The prefix handles the problem if we are in a delay slot. Is the
3076 MOVEM instruction going to change the PC? */
3077 if (cris_get_operand2 (inst
) >= REG_PC
)
3079 inst_env
->reg
[REG_PC
] =
3080 read_memory_unsigned_integer (inst_env
->prefix_value
,
3081 4, inst_env
->byte_order
);
3083 /* The assign value is the value after the increment. Normally, the
3084 assign value is the value before the increment. */
3085 if ((cris_get_operand1 (inst
) == REG_PC
)
3086 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3088 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3089 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3094 /* Is the MOVEM instruction going to change the PC? */
3095 if (cris_get_operand2 (inst
) == REG_PC
)
3097 /* It's invalid to change the PC in a delay slot. */
3098 if (inst_env
->slot_needed
)
3100 inst_env
->invalid
= 1;
3103 inst_env
->reg
[REG_PC
] =
3104 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3105 4, inst_env
->byte_order
);
3107 /* The increment is not depending on the size, instead it's depending
3108 on the number of registers loaded from memory. */
3109 if ((cris_get_operand1 (inst
) == REG_PC
)
3110 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3112 /* It's invalid to change the PC in a delay slot. */
3113 if (inst_env
->slot_needed
)
3115 inst_env
->invalid
= 1;
3118 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3121 inst_env
->slot_needed
= 0;
3122 inst_env
->prefix_found
= 0;
3123 inst_env
->xflag_found
= 0;
3124 inst_env
->disable_interrupt
= 0;
3127 /* Handles the MOVEM to memory from general register instruction. */
3130 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3132 if (inst_env
->prefix_found
)
3134 /* The assign value is the value after the increment. Normally, the
3135 assign value is the value before the increment. */
3136 if ((cris_get_operand1 (inst
) == REG_PC
)
3137 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3139 /* The prefix handles the problem if we are in a delay slot. */
3140 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3141 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3146 /* The increment is not depending on the size, instead it's depending
3147 on the number of registers loaded to memory. */
3148 if ((cris_get_operand1 (inst
) == REG_PC
)
3149 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3151 /* It's invalid to change the PC in a delay slot. */
3152 if (inst_env
->slot_needed
)
3154 inst_env
->invalid
= 1;
3157 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3160 inst_env
->slot_needed
= 0;
3161 inst_env
->prefix_found
= 0;
3162 inst_env
->xflag_found
= 0;
3163 inst_env
->disable_interrupt
= 0;
3166 /* Handles the intructions that's not yet implemented, by setting
3167 inst_env->invalid to true. */
3170 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3172 inst_env
->invalid
= 1;
3175 /* Handles the XOR instruction. */
3178 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3180 /* XOR can't have a prefix. */
3181 if (inst_env
->prefix_found
)
3183 inst_env
->invalid
= 1;
3187 /* Check if the PC is the target. */
3188 if (cris_get_operand2 (inst
) == REG_PC
)
3190 /* It's invalid to change the PC in a delay slot. */
3191 if (inst_env
->slot_needed
)
3193 inst_env
->invalid
= 1;
3196 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3198 inst_env
->slot_needed
= 0;
3199 inst_env
->prefix_found
= 0;
3200 inst_env
->xflag_found
= 0;
3201 inst_env
->disable_interrupt
= 0;
3204 /* Handles the MULS instruction. */
3207 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3209 /* MULS/U can't have a prefix. */
3210 if (inst_env
->prefix_found
)
3212 inst_env
->invalid
= 1;
3216 /* Consider it invalid if the PC is the target. */
3217 if (cris_get_operand2 (inst
) == REG_PC
)
3219 inst_env
->invalid
= 1;
3222 inst_env
->slot_needed
= 0;
3223 inst_env
->prefix_found
= 0;
3224 inst_env
->xflag_found
= 0;
3225 inst_env
->disable_interrupt
= 0;
3228 /* Handles the MULU instruction. */
3231 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3233 /* MULS/U can't have a prefix. */
3234 if (inst_env
->prefix_found
)
3236 inst_env
->invalid
= 1;
3240 /* Consider it invalid if the PC is the target. */
3241 if (cris_get_operand2 (inst
) == REG_PC
)
3243 inst_env
->invalid
= 1;
3246 inst_env
->slot_needed
= 0;
3247 inst_env
->prefix_found
= 0;
3248 inst_env
->xflag_found
= 0;
3249 inst_env
->disable_interrupt
= 0;
3252 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3253 The MOVE instruction is the move from source to register. */
3256 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3257 unsigned long source1
, unsigned long source2
)
3259 unsigned long pc_mask
;
3260 unsigned long operation_mask
;
3262 /* Find out how many bits the operation should apply to. */
3263 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3265 pc_mask
= 0xFFFFFF00;
3266 operation_mask
= 0xFF;
3268 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3270 pc_mask
= 0xFFFF0000;
3271 operation_mask
= 0xFFFF;
3273 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3276 operation_mask
= 0xFFFFFFFF;
3280 /* The size is out of range. */
3281 inst_env
->invalid
= 1;
3285 /* The instruction just works on uw_operation_mask bits. */
3286 source2
&= operation_mask
;
3287 source1
&= operation_mask
;
3289 /* Now calculate the result. The opcode's 3 first bits separates
3290 the different actions. */
3291 switch (cris_get_opcode (inst
) & 7)
3301 case 2: /* subtract */
3305 case 3: /* compare */
3317 inst_env
->invalid
= 1;
3323 /* Make sure that the result doesn't contain more than the instruction
3325 source2
&= operation_mask
;
3327 /* Calculate the new breakpoint address. */
3328 inst_env
->reg
[REG_PC
] &= pc_mask
;
3329 inst_env
->reg
[REG_PC
] |= source1
;
3333 /* Extends the value from either byte or word size to a dword. If the mode
3334 is zero extend then the value is extended with zero. If instead the mode
3335 is signed extend the sign bit of the value is taken into consideration. */
3337 static unsigned long
3338 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3340 /* The size can be either byte or word, check which one it is.
3341 Don't check the highest bit, it's indicating if it's a zero
3343 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3348 /* Check if the instruction is signed extend. If so, check if value has
3350 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3352 value
|= SIGNED_WORD_EXTEND_MASK
;
3360 /* Check if the instruction is signed extend. If so, check if value has
3362 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3364 value
|= SIGNED_BYTE_EXTEND_MASK
;
3367 /* The size should now be dword. */
3368 cris_set_size_to_dword (inst
);
3372 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3373 instruction. The MOVE instruction is the move from source to register. */
3376 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3377 inst_env_type
*inst_env
)
3379 unsigned long operand1
;
3380 unsigned long operand2
;
3382 /* It's invalid to have a prefix to the instruction. This is a register
3383 mode instruction and can't have a prefix. */
3384 if (inst_env
->prefix_found
)
3386 inst_env
->invalid
= 1;
3389 /* Check if the instruction has PC as its target. */
3390 if (cris_get_operand2 (inst
) == REG_PC
)
3392 if (inst_env
->slot_needed
)
3394 inst_env
->invalid
= 1;
3397 /* The instruction has the PC as its target register. */
3398 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3399 operand2
= inst_env
->reg
[REG_PC
];
3401 /* Check if it's a extend, signed or zero instruction. */
3402 if (cris_get_opcode (inst
) < 4)
3404 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3406 /* Calculate the PC value after the instruction, i.e. where the
3407 breakpoint should be. The order of the udw_operands is vital. */
3408 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3410 inst_env
->slot_needed
= 0;
3411 inst_env
->prefix_found
= 0;
3412 inst_env
->xflag_found
= 0;
3413 inst_env
->disable_interrupt
= 0;
3416 /* Returns the data contained at address. The size of the data is derived from
3417 the size of the operation. If the instruction is a zero or signed
3418 extend instruction, the size field is changed in instruction. */
3420 static unsigned long
3421 get_data_from_address (unsigned short *inst
, CORE_ADDR address
,
3422 enum bfd_endian byte_order
)
3424 int size
= cris_get_size (*inst
);
3425 unsigned long value
;
3427 /* If it's an extend instruction we don't want the signed extend bit,
3428 because it influences the size. */
3429 if (cris_get_opcode (*inst
) < 4)
3431 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3433 /* Is there a need for checking the size? Size should contain the number of
3436 value
= read_memory_unsigned_integer (address
, size
, byte_order
);
3438 /* Check if it's an extend, signed or zero instruction. */
3439 if (cris_get_opcode (*inst
) < 4)
3441 value
= do_sign_or_zero_extend (value
, inst
);
3446 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3447 instructions. The MOVE instruction is the move from source to register. */
3450 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3451 inst_env_type
*inst_env
)
3453 unsigned long operand2
;
3454 unsigned long operand3
;
3456 check_assign (inst
, inst_env
);
3457 if (cris_get_operand2 (inst
) == REG_PC
)
3459 operand2
= inst_env
->reg
[REG_PC
];
3461 /* Get the value of the third operand. */
3462 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3463 inst_env
->byte_order
);
3465 /* Calculate the PC value after the instruction, i.e. where the
3466 breakpoint should be. The order of the udw_operands is vital. */
3467 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3469 inst_env
->slot_needed
= 0;
3470 inst_env
->prefix_found
= 0;
3471 inst_env
->xflag_found
= 0;
3472 inst_env
->disable_interrupt
= 0;
3475 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3476 OR instructions. Note that for this to work as expected, the calling
3477 function must have made sure that there is a prefix to this instruction. */
3480 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3481 inst_env_type
*inst_env
)
3483 unsigned long operand2
;
3484 unsigned long operand3
;
3486 if (cris_get_operand1 (inst
) == REG_PC
)
3488 /* The PC will be changed by the instruction. */
3489 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3491 /* Get the value of the third operand. */
3492 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3493 inst_env
->byte_order
);
3495 /* Calculate the PC value after the instruction, i.e. where the
3496 breakpoint should be. */
3497 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3499 inst_env
->slot_needed
= 0;
3500 inst_env
->prefix_found
= 0;
3501 inst_env
->xflag_found
= 0;
3502 inst_env
->disable_interrupt
= 0;
3505 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3506 instructions. The MOVE instruction is the move from source to register. */
3509 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3510 inst_env_type
*inst_env
)
3512 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3514 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3515 SUB, AND or OR something weird is going on (if everything works these
3516 instructions should end up in the three operand version). */
3517 inst_env
->invalid
= 1;
3522 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3524 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3526 inst_env
->slot_needed
= 0;
3527 inst_env
->prefix_found
= 0;
3528 inst_env
->xflag_found
= 0;
3529 inst_env
->disable_interrupt
= 0;
3532 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3533 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3534 source to register. */
3537 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3538 inst_env_type
*inst_env
)
3540 unsigned long operand1
;
3541 unsigned long operand2
;
3542 unsigned long operand3
;
3545 /* The instruction is either an indirect or autoincrement addressing mode.
3546 Check if the destination register is the PC. */
3547 if (cris_get_operand2 (inst
) == REG_PC
)
3549 /* Must be done here, get_data_from_address may change the size
3551 size
= cris_get_size (inst
);
3552 operand2
= inst_env
->reg
[REG_PC
];
3554 /* Get the value of the third operand, i.e. the indirect operand. */
3555 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3556 operand3
= get_data_from_address (&inst
, operand1
, inst_env
->byte_order
);
3558 /* Calculate the PC value after the instruction, i.e. where the
3559 breakpoint should be. The order of the udw_operands is vital. */
3560 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3562 /* If this is an autoincrement addressing mode, check if the increment
3564 if ((cris_get_operand1 (inst
) == REG_PC
)
3565 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3567 /* Get the size field. */
3568 size
= cris_get_size (inst
);
3570 /* If it's an extend instruction we don't want the signed extend bit,
3571 because it influences the size. */
3572 if (cris_get_opcode (inst
) < 4)
3574 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3576 process_autoincrement (size
, inst
, inst_env
);
3578 inst_env
->slot_needed
= 0;
3579 inst_env
->prefix_found
= 0;
3580 inst_env
->xflag_found
= 0;
3581 inst_env
->disable_interrupt
= 0;
3584 /* Handles the two-operand addressing mode, all modes except register, for
3585 the ADD, SUB CMP, AND and OR instruction. */
3588 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3589 inst_env_type
*inst_env
)
3591 if (inst_env
->prefix_found
)
3593 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3595 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3597 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3599 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3603 /* The mode is invalid for a prefixed base instruction. */
3604 inst_env
->invalid
= 1;
3610 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3614 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3617 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3619 unsigned long operand1
;
3620 unsigned long operand2
;
3622 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3623 instruction and can't have a prefix. */
3624 if (inst_env
->prefix_found
)
3626 inst_env
->invalid
= 1;
3630 /* Check if the instruction has PC as its target. */
3631 if (cris_get_operand2 (inst
) == REG_PC
)
3633 if (inst_env
->slot_needed
)
3635 inst_env
->invalid
= 1;
3638 operand1
= cris_get_quick_value (inst
);
3639 operand2
= inst_env
->reg
[REG_PC
];
3641 /* The size should now be dword. */
3642 cris_set_size_to_dword (&inst
);
3644 /* Calculate the PC value after the instruction, i.e. where the
3645 breakpoint should be. */
3646 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3648 inst_env
->slot_needed
= 0;
3649 inst_env
->prefix_found
= 0;
3650 inst_env
->xflag_found
= 0;
3651 inst_env
->disable_interrupt
= 0;
3654 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3657 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3659 unsigned long operand1
;
3660 unsigned long operand2
;
3662 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3663 instruction and can't have a prefix. */
3664 if (inst_env
->prefix_found
)
3666 inst_env
->invalid
= 1;
3669 /* Check if the instruction has PC as its target. */
3670 if (cris_get_operand2 (inst
) == REG_PC
)
3672 if (inst_env
->slot_needed
)
3674 inst_env
->invalid
= 1;
3677 /* The instruction has the PC as its target register. */
3678 operand1
= cris_get_quick_value (inst
);
3679 operand2
= inst_env
->reg
[REG_PC
];
3681 /* The quick value is signed, so check if we must do a signed extend. */
3682 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3685 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3687 /* The size should now be dword. */
3688 cris_set_size_to_dword (&inst
);
3690 /* Calculate the PC value after the instruction, i.e. where the
3691 breakpoint should be. */
3692 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3694 inst_env
->slot_needed
= 0;
3695 inst_env
->prefix_found
= 0;
3696 inst_env
->xflag_found
= 0;
3697 inst_env
->disable_interrupt
= 0;
3700 /* Translate op_type to a function and call it. */
3703 cris_gdb_func (struct gdbarch
*gdbarch
, enum cris_op_type op_type
,
3704 unsigned short inst
, inst_env_type
*inst_env
)
3708 case cris_not_implemented_op
:
3709 not_implemented_op (inst
, inst_env
);
3713 abs_op (inst
, inst_env
);
3717 addi_op (inst
, inst_env
);
3721 asr_op (inst
, inst_env
);
3725 asrq_op (inst
, inst_env
);
3728 case cris_ax_ei_setf_op
:
3729 ax_ei_setf_op (inst
, inst_env
);
3732 case cris_bdap_prefix
:
3733 bdap_prefix (inst
, inst_env
);
3736 case cris_biap_prefix
:
3737 biap_prefix (inst
, inst_env
);
3741 break_op (inst
, inst_env
);
3744 case cris_btst_nop_op
:
3745 btst_nop_op (inst
, inst_env
);
3748 case cris_clearf_di_op
:
3749 clearf_di_op (inst
, inst_env
);
3752 case cris_dip_prefix
:
3753 dip_prefix (inst
, inst_env
);
3756 case cris_dstep_logshift_mstep_neg_not_op
:
3757 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3760 case cris_eight_bit_offset_branch_op
:
3761 eight_bit_offset_branch_op (inst
, inst_env
);
3764 case cris_move_mem_to_reg_movem_op
:
3765 move_mem_to_reg_movem_op (inst
, inst_env
);
3768 case cris_move_reg_to_mem_movem_op
:
3769 move_reg_to_mem_movem_op (inst
, inst_env
);
3772 case cris_move_to_preg_op
:
3773 move_to_preg_op (gdbarch
, inst
, inst_env
);
3777 muls_op (inst
, inst_env
);
3781 mulu_op (inst
, inst_env
);
3784 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3785 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3788 case cris_none_reg_mode_clear_test_op
:
3789 none_reg_mode_clear_test_op (inst
, inst_env
);
3792 case cris_none_reg_mode_jump_op
:
3793 none_reg_mode_jump_op (inst
, inst_env
);
3796 case cris_none_reg_mode_move_from_preg_op
:
3797 none_reg_mode_move_from_preg_op (gdbarch
, inst
, inst_env
);
3800 case cris_quick_mode_add_sub_op
:
3801 quick_mode_add_sub_op (inst
, inst_env
);
3804 case cris_quick_mode_and_cmp_move_or_op
:
3805 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3808 case cris_quick_mode_bdap_prefix
:
3809 quick_mode_bdap_prefix (inst
, inst_env
);
3812 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3813 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3816 case cris_reg_mode_clear_op
:
3817 reg_mode_clear_op (inst
, inst_env
);
3820 case cris_reg_mode_jump_op
:
3821 reg_mode_jump_op (inst
, inst_env
);
3824 case cris_reg_mode_move_from_preg_op
:
3825 reg_mode_move_from_preg_op (inst
, inst_env
);
3828 case cris_reg_mode_test_op
:
3829 reg_mode_test_op (inst
, inst_env
);
3833 scc_op (inst
, inst_env
);
3836 case cris_sixteen_bit_offset_branch_op
:
3837 sixteen_bit_offset_branch_op (inst
, inst_env
);
3840 case cris_three_operand_add_sub_cmp_and_or_op
:
3841 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3844 case cris_three_operand_bound_op
:
3845 three_operand_bound_op (inst
, inst_env
);
3848 case cris_two_operand_bound_op
:
3849 two_operand_bound_op (inst
, inst_env
);
3853 xor_op (inst
, inst_env
);
3858 /* This wrapper is to avoid cris_get_assembler being called before
3859 exec_bfd has been set. */
3862 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3864 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3865 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3866 disassembler, even when there is no BFD. Does something like
3867 "gdb; target remote; disassmeble *0x123" work? */
3868 gdb_assert (exec_bfd
!= NULL
);
3869 print_insn
= cris_get_disassembler (exec_bfd
);
3870 gdb_assert (print_insn
!= NULL
);
3871 return print_insn (addr
, info
);
3874 /* Copied from <asm/elf.h>. */
3875 typedef unsigned long elf_greg_t
;
3877 /* Same as user_regs_struct struct in <asm/user.h>. */
3878 #define CRISV10_ELF_NGREG 35
3879 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3881 #define CRISV32_ELF_NGREG 32
3882 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3884 /* Unpack an elf_gregset_t into GDB's register cache. */
3887 cris_supply_gregset (struct regcache
*regcache
, elf_gregset_t
*gregsetp
)
3889 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3890 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3892 elf_greg_t
*regp
= *gregsetp
;
3893 static char zerobuf
[4] = {0};
3895 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3896 knows about the actual size of each register so that's no problem. */
3897 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3899 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3902 if (tdep
->cris_version
== 32)
3904 /* Needed to set pseudo-register PC for CRISv32. */
3905 /* FIXME: If ERP is in a delay slot at this point then the PC will
3906 be wrong. Issue a warning to alert the user. */
3907 regcache_raw_supply (regcache
, gdbarch_pc_regnum (gdbarch
),
3908 (char *)®p
[ERP_REGNUM
]);
3910 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3911 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3915 /* Use a local version of this function to get the correct types for
3916 regsets, until multi-arch core support is ready. */
3919 fetch_core_registers (struct regcache
*regcache
,
3920 char *core_reg_sect
, unsigned core_reg_size
,
3921 int which
, CORE_ADDR reg_addr
)
3923 elf_gregset_t gregset
;
3928 if (core_reg_size
!= sizeof (elf_gregset_t
)
3929 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3931 warning (_("wrong size gregset struct in core file"));
3935 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3936 cris_supply_gregset (regcache
, &gregset
);
3940 /* We've covered all the kinds of registers we know about here,
3941 so this must be something we wouldn't know what to do with
3942 anyway. Just ignore it. */
3947 static struct core_fns cris_elf_core_fns
=
3949 bfd_target_elf_flavour
, /* core_flavour */
3950 default_check_format
, /* check_format */
3951 default_core_sniffer
, /* core_sniffer */
3952 fetch_core_registers
, /* core_read_registers */
3956 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3959 _initialize_cris_tdep (void)
3961 static struct cmd_list_element
*cris_set_cmdlist
;
3962 static struct cmd_list_element
*cris_show_cmdlist
;
3964 struct cmd_list_element
*c
;
3966 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3968 /* CRIS-specific user-commands. */
3969 add_setshow_uinteger_cmd ("cris-version", class_support
,
3970 &usr_cmd_cris_version
,
3971 _("Set the current CRIS version."),
3972 _("Show the current CRIS version."),
3974 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3977 NULL
, /* FIXME: i18n: Current CRIS version
3979 &setlist
, &showlist
);
3981 add_setshow_enum_cmd ("cris-mode", class_support
,
3982 cris_modes
, &usr_cmd_cris_mode
,
3983 _("Set the current CRIS mode."),
3984 _("Show the current CRIS mode."),
3986 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3987 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3989 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3990 &setlist
, &showlist
);
3992 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3993 &usr_cmd_cris_dwarf2_cfi
,
3994 _("Set the usage of Dwarf-2 CFI for CRIS."),
3995 _("Show the usage of Dwarf-2 CFI for CRIS."),
3996 _("Set this to \"off\" if using gcc-cris < R59."),
3997 set_cris_dwarf2_cfi
,
3998 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI
4000 &setlist
, &showlist
);
4002 deprecated_add_core_fns (&cris_elf_core_fns
);
4005 /* Prints out all target specific values. */
4008 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
4010 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4013 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
4014 tdep
->cris_version
);
4015 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
4017 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4018 tdep
->cris_dwarf2_cfi
);
4023 set_cris_version (char *ignore_args
, int from_tty
,
4024 struct cmd_list_element
*c
)
4026 struct gdbarch_info info
;
4028 usr_cmd_cris_version_valid
= 1;
4030 /* Update the current architecture, if needed. */
4031 gdbarch_info_init (&info
);
4032 if (!gdbarch_update_p (info
))
4033 internal_error (__FILE__
, __LINE__
,
4034 _("cris_gdbarch_update: failed to update architecture."));
4038 set_cris_mode (char *ignore_args
, int from_tty
,
4039 struct cmd_list_element
*c
)
4041 struct gdbarch_info info
;
4043 /* Update the current architecture, if needed. */
4044 gdbarch_info_init (&info
);
4045 if (!gdbarch_update_p (info
))
4046 internal_error (__FILE__
, __LINE__
,
4047 "cris_gdbarch_update: failed to update architecture.");
4051 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
4052 struct cmd_list_element
*c
)
4054 struct gdbarch_info info
;
4056 /* Update the current architecture, if needed. */
4057 gdbarch_info_init (&info
);
4058 if (!gdbarch_update_p (info
))
4059 internal_error (__FILE__
, __LINE__
,
4060 _("cris_gdbarch_update: failed to update architecture."));
4063 static struct gdbarch
*
4064 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4066 struct gdbarch
*gdbarch
;
4067 struct gdbarch_tdep
*tdep
;
4070 if (usr_cmd_cris_version_valid
)
4072 /* Trust the user's CRIS version setting. */
4073 cris_version
= usr_cmd_cris_version
;
4075 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4081 /* Assume it's CRIS version 10. */
4085 /* Make the current settings visible to the user. */
4086 usr_cmd_cris_version
= cris_version
;
4088 /* Find a candidate among the list of pre-declared architectures. */
4089 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4091 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4093 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4094 == usr_cmd_cris_version
)
4095 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4096 == usr_cmd_cris_mode
)
4097 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4098 == usr_cmd_cris_dwarf2_cfi
))
4099 return arches
->gdbarch
;
4102 /* No matching architecture was found. Create a new one. */
4103 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4104 gdbarch
= gdbarch_alloc (&info
, tdep
);
4106 tdep
->cris_version
= usr_cmd_cris_version
;
4107 tdep
->cris_mode
= usr_cmd_cris_mode
;
4108 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4110 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4111 switch (info
.byte_order
)
4113 case BFD_ENDIAN_LITTLE
:
4117 case BFD_ENDIAN_BIG
:
4118 internal_error (__FILE__
, __LINE__
,
4119 _("cris_gdbarch_init: big endian byte order in info"));
4123 internal_error (__FILE__
, __LINE__
,
4124 _("cris_gdbarch_init: unknown byte order in info"));
4127 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4129 set_gdbarch_sp_regnum (gdbarch
, 14);
4131 /* Length of ordinary registers used in push_word and a few other
4132 places. register_size() is the real way to know how big a
4135 set_gdbarch_double_bit (gdbarch
, 64);
4136 /* The default definition of a long double is 2 * gdbarch_double_bit,
4137 which means we have to set this explicitly. */
4138 set_gdbarch_long_double_bit (gdbarch
, 64);
4140 /* The total amount of space needed to store (in an array called registers)
4141 GDB's copy of the machine's register state. Note: We can not use
4142 cris_register_size at this point, since it relies on gdbarch
4144 switch (tdep
->cris_version
)
4152 /* Old versions; not supported. */
4153 internal_error (__FILE__
, __LINE__
,
4154 _("cris_gdbarch_init: unsupported CRIS version"));
4159 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4160 P7 (32 bits), and P15 (32 bits) have been implemented. */
4161 set_gdbarch_pc_regnum (gdbarch
, 15);
4162 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4163 /* There are 32 registers (some of which may not be implemented). */
4164 set_gdbarch_num_regs (gdbarch
, 32);
4165 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4166 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4167 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4169 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4173 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4174 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4175 and pseudo-register PC (32 bits). */
4176 set_gdbarch_pc_regnum (gdbarch
, 32);
4177 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4178 /* 32 registers + pseudo-register PC + 16 support registers. */
4179 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4180 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4182 set_gdbarch_cannot_store_register
4183 (gdbarch
, crisv32_cannot_store_register
);
4184 set_gdbarch_cannot_fetch_register
4185 (gdbarch
, crisv32_cannot_fetch_register
);
4187 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4189 set_gdbarch_single_step_through_delay
4190 (gdbarch
, crisv32_single_step_through_delay
);
4195 internal_error (__FILE__
, __LINE__
,
4196 _("cris_gdbarch_init: unknown CRIS version"));
4199 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4200 have the same ABI). */
4201 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4202 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4203 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4204 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4206 /* The stack grows downward. */
4207 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4209 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4211 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4212 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4213 set_gdbarch_dummy_id (gdbarch
, cris_dummy_id
);
4215 if (tdep
->cris_dwarf2_cfi
== 1)
4217 /* Hook in the Dwarf-2 frame sniffer. */
4218 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4219 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4220 dwarf2_append_unwinders (gdbarch
);
4223 if (tdep
->cris_mode
!= cris_mode_guru
)
4225 frame_unwind_append_unwinder (gdbarch
, &cris_sigtramp_frame_unwind
);
4228 frame_unwind_append_unwinder (gdbarch
, &cris_frame_unwind
);
4229 frame_base_set_default (gdbarch
, &cris_frame_base
);
4231 set_solib_svr4_fetch_link_map_offsets
4232 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
4234 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4235 disassembler, even when there is no BFD. Does something like
4236 "gdb; target remote; disassmeble *0x123" work? */
4237 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);