1 /* Target-dependent code for Mitsubishi D10V, for GDB.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Contributed by Martin Hunt, hunt@cygnus.com */
31 #include "gdb_string.h"
38 #include "arch-utils.h"
41 #include "floatformat.h"
45 #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
47 struct frame_extra_info
58 unsigned long (*dmap_register
) (int nr
);
59 unsigned long (*imap_register
) (int nr
);
62 /* These are the addresses the D10V-EVA board maps data and
63 instruction memory to. */
65 #define DMEM_START 0x2000000
66 #define IMEM_START 0x1000000
67 #define STACK_START 0x0007ffe
69 /* d10v register names. */
79 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
80 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
82 /* d10v calling convention. */
84 #define ARG1_REGNUM R0_REGNUM
86 #define RET1_REGNUM R0_REGNUM
90 extern void _initialize_d10v_tdep (void);
92 static void d10v_eva_prepare_to_trace (void);
94 static void d10v_eva_get_trace_data (void);
96 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
99 static void d10v_frame_init_saved_regs (struct frame_info
*);
101 static void do_d10v_pop_frame (struct frame_info
*fi
);
104 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
106 return ((chain
) != 0 && (frame
) != 0 && (frame
)->pc
> IMEM_START
);
110 d10v_stack_align (CORE_ADDR len
)
112 return (len
+ 1) & ~1;
115 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
116 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
117 and TYPE is the type (which is known to be struct, union or array).
119 The d10v returns anything less than 8 bytes in size in
123 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
125 return (TYPE_LENGTH (type
) > 8);
129 static unsigned char *
130 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
132 static unsigned char breakpoint
[] =
133 {0x2f, 0x90, 0x5e, 0x00};
134 *lenptr
= sizeof (breakpoint
);
138 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
139 when the reg_nr isn't valid. */
143 TS2_IMAP0_REGNUM
= 32,
144 TS2_DMAP_REGNUM
= 34,
145 TS2_NR_DMAP_REGS
= 1,
150 d10v_ts2_register_name (int reg_nr
)
152 static char *register_names
[] =
154 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
155 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
156 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
157 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
158 "imap0", "imap1", "dmap", "a0", "a1"
162 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
164 return register_names
[reg_nr
];
169 TS3_IMAP0_REGNUM
= 36,
170 TS3_DMAP0_REGNUM
= 38,
171 TS3_NR_DMAP_REGS
= 4,
176 d10v_ts3_register_name (int reg_nr
)
178 static char *register_names
[] =
180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
182 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
183 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
187 "dmap0", "dmap1", "dmap2", "dmap3"
191 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
193 return register_names
[reg_nr
];
196 /* Access the DMAP/IMAP registers in a target independent way.
198 Divide the D10V's 64k data space into four 16k segments:
199 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
202 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
203 0x7fff) always map to the on-chip data RAM, and the fourth always
204 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
205 unified memory or instruction memory, under the control of the
206 single DMAP register.
208 On the TS3, there are four DMAP registers, each of which controls
209 one of the segments. */
212 d10v_ts2_dmap_register (int reg_nr
)
220 return read_register (TS2_DMAP_REGNUM
);
227 d10v_ts3_dmap_register (int reg_nr
)
229 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
233 d10v_dmap_register (int reg_nr
)
235 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
239 d10v_ts2_imap_register (int reg_nr
)
241 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
245 d10v_ts3_imap_register (int reg_nr
)
247 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
251 d10v_imap_register (int reg_nr
)
253 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
256 /* MAP GDB's internal register numbering (determined by the layout fo
257 the REGISTER_BYTE array) onto the simulator's register
261 d10v_ts2_register_sim_regno (int nr
)
263 if (nr
>= TS2_IMAP0_REGNUM
264 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
265 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
266 if (nr
== TS2_DMAP_REGNUM
)
267 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
268 if (nr
>= TS2_A0_REGNUM
269 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
270 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
275 d10v_ts3_register_sim_regno (int nr
)
277 if (nr
>= TS3_IMAP0_REGNUM
278 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
279 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
280 if (nr
>= TS3_DMAP0_REGNUM
281 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
282 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
283 if (nr
>= TS3_A0_REGNUM
284 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
285 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
289 /* Index within `registers' of the first byte of the space for
293 d10v_register_byte (int reg_nr
)
295 if (reg_nr
< A0_REGNUM
)
297 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
298 return (A0_REGNUM
* 2
299 + (reg_nr
- A0_REGNUM
) * 8);
301 return (A0_REGNUM
* 2
303 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
306 /* Number of bytes of storage in the actual machine representation for
310 d10v_register_raw_size (int reg_nr
)
312 if (reg_nr
< A0_REGNUM
)
314 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
320 /* Number of bytes of storage in the program's representation
324 d10v_register_virtual_size (int reg_nr
)
326 return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr
));
329 /* Return the GDB type object for the "standard" data type
330 of data in register N. */
333 d10v_register_virtual_type (int reg_nr
)
335 if (reg_nr
== PC_REGNUM
)
336 return builtin_type_void_func_ptr
;
337 else if (reg_nr
>= A0_REGNUM
338 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
339 return builtin_type_int64
;
341 return builtin_type_int16
;
345 d10v_make_daddr (CORE_ADDR x
)
347 return ((x
) | DMEM_START
);
351 d10v_make_iaddr (CORE_ADDR x
)
353 return (((x
) << 2) | IMEM_START
);
357 d10v_daddr_p (CORE_ADDR x
)
359 return (((x
) & 0x3000000) == DMEM_START
);
363 d10v_iaddr_p (CORE_ADDR x
)
365 return (((x
) & 0x3000000) == IMEM_START
);
370 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
372 return (((x
) >> 2) & 0xffff);
376 d10v_convert_daddr_to_raw (CORE_ADDR x
)
378 return ((x
) & 0xffff);
382 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
384 /* Is it a code address? */
385 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
386 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
389 if (! d10v_iaddr_p (addr
))
392 fprintf_unfiltered (gdb_stderr
, "address `");
393 print_address_numeric (addr
, 1, gdb_stderr
);
394 fprintf_unfiltered (gdb_stderr
, "' is not a code address\n");
398 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
399 d10v_convert_iaddr_to_raw (addr
));
403 /* Strip off any upper segment bits. */
404 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
405 d10v_convert_daddr_to_raw (addr
));
410 d10v_pointer_to_address (struct type
*type
, void *buf
)
412 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
414 /* Is it a code address? */
415 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
416 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
417 return d10v_make_iaddr (addr
);
419 return d10v_make_daddr (addr
);
423 /* Store the address of the place in which to copy the structure the
424 subroutine will return. This is called from call_function.
426 We store structs through a pointer passed in the first Argument
430 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
432 write_register (ARG1_REGNUM
, (addr
));
435 /* Write into appropriate registers a function return value
436 of type TYPE, given in virtual format.
438 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
441 d10v_store_return_value (struct type
*type
, char *valbuf
)
443 write_register_bytes (REGISTER_BYTE (RET1_REGNUM
),
448 /* Extract from an array REGBUF containing the (raw) register state
449 the address in which a function should return its structure value,
450 as a CORE_ADDR (or an expression that can be used as one). */
453 d10v_extract_struct_value_address (char *regbuf
)
455 return (extract_address ((regbuf
) + REGISTER_BYTE (ARG1_REGNUM
),
456 REGISTER_RAW_SIZE (ARG1_REGNUM
))
461 d10v_frame_saved_pc (struct frame_info
*frame
)
463 return ((frame
)->extra_info
->return_pc
);
466 /* Immediately after a function call, return the saved pc. We can't
467 use frame->return_pc beause that is determined by reading R13 off
468 the stack and that may not be written yet. */
471 d10v_saved_pc_after_call (struct frame_info
*frame
)
473 return ((read_register (LR_REGNUM
) << 2)
477 /* Discard from the stack the innermost frame, restoring all saved
481 d10v_pop_frame (void)
483 generic_pop_current_frame (do_d10v_pop_frame
);
487 do_d10v_pop_frame (struct frame_info
*fi
)
494 /* fill out fsr with the address of where each */
495 /* register was stored in the frame */
496 d10v_frame_init_saved_regs (fi
);
498 /* now update the current registers with the old values */
499 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
501 if (fi
->saved_regs
[regnum
])
503 read_memory (fi
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
504 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
, REGISTER_RAW_SIZE (regnum
));
507 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
509 if (fi
->saved_regs
[regnum
])
511 write_register (regnum
, read_memory_unsigned_integer (fi
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
514 if (fi
->saved_regs
[PSW_REGNUM
])
516 write_register (PSW_REGNUM
, read_memory_unsigned_integer (fi
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
519 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
520 write_register (SP_REGNUM
, fp
+ fi
->extra_info
->size
);
521 target_store_registers (-1);
522 flush_cached_frames ();
526 check_prologue (unsigned short op
)
529 if ((op
& 0x7E1F) == 0x6C1F)
533 if ((op
& 0x7E3F) == 0x6E1F)
537 if ((op
& 0x7FE1) == 0x01E1)
549 if ((op
& 0x7E1F) == 0x681E)
553 if ((op
& 0x7E3F) == 0x3A1E)
560 d10v_skip_prologue (CORE_ADDR pc
)
563 unsigned short op1
, op2
;
564 CORE_ADDR func_addr
, func_end
;
565 struct symtab_and_line sal
;
567 /* If we have line debugging information, then the end of the */
568 /* prologue should the first assembly instruction of the first source line */
569 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
571 sal
= find_pc_line (func_addr
, 0);
572 if (sal
.end
&& sal
.end
< func_end
)
576 if (target_read_memory (pc
, (char *) &op
, 4))
577 return pc
; /* Can't access it -- assume no prologue. */
581 op
= (unsigned long) read_memory_integer (pc
, 4);
582 if ((op
& 0xC0000000) == 0xC0000000)
584 /* long instruction */
585 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
586 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
587 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
592 /* short instructions */
593 if ((op
& 0xC0000000) == 0x80000000)
595 op2
= (op
& 0x3FFF8000) >> 15;
600 op1
= (op
& 0x3FFF8000) >> 15;
603 if (check_prologue (op1
))
605 if (!check_prologue (op2
))
607 /* if the previous opcode was really part of the prologue */
608 /* and not just a NOP, then we want to break after both instructions */
622 /* Given a GDB frame, determine the address of the calling function's frame.
623 This will be used to create a new GDB frame struct, and then
624 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
628 d10v_frame_chain (struct frame_info
*fi
)
630 d10v_frame_init_saved_regs (fi
);
632 if (fi
->extra_info
->return_pc
== IMEM_START
633 || inside_entry_file (fi
->extra_info
->return_pc
))
634 return (CORE_ADDR
) 0;
636 if (!fi
->saved_regs
[FP_REGNUM
])
638 if (!fi
->saved_regs
[SP_REGNUM
]
639 || fi
->saved_regs
[SP_REGNUM
] == STACK_START
)
640 return (CORE_ADDR
) 0;
642 return fi
->saved_regs
[SP_REGNUM
];
645 if (!read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
646 REGISTER_RAW_SIZE (FP_REGNUM
)))
647 return (CORE_ADDR
) 0;
649 return d10v_make_daddr (read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
650 REGISTER_RAW_SIZE (FP_REGNUM
)));
653 static int next_addr
, uses_frame
;
656 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
661 if ((op
& 0x7E1F) == 0x6C1F)
663 n
= (op
& 0x1E0) >> 5;
665 fi
->saved_regs
[n
] = next_addr
;
670 else if ((op
& 0x7E3F) == 0x6E1F)
672 n
= (op
& 0x1E0) >> 5;
674 fi
->saved_regs
[n
] = next_addr
;
675 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
680 if ((op
& 0x7FE1) == 0x01E1)
682 n
= (op
& 0x1E) >> 1;
701 if ((op
& 0x7E1F) == 0x681E)
703 n
= (op
& 0x1E0) >> 5;
704 fi
->saved_regs
[n
] = next_addr
;
709 if ((op
& 0x7E3F) == 0x3A1E)
711 n
= (op
& 0x1E0) >> 5;
712 fi
->saved_regs
[n
] = next_addr
;
713 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
720 /* Put here the code to store, into fi->saved_regs, the addresses of
721 the saved registers of frame described by FRAME_INFO. This
722 includes special registers such as pc and fp saved in special ways
723 in the stack frame. sp is even more special: the address we return
724 for it IS the sp for the next frame. */
727 d10v_frame_init_saved_regs (struct frame_info
*fi
)
731 unsigned short op1
, op2
;
735 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
738 pc
= get_pc_function_start (fi
->pc
);
743 op
= (unsigned long) read_memory_integer (pc
, 4);
744 if ((op
& 0xC0000000) == 0xC0000000)
746 /* long instruction */
747 if ((op
& 0x3FFF0000) == 0x01FF0000)
750 short n
= op
& 0xFFFF;
753 else if ((op
& 0x3F0F0000) == 0x340F0000)
755 /* st rn, @(offset,sp) */
756 short offset
= op
& 0xFFFF;
757 short n
= (op
>> 20) & 0xF;
758 fi
->saved_regs
[n
] = next_addr
+ offset
;
760 else if ((op
& 0x3F1F0000) == 0x350F0000)
762 /* st2w rn, @(offset,sp) */
763 short offset
= op
& 0xFFFF;
764 short n
= (op
>> 20) & 0xF;
765 fi
->saved_regs
[n
] = next_addr
+ offset
;
766 fi
->saved_regs
[n
+ 1] = next_addr
+ offset
+ 2;
773 /* short instructions */
774 if ((op
& 0xC0000000) == 0x80000000)
776 op2
= (op
& 0x3FFF8000) >> 15;
781 op1
= (op
& 0x3FFF8000) >> 15;
784 if (!prologue_find_regs (op1
, fi
, pc
) || !prologue_find_regs (op2
, fi
, pc
))
790 fi
->extra_info
->size
= -next_addr
;
793 fp
= d10v_make_daddr (read_register (SP_REGNUM
));
795 for (i
= 0; i
< NUM_REGS
- 1; i
++)
796 if (fi
->saved_regs
[i
])
798 fi
->saved_regs
[i
] = fp
- (next_addr
- fi
->saved_regs
[i
]);
801 if (fi
->saved_regs
[LR_REGNUM
])
803 CORE_ADDR return_pc
= read_memory_unsigned_integer (fi
->saved_regs
[LR_REGNUM
], REGISTER_RAW_SIZE (LR_REGNUM
));
804 fi
->extra_info
->return_pc
= d10v_make_iaddr (return_pc
);
808 fi
->extra_info
->return_pc
= d10v_make_iaddr (read_register (LR_REGNUM
));
811 /* th SP is not normally (ever?) saved, but check anyway */
812 if (!fi
->saved_regs
[SP_REGNUM
])
814 /* if the FP was saved, that means the current FP is valid, */
815 /* otherwise, it isn't being used, so we use the SP instead */
817 fi
->saved_regs
[SP_REGNUM
] = read_register (FP_REGNUM
) + fi
->extra_info
->size
;
820 fi
->saved_regs
[SP_REGNUM
] = fp
+ fi
->extra_info
->size
;
821 fi
->extra_info
->frameless
= 1;
822 fi
->saved_regs
[FP_REGNUM
] = 0;
828 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
830 fi
->extra_info
= (struct frame_extra_info
*)
831 frame_obstack_alloc (sizeof (struct frame_extra_info
));
832 frame_saved_regs_zalloc (fi
);
834 fi
->extra_info
->frameless
= 0;
835 fi
->extra_info
->size
= 0;
836 fi
->extra_info
->return_pc
= 0;
838 /* The call dummy doesn't save any registers on the stack, so we can
840 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
846 d10v_frame_init_saved_regs (fi
);
851 show_regs (char *args
, int from_tty
)
854 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
855 (long) read_register (PC_REGNUM
),
856 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
857 (long) read_register (PSW_REGNUM
),
858 (long) read_register (24),
859 (long) read_register (25),
860 (long) read_register (23));
861 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
862 (long) read_register (0),
863 (long) read_register (1),
864 (long) read_register (2),
865 (long) read_register (3),
866 (long) read_register (4),
867 (long) read_register (5),
868 (long) read_register (6),
869 (long) read_register (7));
870 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
871 (long) read_register (8),
872 (long) read_register (9),
873 (long) read_register (10),
874 (long) read_register (11),
875 (long) read_register (12),
876 (long) read_register (13),
877 (long) read_register (14),
878 (long) read_register (15));
879 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
882 printf_filtered (" ");
883 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
885 if (NR_DMAP_REGS
== 1)
886 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
889 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
891 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
893 printf_filtered ("\n");
895 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
896 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
898 char num
[MAX_REGISTER_RAW_SIZE
];
900 printf_filtered (" ");
901 read_register_gen (a
, (char *) &num
);
902 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
904 printf_filtered ("%02x", (num
[i
] & 0xff));
907 printf_filtered ("\n");
911 d10v_read_pc (ptid_t ptid
)
917 save_ptid
= inferior_ptid
;
918 inferior_ptid
= ptid
;
919 pc
= (int) read_register (PC_REGNUM
);
920 inferior_ptid
= save_ptid
;
921 retval
= d10v_make_iaddr (pc
);
926 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
930 save_ptid
= inferior_ptid
;
931 inferior_ptid
= ptid
;
932 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
933 inferior_ptid
= save_ptid
;
939 return (d10v_make_daddr (read_register (SP_REGNUM
)));
943 d10v_write_sp (CORE_ADDR val
)
945 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
949 d10v_write_fp (CORE_ADDR val
)
951 write_register (FP_REGNUM
, d10v_convert_daddr_to_raw (val
));
957 return (d10v_make_daddr (read_register (FP_REGNUM
)));
960 /* Function: push_return_address (pc)
961 Set up the return address for the inferior function call.
962 Needed for targets where we don't actually execute a JSR/BSR instruction */
965 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
967 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
972 /* When arguments must be pushed onto the stack, they go on in reverse
973 order. The below implements a FILO (stack) to do this. */
978 struct stack_item
*prev
;
982 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
983 void *contents
, int len
);
984 static struct stack_item
*
985 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
987 struct stack_item
*si
;
988 si
= xmalloc (sizeof (struct stack_item
));
989 si
->data
= xmalloc (len
);
992 memcpy (si
->data
, contents
, len
);
996 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
997 static struct stack_item
*
998 pop_stack_item (struct stack_item
*si
)
1000 struct stack_item
*dead
= si
;
1009 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1010 int struct_return
, CORE_ADDR struct_addr
)
1013 int regnum
= ARG1_REGNUM
;
1014 struct stack_item
*si
= NULL
;
1016 /* Fill in registers and arg lists */
1017 for (i
= 0; i
< nargs
; i
++)
1019 struct value
*arg
= args
[i
];
1020 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1021 char *contents
= VALUE_CONTENTS (arg
);
1022 int len
= TYPE_LENGTH (type
);
1023 /* printf ("push: type=%d len=%d\n", type->code, len); */
1025 int aligned_regnum
= (regnum
+ 1) & ~1;
1026 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1027 /* fits in a single register, do not align */
1029 long val
= extract_unsigned_integer (contents
, len
);
1030 write_register (regnum
++, val
);
1032 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1033 /* value fits in remaining registers, store keeping left
1037 regnum
= aligned_regnum
;
1038 for (b
= 0; b
< (len
& ~1); b
+= 2)
1040 long val
= extract_unsigned_integer (&contents
[b
], 2);
1041 write_register (regnum
++, val
);
1045 long val
= extract_unsigned_integer (&contents
[b
], 1);
1046 write_register (regnum
++, (val
<< 8));
1051 /* arg will go onto stack */
1052 regnum
= ARGN_REGNUM
+ 1;
1053 si
= push_stack_item (si
, contents
, len
);
1060 sp
= (sp
- si
->len
) & ~1;
1061 write_memory (sp
, si
->data
, si
->len
);
1062 si
= pop_stack_item (si
);
1069 /* Given a return value in `regbuf' with a type `valtype',
1070 extract and copy its value into `valbuf'. */
1073 d10v_extract_return_value (struct type
*type
, char regbuf
[REGISTER_BYTES
],
1077 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1079 len
= TYPE_LENGTH (type
);
1082 unsigned short c
= extract_unsigned_integer (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1083 store_unsigned_integer (valbuf
, 1, c
);
1085 else if ((len
& 1) == 0)
1086 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
), len
);
1089 /* For return values of odd size, the first byte is in the
1090 least significant part of the first register. The
1091 remaining bytes in remaining registers. Interestingly,
1092 when such values are passed in, the last byte is in the
1093 most significant byte of that same register - wierd. */
1094 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
) + 1, len
);
1099 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1100 understands. Returns number of bytes that can be transfered
1101 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1102 (segmentation fault). Since the simulator knows all about how the
1103 VM system works, we just call that to do the translation. */
1106 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1107 CORE_ADDR
*targ_addr
, int *targ_len
)
1111 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1114 d10v_imap_register
);
1115 *targ_addr
= out_addr
;
1116 *targ_len
= out_len
;
1120 /* The following code implements access to, and display of, the D10V's
1121 instruction trace buffer. The buffer consists of 64K or more
1122 4-byte words of data, of which each words includes an 8-bit count,
1123 an 8-bit segment number, and a 16-bit instruction address.
1125 In theory, the trace buffer is continuously capturing instruction
1126 data that the CPU presents on its "debug bus", but in practice, the
1127 ROMified GDB stub only enables tracing when it continues or steps
1128 the program, and stops tracing when the program stops; so it
1129 actually works for GDB to read the buffer counter out of memory and
1130 then read each trace word. The counter records where the tracing
1131 stops, but there is no record of where it started, so we remember
1132 the PC when we resumed and then search backwards in the trace
1133 buffer for a word that includes that address. This is not perfect,
1134 because you will miss trace data if the resumption PC is the target
1135 of a branch. (The value of the buffer counter is semi-random, any
1136 trace data from a previous program stop is gone.) */
1138 /* The address of the last word recorded in the trace buffer. */
1140 #define DBBC_ADDR (0xd80000)
1142 /* The base of the trace buffer, at least for the "Board_0". */
1144 #define TRACE_BUFFER_BASE (0xf40000)
1146 static void trace_command (char *, int);
1148 static void untrace_command (char *, int);
1150 static void trace_info (char *, int);
1152 static void tdisassemble_command (char *, int);
1154 static void display_trace (int, int);
1156 /* True when instruction traces are being collected. */
1160 /* Remembered PC. */
1162 static CORE_ADDR last_pc
;
1164 /* True when trace output should be displayed whenever program stops. */
1166 static int trace_display
;
1168 /* True when trace listing should include source lines. */
1170 static int default_trace_show_source
= 1;
1181 trace_command (char *args
, int from_tty
)
1183 /* Clear the host-side trace buffer, allocating space if needed. */
1184 trace_data
.size
= 0;
1185 if (trace_data
.counts
== NULL
)
1186 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1187 if (trace_data
.addrs
== NULL
)
1188 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1192 printf_filtered ("Tracing is now on.\n");
1196 untrace_command (char *args
, int from_tty
)
1200 printf_filtered ("Tracing is now off.\n");
1204 trace_info (char *args
, int from_tty
)
1208 if (trace_data
.size
)
1210 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1212 for (i
= 0; i
< trace_data
.size
; ++i
)
1214 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1216 trace_data
.counts
[i
],
1217 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1218 paddr_nz (trace_data
.addrs
[i
]));
1222 printf_filtered ("No entries in trace buffer.\n");
1224 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1227 /* Print the instruction at address MEMADDR in debugged memory,
1228 on STREAM. Returns length of the instruction, in bytes. */
1231 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1233 /* If there's no disassembler, something is very wrong. */
1234 if (tm_print_insn
== NULL
)
1235 internal_error (__FILE__
, __LINE__
,
1236 "print_insn: no disassembler");
1238 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1239 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1241 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1242 return (*tm_print_insn
) (memaddr
, &tm_print_insn_info
);
1246 d10v_eva_prepare_to_trace (void)
1251 last_pc
= read_register (PC_REGNUM
);
1254 /* Collect trace data from the target board and format it into a form
1255 more useful for display. */
1258 d10v_eva_get_trace_data (void)
1260 int count
, i
, j
, oldsize
;
1261 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1262 unsigned int last_trace
, trace_word
, next_word
;
1263 unsigned int *tmpspace
;
1268 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1270 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1272 /* Collect buffer contents from the target, stopping when we reach
1273 the word recorded when execution resumed. */
1276 while (last_trace
> 0)
1280 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1281 trace_addr
= trace_word
& 0xffff;
1283 /* Ignore an apparently nonsensical entry. */
1284 if (trace_addr
== 0xffd5)
1286 tmpspace
[count
++] = trace_word
;
1287 if (trace_addr
== last_pc
)
1293 /* Move the data to the host-side trace buffer, adjusting counts to
1294 include the last instruction executed and transforming the address
1295 into something that GDB likes. */
1297 for (i
= 0; i
< count
; ++i
)
1299 trace_word
= tmpspace
[i
];
1300 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1301 trace_addr
= trace_word
& 0xffff;
1302 next_cnt
= (next_word
>> 24) & 0xff;
1303 j
= trace_data
.size
+ count
- i
- 1;
1304 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1305 trace_data
.counts
[j
] = next_cnt
+ 1;
1308 oldsize
= trace_data
.size
;
1309 trace_data
.size
+= count
;
1314 display_trace (oldsize
, trace_data
.size
);
1318 tdisassemble_command (char *arg
, int from_tty
)
1321 CORE_ADDR low
, high
;
1327 high
= trace_data
.size
;
1329 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1331 low
= parse_and_eval_address (arg
);
1336 /* Two arguments. */
1337 *space_index
= '\0';
1338 low
= parse_and_eval_address (arg
);
1339 high
= parse_and_eval_address (space_index
+ 1);
1344 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1346 display_trace (low
, high
);
1348 printf_filtered ("End of trace dump.\n");
1349 gdb_flush (gdb_stdout
);
1353 display_trace (int low
, int high
)
1355 int i
, count
, trace_show_source
, first
, suppress
;
1356 CORE_ADDR next_address
;
1358 trace_show_source
= default_trace_show_source
;
1359 if (!have_full_symbols () && !have_partial_symbols ())
1361 trace_show_source
= 0;
1362 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1363 printf_filtered ("Trace will not display any source.\n");
1368 for (i
= low
; i
< high
; ++i
)
1370 next_address
= trace_data
.addrs
[i
];
1371 count
= trace_data
.counts
[i
];
1375 if (trace_show_source
)
1377 struct symtab_and_line sal
, sal_prev
;
1379 sal_prev
= find_pc_line (next_address
- 4, 0);
1380 sal
= find_pc_line (next_address
, 0);
1384 if (first
|| sal
.line
!= sal_prev
.line
)
1385 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1391 /* FIXME-32x64--assumes sal.pc fits in long. */
1392 printf_filtered ("No source file for address %s.\n",
1393 local_hex_string ((unsigned long) sal
.pc
));
1398 print_address (next_address
, gdb_stdout
);
1399 printf_filtered (":");
1400 printf_filtered ("\t");
1402 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1403 printf_filtered ("\n");
1404 gdb_flush (gdb_stdout
);
1410 static gdbarch_init_ftype d10v_gdbarch_init
;
1412 static struct gdbarch
*
1413 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1415 static LONGEST d10v_call_dummy_words
[] =
1417 struct gdbarch
*gdbarch
;
1419 struct gdbarch_tdep
*tdep
;
1420 gdbarch_register_name_ftype
*d10v_register_name
;
1421 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1423 /* Find a candidate among the list of pre-declared architectures. */
1424 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1426 return arches
->gdbarch
;
1428 /* None found, create a new architecture from the information
1430 tdep
= XMALLOC (struct gdbarch_tdep
);
1431 gdbarch
= gdbarch_alloc (&info
, tdep
);
1433 switch (info
.bfd_arch_info
->mach
)
1435 case bfd_mach_d10v_ts2
:
1437 d10v_register_name
= d10v_ts2_register_name
;
1438 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1439 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1440 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1441 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1442 tdep
->imap_register
= d10v_ts2_imap_register
;
1445 case bfd_mach_d10v_ts3
:
1447 d10v_register_name
= d10v_ts3_register_name
;
1448 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1449 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1450 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1451 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1452 tdep
->imap_register
= d10v_ts3_imap_register
;
1456 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1457 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1458 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1459 set_gdbarch_write_fp (gdbarch
, d10v_write_fp
);
1460 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1461 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1463 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1464 set_gdbarch_sp_regnum (gdbarch
, 15);
1465 set_gdbarch_fp_regnum (gdbarch
, 11);
1466 set_gdbarch_pc_regnum (gdbarch
, 18);
1467 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1468 set_gdbarch_register_size (gdbarch
, 2);
1469 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1470 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1471 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1472 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1473 set_gdbarch_register_virtual_size (gdbarch
, d10v_register_virtual_size
);
1474 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1475 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1477 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1478 set_gdbarch_addr_bit (gdbarch
, 32);
1479 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1480 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1481 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1482 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1483 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1484 set_gdbarch_long_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1485 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1486 double'' is 64 bits. */
1487 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1488 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1489 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1490 switch (info
.byte_order
)
1493 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1494 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1495 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1498 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1499 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1500 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1503 internal_error (__FILE__
, __LINE__
,
1504 "d10v_gdbarch_init: bad byte order for float format");
1507 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
1508 set_gdbarch_call_dummy_length (gdbarch
, 0);
1509 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
1510 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1511 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1512 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1513 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1514 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
1515 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1516 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1517 set_gdbarch_call_dummy_p (gdbarch
, 1);
1518 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1519 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
1520 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1522 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1523 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1524 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1525 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1527 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1528 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1529 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1530 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1532 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1533 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1535 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1537 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1538 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1539 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1540 set_gdbarch_function_start_offset (gdbarch
, 0);
1541 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1543 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1545 set_gdbarch_frame_args_skip (gdbarch
, 0);
1546 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1547 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1548 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1549 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1550 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
1551 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
1552 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1553 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1554 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1556 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1557 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1563 extern void (*target_resume_hook
) (void);
1564 extern void (*target_wait_loop_hook
) (void);
1567 _initialize_d10v_tdep (void)
1569 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1571 tm_print_insn
= print_insn_d10v
;
1573 target_resume_hook
= d10v_eva_prepare_to_trace
;
1574 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1576 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1578 add_com ("itrace", class_support
, trace_command
,
1579 "Enable tracing of instruction execution.");
1581 add_com ("iuntrace", class_support
, untrace_command
,
1582 "Disable tracing of instruction execution.");
1584 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1585 "Disassemble the trace buffer.\n\
1586 Two optional arguments specify a range of trace buffer entries\n\
1587 as reported by info trace (NOT addresses!).");
1589 add_info ("itrace", trace_info
,
1590 "Display info about the trace data buffer.");
1592 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1593 var_integer
, (char *) &trace_display
,
1594 "Set automatic display of trace.\n", &setlist
),
1596 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1597 var_integer
, (char *) &default_trace_show_source
,
1598 "Set display of source code with trace.\n", &setlist
),