1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
32 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "gdb/sim-d10v.h"
44 #include "sim-regno.h"
46 #include "gdb_assert.h"
52 unsigned long (*dmap_register
) (int nr
);
53 unsigned long (*imap_register
) (int nr
);
56 /* These are the addresses the D10V-EVA board maps data and
57 instruction memory to. */
60 DMEM_START
= 0x2000000,
61 IMEM_START
= 0x1000000,
62 STACK_START
= 0x200bffe
65 /* d10v register names. */
80 /* d10v calling convention. */
81 ARG1_REGNUM
= R0_REGNUM
,
82 ARGN_REGNUM
= R3_REGNUM
,
83 RET1_REGNUM
= R0_REGNUM
,
86 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
87 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
91 extern void _initialize_d10v_tdep (void);
93 static CORE_ADDR
d10v_read_sp (void);
95 static CORE_ADDR
d10v_read_fp (void);
97 static void d10v_eva_prepare_to_trace (void);
99 static void d10v_eva_get_trace_data (void);
102 d10v_stack_align (CORE_ADDR len
)
104 return (len
+ 1) & ~1;
107 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
108 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
109 and TYPE is the type (which is known to be struct, union or array).
111 The d10v returns anything less than 8 bytes in size in
115 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
119 /* The d10v only passes a struct in a register when that structure
120 has an alignment that matches the size of a register. */
121 /* If the structure doesn't fit in 4 registers, put it on the
123 if (TYPE_LENGTH (type
) > 8)
125 /* If the struct contains only one field, don't put it on the stack
126 - gcc can fit it in one or more registers. */
127 if (TYPE_NFIELDS (type
) == 1)
129 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
130 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
132 /* If the alignment changes, just assume it goes on the
134 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
137 /* If the alignment is suitable for the d10v's 16 bit registers,
138 don't put it on the stack. */
139 if (alignment
== 2 || alignment
== 4)
145 static const unsigned char *
146 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
148 static unsigned char breakpoint
[] =
149 {0x2f, 0x90, 0x5e, 0x00};
150 *lenptr
= sizeof (breakpoint
);
154 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
155 when the reg_nr isn't valid. */
159 TS2_IMAP0_REGNUM
= 32,
160 TS2_DMAP_REGNUM
= 34,
161 TS2_NR_DMAP_REGS
= 1,
166 d10v_ts2_register_name (int reg_nr
)
168 static char *register_names
[] =
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
173 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
174 "imap0", "imap1", "dmap", "a0", "a1"
178 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
180 return register_names
[reg_nr
];
185 TS3_IMAP0_REGNUM
= 36,
186 TS3_DMAP0_REGNUM
= 38,
187 TS3_NR_DMAP_REGS
= 4,
192 d10v_ts3_register_name (int reg_nr
)
194 static char *register_names
[] =
196 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
197 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
198 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
199 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
203 "dmap0", "dmap1", "dmap2", "dmap3"
207 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
209 return register_names
[reg_nr
];
212 /* Access the DMAP/IMAP registers in a target independent way.
214 Divide the D10V's 64k data space into four 16k segments:
215 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
218 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
219 0x7fff) always map to the on-chip data RAM, and the fourth always
220 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
221 unified memory or instruction memory, under the control of the
222 single DMAP register.
224 On the TS3, there are four DMAP registers, each of which controls
225 one of the segments. */
228 d10v_ts2_dmap_register (int reg_nr
)
236 return read_register (TS2_DMAP_REGNUM
);
243 d10v_ts3_dmap_register (int reg_nr
)
245 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
249 d10v_dmap_register (int reg_nr
)
251 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
255 d10v_ts2_imap_register (int reg_nr
)
257 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
261 d10v_ts3_imap_register (int reg_nr
)
263 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
267 d10v_imap_register (int reg_nr
)
269 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
272 /* MAP GDB's internal register numbering (determined by the layout fo
273 the REGISTER_BYTE array) onto the simulator's register
277 d10v_ts2_register_sim_regno (int nr
)
279 if (legacy_register_sim_regno (nr
) < 0)
280 return legacy_register_sim_regno (nr
);
281 if (nr
>= TS2_IMAP0_REGNUM
282 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
283 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
284 if (nr
== TS2_DMAP_REGNUM
)
285 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
286 if (nr
>= TS2_A0_REGNUM
287 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
288 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
293 d10v_ts3_register_sim_regno (int nr
)
295 if (legacy_register_sim_regno (nr
) < 0)
296 return legacy_register_sim_regno (nr
);
297 if (nr
>= TS3_IMAP0_REGNUM
298 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
299 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
300 if (nr
>= TS3_DMAP0_REGNUM
301 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
302 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
303 if (nr
>= TS3_A0_REGNUM
304 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
305 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
309 /* Index within `registers' of the first byte of the space for
313 d10v_register_byte (int reg_nr
)
315 if (reg_nr
< A0_REGNUM
)
317 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
318 return (A0_REGNUM
* 2
319 + (reg_nr
- A0_REGNUM
) * 8);
321 return (A0_REGNUM
* 2
323 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
326 /* Number of bytes of storage in the actual machine representation for
330 d10v_register_raw_size (int reg_nr
)
332 if (reg_nr
< A0_REGNUM
)
334 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
340 /* Return the GDB type object for the "standard" data type
341 of data in register N. */
344 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
346 if (reg_nr
== PC_REGNUM
)
347 return builtin_type_void_func_ptr
;
348 if (reg_nr
== _SP_REGNUM
|| reg_nr
== _FP_REGNUM
)
349 return builtin_type_void_data_ptr
;
350 else if (reg_nr
>= A0_REGNUM
351 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
352 return builtin_type_int64
;
354 return builtin_type_int16
;
358 d10v_daddr_p (CORE_ADDR x
)
360 return (((x
) & 0x3000000) == DMEM_START
);
364 d10v_iaddr_p (CORE_ADDR x
)
366 return (((x
) & 0x3000000) == IMEM_START
);
370 d10v_make_daddr (CORE_ADDR x
)
372 return ((x
) | DMEM_START
);
376 d10v_make_iaddr (CORE_ADDR x
)
378 if (d10v_iaddr_p (x
))
379 return x
; /* Idempotency -- x is already in the IMEM space. */
381 return (((x
) << 2) | IMEM_START
);
385 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
387 return (((x
) >> 2) & 0xffff);
391 d10v_convert_daddr_to_raw (CORE_ADDR x
)
393 return ((x
) & 0xffff);
397 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
399 /* Is it a code address? */
400 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
401 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
403 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
404 d10v_convert_iaddr_to_raw (addr
));
408 /* Strip off any upper segment bits. */
409 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
410 d10v_convert_daddr_to_raw (addr
));
415 d10v_pointer_to_address (struct type
*type
, const void *buf
)
417 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
419 /* Is it a code address? */
420 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
421 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
422 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
423 return d10v_make_iaddr (addr
);
425 return d10v_make_daddr (addr
);
428 /* Don't do anything if we have an integer, this way users can type 'x
429 <addr>' w/o having gdb outsmart them. The internal gdb conversions
430 to the correct space are taken care of in the pointer_to_address
431 function. If we don't do this, 'x $fp' wouldn't work. */
433 d10v_integer_to_address (struct type
*type
, void *buf
)
436 val
= unpack_long (type
, buf
);
440 /* Store the address of the place in which to copy the structure the
441 subroutine will return. This is called from call_function.
443 We store structs through a pointer passed in the first Argument
447 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
449 write_register (ARG1_REGNUM
, (addr
));
452 /* Write into appropriate registers a function return value
453 of type TYPE, given in virtual format.
455 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
458 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
461 /* Only char return values need to be shifted right within the first
463 if (TYPE_LENGTH (type
) == 1
464 && TYPE_CODE (type
) == TYPE_CODE_INT
)
467 tmp
[1] = *(bfd_byte
*)valbuf
;
468 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
473 /* A structure is never more than 8 bytes long. See
474 use_struct_convention(). */
475 gdb_assert (TYPE_LENGTH (type
) <= 8);
476 /* Write out most registers, stop loop before trying to write
477 out any dangling byte at the end of the buffer. */
478 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
480 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
481 (bfd_byte
*) valbuf
+ reg
* 2);
483 /* Write out any dangling byte at the end of the buffer. */
484 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
485 regcache_cooked_write_part (regcache
, reg
, 0, 1,
486 (bfd_byte
*) valbuf
+ reg
* 2);
490 /* Extract from an array REGBUF containing the (raw) register state
491 the address in which a function should return its structure value,
492 as a CORE_ADDR (or an expression that can be used as one). */
495 d10v_extract_struct_value_address (struct regcache
*regcache
)
498 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
499 return (addr
| DMEM_START
);
502 /* Immediately after a function call, return the saved pc. We can't
503 use frame->return_pc beause that is determined by reading R13 off
504 the stack and that may not be written yet. */
507 d10v_saved_pc_after_call (struct frame_info
*frame
)
509 return ((read_register (LR_REGNUM
) << 2)
514 check_prologue (unsigned short op
)
517 if ((op
& 0x7E1F) == 0x6C1F)
521 if ((op
& 0x7E3F) == 0x6E1F)
525 if ((op
& 0x7FE1) == 0x01E1)
537 if ((op
& 0x7E1F) == 0x681E)
541 if ((op
& 0x7E3F) == 0x3A1E)
548 d10v_skip_prologue (CORE_ADDR pc
)
551 unsigned short op1
, op2
;
552 CORE_ADDR func_addr
, func_end
;
553 struct symtab_and_line sal
;
555 /* If we have line debugging information, then the end of the */
556 /* prologue should the first assembly instruction of the first source line */
557 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
559 sal
= find_pc_line (func_addr
, 0);
560 if (sal
.end
&& sal
.end
< func_end
)
564 if (target_read_memory (pc
, (char *) &op
, 4))
565 return pc
; /* Can't access it -- assume no prologue. */
569 op
= (unsigned long) read_memory_integer (pc
, 4);
570 if ((op
& 0xC0000000) == 0xC0000000)
572 /* long instruction */
573 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
574 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
575 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
580 /* short instructions */
581 if ((op
& 0xC0000000) == 0x80000000)
583 op2
= (op
& 0x3FFF8000) >> 15;
588 op1
= (op
& 0x3FFF8000) >> 15;
591 if (check_prologue (op1
))
593 if (!check_prologue (op2
))
595 /* if the previous opcode was really part of the prologue */
596 /* and not just a NOP, then we want to break after both instructions */
610 struct d10v_unwind_cache
613 /* The frame's base. Used when constructing a frame ID. */
616 CORE_ADDR
*saved_regs
;
617 /* How far the SP and r11 (FP) have been offset from the start of
618 the stack frame (as defined by the previous frame's stack
627 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
633 if ((op
& 0x7E1F) == 0x6C1F)
635 n
= (op
& 0x1E0) >> 5;
636 info
->sp_offset
-= 2;
637 info
->saved_regs
[n
] = info
->sp_offset
;
642 else if ((op
& 0x7E3F) == 0x6E1F)
644 n
= (op
& 0x1E0) >> 5;
645 info
->sp_offset
-= 4;
646 info
->saved_regs
[n
] = info
->sp_offset
;
647 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
652 if ((op
& 0x7FE1) == 0x01E1)
654 n
= (op
& 0x1E) >> 1;
657 info
->sp_offset
-= n
;
664 info
->uses_frame
= 1;
665 info
->r11_offset
= info
->sp_offset
;
670 if ((op
& 0x7E1F) == 0x6816)
672 n
= (op
& 0x1E0) >> 5;
673 info
->saved_regs
[n
] = info
->r11_offset
;
682 if ((op
& 0x7E1F) == 0x681E)
684 n
= (op
& 0x1E0) >> 5;
685 info
->saved_regs
[n
] = info
->sp_offset
;
690 if ((op
& 0x7E3F) == 0x3A1E)
692 n
= (op
& 0x1E0) >> 5;
693 info
->saved_regs
[n
] = info
->sp_offset
;
694 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
701 /* Put here the code to store, into fi->saved_regs, the addresses of
702 the saved registers of frame described by FRAME_INFO. This
703 includes special registers such as pc and fp saved in special ways
704 in the stack frame. sp is even more special: the address we return
705 for it IS the sp for the next frame. */
707 struct d10v_unwind_cache
*
708 d10v_frame_unwind_cache (struct frame_info
*fi
,
715 unsigned short op1
, op2
;
717 struct d10v_unwind_cache
*info
;
722 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
724 info
->saved_regs
= frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS
);
730 pc
= get_pc_function_start (get_frame_pc (fi
));
732 info
->uses_frame
= 0;
735 op
= (unsigned long) read_memory_integer (pc
, 4);
736 if ((op
& 0xC0000000) == 0xC0000000)
738 /* long instruction */
739 if ((op
& 0x3FFF0000) == 0x01FF0000)
742 short n
= op
& 0xFFFF;
743 info
->sp_offset
+= n
;
745 else if ((op
& 0x3F0F0000) == 0x340F0000)
747 /* st rn, @(offset,sp) */
748 short offset
= op
& 0xFFFF;
749 short n
= (op
>> 20) & 0xF;
750 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
752 else if ((op
& 0x3F1F0000) == 0x350F0000)
754 /* st2w rn, @(offset,sp) */
755 short offset
= op
& 0xFFFF;
756 short n
= (op
>> 20) & 0xF;
757 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
758 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
765 /* short instructions */
766 if ((op
& 0xC0000000) == 0x80000000)
768 op2
= (op
& 0x3FFF8000) >> 15;
773 op1
= (op
& 0x3FFF8000) >> 15;
776 if (!prologue_find_regs (info
, op1
, pc
)
777 || !prologue_find_regs (info
, op2
, pc
))
783 info
->size
= -info
->sp_offset
;
785 /* Compute the frame's base, and the previous frame's SP. */
786 if (info
->uses_frame
)
788 /* The SP was moved to the FP. This indicates that a new frame
789 was created. Get THIS frame's FP value by unwinding it from
791 frame_read_unsigned_register (fi
, FP_REGNUM
, &this_base
);
792 /* The FP points at the last saved register. Adjust the FP back
793 to before the first saved register giving the SP. */
794 prev_sp
= this_base
+ info
->size
;
796 else if (info
->saved_regs
[SP_REGNUM
])
798 /* The SP was saved (which is very unusual), the frame base is
799 just the PREV's frame's TOP-OF-STACK. */
800 this_base
= read_memory_unsigned_integer (info
->saved_regs
[SP_REGNUM
],
801 register_size (current_gdbarch
,
807 /* Assume that the FP is this frame's SP but with that pushed
808 stack space added back. */
809 frame_read_unsigned_register (fi
, SP_REGNUM
, &this_base
);
810 prev_sp
= this_base
+ info
->size
;
813 info
->base
= d10v_make_daddr (this_base
);
814 prev_sp
= d10v_make_daddr (prev_sp
);
816 /* Adjust all the saved registers so that they contain addresses and
818 for (i
= 0; i
< NUM_REGS
- 1; i
++)
819 if (info
->saved_regs
[i
])
821 info
->saved_regs
[i
] = (prev_sp
+ info
->saved_regs
[i
]);
824 if (info
->saved_regs
[LR_REGNUM
])
827 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
828 register_size (current_gdbarch
, LR_REGNUM
));
829 info
->return_pc
= d10v_make_iaddr (return_pc
);
834 frame_read_unsigned_register (fi
, LR_REGNUM
, &return_pc
);
835 info
->return_pc
= d10v_make_iaddr (return_pc
);
838 /* The SP_REGNUM is special. Instead of the address of the SP, the
839 previous frame's SP value is saved. */
840 info
->saved_regs
[SP_REGNUM
] = prev_sp
;
846 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
847 struct frame_info
*frame
, int regnum
, int all
)
851 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
856 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
857 frame_read_unsigned_register (frame
, PC_REGNUM
, &pc
);
858 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
859 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
860 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
861 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
862 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
863 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
864 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
869 for (group
= 0; group
< 16; group
+= 8)
872 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
873 for (r
= group
; r
< group
+ 8; r
++)
876 frame_read_unsigned_register (frame
, r
, &tmp
);
877 fprintf_filtered (file
, " %04lx", (long) tmp
);
879 fprintf_filtered (file
, "\n");
883 /* Note: The IMAP/DMAP registers don't participate in function
884 calls. Don't bother trying to unwind them. */
888 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
891 fprintf_filtered (file
, " ");
892 fprintf_filtered (file
, "IMAP%d %04lx", a
, d10v_imap_register (a
));
894 if (NR_DMAP_REGS
== 1)
895 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
896 fprintf_filtered (file
, " DMAP %04lx\n", d10v_dmap_register (2));
899 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
901 fprintf_filtered (file
, " DMAP%d %04lx", a
, d10v_dmap_register (a
));
903 fprintf_filtered (file
, "\n");
908 char *num
= alloca (max_register_size (gdbarch
));
910 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
911 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
914 fprintf_filtered (file
, " ");
915 frame_register_read (frame
, a
, num
);
916 for (i
= 0; i
< max_register_size (current_gdbarch
); i
++)
918 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
922 fprintf_filtered (file
, "\n");
926 show_regs (char *args
, int from_tty
)
928 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
929 get_current_frame (), -1, 1);
933 d10v_read_pc (ptid_t ptid
)
939 save_ptid
= inferior_ptid
;
940 inferior_ptid
= ptid
;
941 pc
= (int) read_register (PC_REGNUM
);
942 inferior_ptid
= save_ptid
;
943 retval
= d10v_make_iaddr (pc
);
948 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
952 save_ptid
= inferior_ptid
;
953 inferior_ptid
= ptid
;
954 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
955 inferior_ptid
= save_ptid
;
961 return (d10v_make_daddr (read_register (SP_REGNUM
)));
965 d10v_write_sp (CORE_ADDR val
)
967 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
973 return (d10v_make_daddr (read_register (FP_REGNUM
)));
976 /* Function: push_return_address (pc)
977 Set up the return address for the inferior function call.
978 Needed for targets where we don't actually execute a JSR/BSR instruction */
981 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
983 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
988 /* When arguments must be pushed onto the stack, they go on in reverse
989 order. The below implements a FILO (stack) to do this. */
994 struct stack_item
*prev
;
998 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
999 void *contents
, int len
);
1000 static struct stack_item
*
1001 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1003 struct stack_item
*si
;
1004 si
= xmalloc (sizeof (struct stack_item
));
1005 si
->data
= xmalloc (len
);
1008 memcpy (si
->data
, contents
, len
);
1012 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1013 static struct stack_item
*
1014 pop_stack_item (struct stack_item
*si
)
1016 struct stack_item
*dead
= si
;
1025 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1026 int struct_return
, CORE_ADDR struct_addr
)
1029 int regnum
= ARG1_REGNUM
;
1030 struct stack_item
*si
= NULL
;
1033 /* If struct_return is true, then the struct return address will
1034 consume one argument-passing register. No need to actually
1035 write the value to the register -- that's done by
1036 d10v_store_struct_return(). */
1041 /* Fill in registers and arg lists */
1042 for (i
= 0; i
< nargs
; i
++)
1044 struct value
*arg
= args
[i
];
1045 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1046 char *contents
= VALUE_CONTENTS (arg
);
1047 int len
= TYPE_LENGTH (type
);
1048 int aligned_regnum
= (regnum
+ 1) & ~1;
1050 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1051 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1052 /* fits in a single register, do not align */
1054 val
= extract_unsigned_integer (contents
, len
);
1055 write_register (regnum
++, val
);
1057 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1058 /* value fits in remaining registers, store keeping left
1062 regnum
= aligned_regnum
;
1063 for (b
= 0; b
< (len
& ~1); b
+= 2)
1065 val
= extract_unsigned_integer (&contents
[b
], 2);
1066 write_register (regnum
++, val
);
1070 val
= extract_unsigned_integer (&contents
[b
], 1);
1071 write_register (regnum
++, (val
<< 8));
1076 /* arg will go onto stack */
1077 regnum
= ARGN_REGNUM
+ 1;
1078 si
= push_stack_item (si
, contents
, len
);
1084 sp
= (sp
- si
->len
) & ~1;
1085 write_memory (sp
, si
->data
, si
->len
);
1086 si
= pop_stack_item (si
);
1093 /* Given a return value in `regbuf' with a type `valtype',
1094 extract and copy its value into `valbuf'. */
1097 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1102 printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type
),
1103 TYPE_LENGTH (type
), RET1_REGNUM
- R0_REGNUM
,
1104 (int) extract_unsigned_integer (regbuf
+ REGISTER_BYTE(RET1_REGNUM
),
1105 register_size (current_gdbarch
, RET1_REGNUM
)));
1107 if (TYPE_LENGTH (type
) == 1)
1110 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1111 store_unsigned_integer (valbuf
, 1, c
);
1115 /* For return values of odd size, the first byte is in the
1116 least significant part of the first register. The
1117 remaining bytes in remaining registers. Interestingly, when
1118 such values are passed in, the last byte is in the most
1119 significant byte of that same register - wierd. */
1120 int reg
= RET1_REGNUM
;
1122 if (TYPE_LENGTH (type
) & 1)
1124 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1125 (bfd_byte
*)valbuf
+ off
);
1129 /* Transfer the remaining registers. */
1130 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1132 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1133 (bfd_byte
*) valbuf
+ off
);
1138 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1139 understands. Returns number of bytes that can be transfered
1140 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1141 (segmentation fault). Since the simulator knows all about how the
1142 VM system works, we just call that to do the translation. */
1145 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1146 CORE_ADDR
*targ_addr
, int *targ_len
)
1150 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1153 d10v_imap_register
);
1154 *targ_addr
= out_addr
;
1155 *targ_len
= out_len
;
1159 /* The following code implements access to, and display of, the D10V's
1160 instruction trace buffer. The buffer consists of 64K or more
1161 4-byte words of data, of which each words includes an 8-bit count,
1162 an 8-bit segment number, and a 16-bit instruction address.
1164 In theory, the trace buffer is continuously capturing instruction
1165 data that the CPU presents on its "debug bus", but in practice, the
1166 ROMified GDB stub only enables tracing when it continues or steps
1167 the program, and stops tracing when the program stops; so it
1168 actually works for GDB to read the buffer counter out of memory and
1169 then read each trace word. The counter records where the tracing
1170 stops, but there is no record of where it started, so we remember
1171 the PC when we resumed and then search backwards in the trace
1172 buffer for a word that includes that address. This is not perfect,
1173 because you will miss trace data if the resumption PC is the target
1174 of a branch. (The value of the buffer counter is semi-random, any
1175 trace data from a previous program stop is gone.) */
1177 /* The address of the last word recorded in the trace buffer. */
1179 #define DBBC_ADDR (0xd80000)
1181 /* The base of the trace buffer, at least for the "Board_0". */
1183 #define TRACE_BUFFER_BASE (0xf40000)
1185 static void trace_command (char *, int);
1187 static void untrace_command (char *, int);
1189 static void trace_info (char *, int);
1191 static void tdisassemble_command (char *, int);
1193 static void display_trace (int, int);
1195 /* True when instruction traces are being collected. */
1199 /* Remembered PC. */
1201 static CORE_ADDR last_pc
;
1203 /* True when trace output should be displayed whenever program stops. */
1205 static int trace_display
;
1207 /* True when trace listing should include source lines. */
1209 static int default_trace_show_source
= 1;
1220 trace_command (char *args
, int from_tty
)
1222 /* Clear the host-side trace buffer, allocating space if needed. */
1223 trace_data
.size
= 0;
1224 if (trace_data
.counts
== NULL
)
1225 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1226 if (trace_data
.addrs
== NULL
)
1227 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1231 printf_filtered ("Tracing is now on.\n");
1235 untrace_command (char *args
, int from_tty
)
1239 printf_filtered ("Tracing is now off.\n");
1243 trace_info (char *args
, int from_tty
)
1247 if (trace_data
.size
)
1249 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1251 for (i
= 0; i
< trace_data
.size
; ++i
)
1253 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1255 trace_data
.counts
[i
],
1256 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1257 paddr_nz (trace_data
.addrs
[i
]));
1261 printf_filtered ("No entries in trace buffer.\n");
1263 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1266 /* Print the instruction at address MEMADDR in debugged memory,
1267 on STREAM. Returns length of the instruction, in bytes. */
1270 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1272 /* If there's no disassembler, something is very wrong. */
1273 if (tm_print_insn
== NULL
)
1274 internal_error (__FILE__
, __LINE__
,
1275 "print_insn: no disassembler");
1277 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1278 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1280 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1281 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1285 d10v_eva_prepare_to_trace (void)
1290 last_pc
= read_register (PC_REGNUM
);
1293 /* Collect trace data from the target board and format it into a form
1294 more useful for display. */
1297 d10v_eva_get_trace_data (void)
1299 int count
, i
, j
, oldsize
;
1300 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1301 unsigned int last_trace
, trace_word
, next_word
;
1302 unsigned int *tmpspace
;
1307 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1309 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1311 /* Collect buffer contents from the target, stopping when we reach
1312 the word recorded when execution resumed. */
1315 while (last_trace
> 0)
1319 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1320 trace_addr
= trace_word
& 0xffff;
1322 /* Ignore an apparently nonsensical entry. */
1323 if (trace_addr
== 0xffd5)
1325 tmpspace
[count
++] = trace_word
;
1326 if (trace_addr
== last_pc
)
1332 /* Move the data to the host-side trace buffer, adjusting counts to
1333 include the last instruction executed and transforming the address
1334 into something that GDB likes. */
1336 for (i
= 0; i
< count
; ++i
)
1338 trace_word
= tmpspace
[i
];
1339 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1340 trace_addr
= trace_word
& 0xffff;
1341 next_cnt
= (next_word
>> 24) & 0xff;
1342 j
= trace_data
.size
+ count
- i
- 1;
1343 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1344 trace_data
.counts
[j
] = next_cnt
+ 1;
1347 oldsize
= trace_data
.size
;
1348 trace_data
.size
+= count
;
1353 display_trace (oldsize
, trace_data
.size
);
1357 tdisassemble_command (char *arg
, int from_tty
)
1360 CORE_ADDR low
, high
;
1366 high
= trace_data
.size
;
1368 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1370 low
= parse_and_eval_address (arg
);
1375 /* Two arguments. */
1376 *space_index
= '\0';
1377 low
= parse_and_eval_address (arg
);
1378 high
= parse_and_eval_address (space_index
+ 1);
1383 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1385 display_trace (low
, high
);
1387 printf_filtered ("End of trace dump.\n");
1388 gdb_flush (gdb_stdout
);
1392 display_trace (int low
, int high
)
1394 int i
, count
, trace_show_source
, first
, suppress
;
1395 CORE_ADDR next_address
;
1397 trace_show_source
= default_trace_show_source
;
1398 if (!have_full_symbols () && !have_partial_symbols ())
1400 trace_show_source
= 0;
1401 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1402 printf_filtered ("Trace will not display any source.\n");
1407 for (i
= low
; i
< high
; ++i
)
1409 next_address
= trace_data
.addrs
[i
];
1410 count
= trace_data
.counts
[i
];
1414 if (trace_show_source
)
1416 struct symtab_and_line sal
, sal_prev
;
1418 sal_prev
= find_pc_line (next_address
- 4, 0);
1419 sal
= find_pc_line (next_address
, 0);
1423 if (first
|| sal
.line
!= sal_prev
.line
)
1424 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1430 /* FIXME-32x64--assumes sal.pc fits in long. */
1431 printf_filtered ("No source file for address %s.\n",
1432 local_hex_string ((unsigned long) sal
.pc
));
1437 print_address (next_address
, gdb_stdout
);
1438 printf_filtered (":");
1439 printf_filtered ("\t");
1441 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1442 printf_filtered ("\n");
1443 gdb_flush (gdb_stdout
);
1449 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1452 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1453 return d10v_make_iaddr (pc
);
1456 /* Given a GDB frame, determine the address of the calling function's
1457 frame. This will be used to create a new GDB frame struct. */
1460 d10v_frame_id_unwind (struct frame_info
*frame
,
1462 struct frame_id
*id
)
1464 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (frame
, cache
);
1467 /* Start with a NULL frame ID. */
1468 (*id
) = null_frame_id
;
1470 if (info
->return_pc
== IMEM_START
1471 || info
->return_pc
<= IMEM_START
1472 || inside_entry_file (info
->return_pc
))
1474 /* This is meant to halt the backtrace at "_start".
1475 Make sure we don't halt it at a generic dummy frame. */
1479 if (!info
->saved_regs
[FP_REGNUM
])
1481 if (!info
->saved_regs
[SP_REGNUM
]
1482 || info
->saved_regs
[SP_REGNUM
] == STACK_START
)
1485 id
->base
= info
->saved_regs
[SP_REGNUM
];
1486 id
->pc
= info
->return_pc
;
1489 addr
= read_memory_unsigned_integer (info
->saved_regs
[FP_REGNUM
],
1490 register_size (current_gdbarch
, FP_REGNUM
));
1494 id
->base
= d10v_make_daddr (addr
);
1495 id
->pc
= info
->return_pc
;
1499 saved_regs_unwinder (struct frame_info
*frame
,
1500 CORE_ADDR
*saved_regs
,
1501 int regnum
, int *optimizedp
,
1502 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1503 int *realnump
, void *bufferp
)
1505 /* If we're using generic dummy frames, we'd better not be in a call
1506 dummy. (generic_call_dummy_register_unwind ought to have been called
1508 gdb_assert (!(DEPRECATED_USE_GENERIC_DUMMY_FRAMES
1509 && (get_frame_type (frame
) == DUMMY_FRAME
)));
1511 if (saved_regs
[regnum
] != 0)
1513 if (regnum
== SP_REGNUM
)
1515 /* SP register treated specially. */
1520 if (bufferp
!= NULL
)
1521 store_address (bufferp
, register_size (current_gdbarch
, regnum
),
1522 saved_regs
[regnum
]);
1526 /* Any other register is saved in memory, fetch it but cache
1527 a local copy of its value. */
1529 *lvalp
= lval_memory
;
1530 *addrp
= saved_regs
[regnum
];
1532 if (bufferp
!= NULL
)
1534 /* Read the value in from memory. */
1535 read_memory (saved_regs
[regnum
], bufferp
,
1536 register_size (current_gdbarch
, regnum
));
1542 /* No luck, assume this and the next frame have the same register
1543 value. If a value is needed, pass the request on down the chain;
1544 otherwise just return an indication that the value is in the same
1545 register as the next frame. */
1546 frame_register (frame
, regnum
, optimizedp
, lvalp
, addrp
,
1552 d10v_frame_register_unwind (struct frame_info
*frame
,
1554 int regnum
, int *optimizedp
,
1555 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1556 int *realnump
, void *bufferp
)
1558 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (frame
, cache
);
1559 if (regnum
== PC_REGNUM
)
1561 /* The call instruction saves the caller's PC in LR. The
1562 function prologue of the callee may then save the LR on the
1563 stack. Find that possibly saved LR value and return it. */
1564 saved_regs_unwinder (frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1565 lvalp
, addrp
, realnump
, bufferp
);
1569 saved_regs_unwinder (frame
, info
->saved_regs
, regnum
, optimizedp
,
1570 lvalp
, addrp
, realnump
, bufferp
);
1576 d10v_frame_pop (struct frame_info
*fi
, void **unwind_cache
,
1577 struct regcache
*regcache
)
1579 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (fi
, unwind_cache
);
1584 fp
= get_frame_base (fi
);
1586 /* now update the current registers with the old values */
1587 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
1589 frame_unwind_register (fi
, regnum
, raw_buffer
);
1590 regcache_cooked_write (regcache
, regnum
, raw_buffer
);
1592 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
1594 frame_unwind_register (fi
, regnum
, raw_buffer
);
1595 regcache_cooked_write (regcache
, regnum
, raw_buffer
);
1597 frame_unwind_register (fi
, PSW_REGNUM
, raw_buffer
);
1598 regcache_cooked_write (regcache
, PSW_REGNUM
, raw_buffer
);
1600 frame_unwind_register (fi
, PC_REGNUM
, raw_buffer
);
1601 regcache_cooked_write (regcache
, PC_REGNUM
, raw_buffer
);
1603 store_unsigned_integer (raw_buffer
,
1604 register_size (current_gdbarch
, SP_REGNUM
),
1606 regcache_cooked_write (regcache
, SP_REGNUM
, raw_buffer
);
1608 target_store_registers (-1);
1609 flush_cached_frames ();
1612 static struct frame_unwind d10v_frame_unwind
= {
1614 d10v_frame_id_unwind
,
1615 d10v_frame_register_unwind
1618 const struct frame_unwind
*
1619 d10v_frame_p (CORE_ADDR pc
)
1621 return &d10v_frame_unwind
;
1624 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1625 dummy frame. The frame ID's base needs to match the TOS value
1626 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1629 static struct frame_id
1630 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1634 id
.pc
= frame_pc_unwind (next_frame
);
1635 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &base
);
1636 id
.base
= d10v_make_daddr (base
);
1640 static gdbarch_init_ftype d10v_gdbarch_init
;
1642 static struct gdbarch
*
1643 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1645 static LONGEST d10v_call_dummy_words
[] =
1647 struct gdbarch
*gdbarch
;
1649 struct gdbarch_tdep
*tdep
;
1650 gdbarch_register_name_ftype
*d10v_register_name
;
1651 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1653 /* Find a candidate among the list of pre-declared architectures. */
1654 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1656 return arches
->gdbarch
;
1658 /* None found, create a new architecture from the information
1660 tdep
= XMALLOC (struct gdbarch_tdep
);
1661 gdbarch
= gdbarch_alloc (&info
, tdep
);
1663 switch (info
.bfd_arch_info
->mach
)
1665 case bfd_mach_d10v_ts2
:
1667 d10v_register_name
= d10v_ts2_register_name
;
1668 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1669 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1670 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1671 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1672 tdep
->imap_register
= d10v_ts2_imap_register
;
1675 case bfd_mach_d10v_ts3
:
1677 d10v_register_name
= d10v_ts3_register_name
;
1678 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1679 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1680 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1681 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1682 tdep
->imap_register
= d10v_ts3_imap_register
;
1686 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1687 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1688 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1689 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1690 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1692 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1693 set_gdbarch_sp_regnum (gdbarch
, 15);
1694 set_gdbarch_fp_regnum (gdbarch
, 11);
1695 set_gdbarch_pc_regnum (gdbarch
, 18);
1696 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1697 set_gdbarch_register_size (gdbarch
, 2);
1698 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1699 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1700 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1701 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1702 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1704 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1705 set_gdbarch_addr_bit (gdbarch
, 32);
1706 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1707 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1708 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1709 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1710 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1711 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1712 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1713 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1714 double'' is 64 bits. */
1715 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1716 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1717 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1718 switch (info
.byte_order
)
1720 case BFD_ENDIAN_BIG
:
1721 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1722 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1723 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1725 case BFD_ENDIAN_LITTLE
:
1726 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1727 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1728 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1731 internal_error (__FILE__
, __LINE__
,
1732 "d10v_gdbarch_init: bad byte order for float format");
1735 set_gdbarch_call_dummy_length (gdbarch
, 0);
1736 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1737 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1738 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1739 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1740 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1741 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1742 set_gdbarch_call_dummy_p (gdbarch
, 1);
1743 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1744 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1746 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1747 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1748 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1750 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1751 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1752 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1753 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1755 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1756 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1757 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1758 set_gdbarch_function_start_offset (gdbarch
, 0);
1759 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1761 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1763 set_gdbarch_frame_args_skip (gdbarch
, 0);
1764 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1766 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1767 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1768 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1770 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1771 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1773 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1775 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1777 /* Methods for saving / extracting a dummy frame's ID. */
1778 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1779 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1781 /* Return the unwound PC value. */
1782 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1788 extern void (*target_resume_hook
) (void);
1789 extern void (*target_wait_loop_hook
) (void);
1792 _initialize_d10v_tdep (void)
1794 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1796 tm_print_insn
= print_insn_d10v
;
1798 target_resume_hook
= d10v_eva_prepare_to_trace
;
1799 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1801 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1804 add_com ("itrace", class_support
, trace_command
,
1805 "Enable tracing of instruction execution.");
1807 add_com ("iuntrace", class_support
, untrace_command
,
1808 "Disable tracing of instruction execution.");
1810 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1811 "Disassemble the trace buffer.\n\
1812 Two optional arguments specify a range of trace buffer entries\n\
1813 as reported by info trace (NOT addresses!).");
1815 add_info ("itrace", trace_info
,
1816 "Display info about the trace data buffer.");
1818 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1819 var_integer
, (char *) &trace_display
,
1820 "Set automatic display of trace.\n", &setlist
),
1822 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1823 var_integer
, (char *) &default_trace_show_source
,
1824 "Set display of source code with trace.\n", &setlist
),