1 /* Target-dependent code for Renesas D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
47 #include "trad-frame.h"
49 #include "gdb_assert.h"
55 unsigned long (*dmap_register
) (void *regcache
, int nr
);
56 unsigned long (*imap_register
) (void *regcache
, int nr
);
59 /* These are the addresses the D10V-EVA board maps data and
60 instruction memory to. */
63 DMEM_START
= 0x2000000,
64 IMEM_START
= 0x1000000,
65 STACK_START
= 0x200bffe
68 /* d10v register names. */
83 /* d10v calling convention. */
84 ARG1_REGNUM
= R0_REGNUM
,
85 ARGN_REGNUM
= R3_REGNUM
89 nr_dmap_regs (struct gdbarch
*gdbarch
)
91 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
95 a0_regnum (struct gdbarch
*gdbarch
)
97 return gdbarch_tdep (gdbarch
)->a0_regnum
;
100 /* Local functions */
102 extern void _initialize_d10v_tdep (void);
104 static void d10v_eva_prepare_to_trace (void);
106 static void d10v_eva_get_trace_data (void);
109 d10v_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
111 /* Align to the size of an instruction (so that they can safely be
112 pushed onto the stack. */
116 static const unsigned char *
117 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
119 static unsigned char breakpoint
[] =
120 {0x2f, 0x90, 0x5e, 0x00};
121 *lenptr
= sizeof (breakpoint
);
125 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
126 when the reg_nr isn't valid. */
130 TS2_IMAP0_REGNUM
= 32,
131 TS2_DMAP_REGNUM
= 34,
132 TS2_NR_DMAP_REGS
= 1,
137 d10v_ts2_register_name (int reg_nr
)
139 static char *register_names
[] =
141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
144 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
145 "imap0", "imap1", "dmap", "a0", "a1"
149 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
151 return register_names
[reg_nr
];
156 TS3_IMAP0_REGNUM
= 36,
157 TS3_DMAP0_REGNUM
= 38,
158 TS3_NR_DMAP_REGS
= 4,
163 d10v_ts3_register_name (int reg_nr
)
165 static char *register_names
[] =
167 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
168 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
169 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
170 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
174 "dmap0", "dmap1", "dmap2", "dmap3"
178 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
180 return register_names
[reg_nr
];
183 /* Access the DMAP/IMAP registers in a target independent way.
185 Divide the D10V's 64k data space into four 16k segments:
186 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
189 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
190 0x7fff) always map to the on-chip data RAM, and the fourth always
191 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
192 unified memory or instruction memory, under the control of the
193 single DMAP register.
195 On the TS3, there are four DMAP registers, each of which controls
196 one of the segments. */
199 d10v_ts2_dmap_register (void *regcache
, int reg_nr
)
209 regcache_cooked_read_unsigned (regcache
, TS2_DMAP_REGNUM
, ®
);
218 d10v_ts3_dmap_register (void *regcache
, int reg_nr
)
221 regcache_cooked_read_unsigned (regcache
, TS3_DMAP0_REGNUM
+ reg_nr
, ®
);
226 d10v_ts2_imap_register (void *regcache
, int reg_nr
)
229 regcache_cooked_read_unsigned (regcache
, TS2_IMAP0_REGNUM
+ reg_nr
, ®
);
234 d10v_ts3_imap_register (void *regcache
, int reg_nr
)
237 regcache_cooked_read_unsigned (regcache
, TS3_IMAP0_REGNUM
+ reg_nr
, ®
);
241 /* MAP GDB's internal register numbering (determined by the layout
242 from the DEPRECATED_REGISTER_BYTE array) onto the simulator's
243 register numbering. */
246 d10v_ts2_register_sim_regno (int nr
)
248 /* Only makes sense to supply raw registers. */
249 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
250 if (nr
>= TS2_IMAP0_REGNUM
251 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
252 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
253 if (nr
== TS2_DMAP_REGNUM
)
254 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
255 if (nr
>= TS2_A0_REGNUM
256 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
257 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
262 d10v_ts3_register_sim_regno (int nr
)
264 /* Only makes sense to supply raw registers. */
265 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
266 if (nr
>= TS3_IMAP0_REGNUM
267 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
268 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
269 if (nr
>= TS3_DMAP0_REGNUM
270 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
271 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
272 if (nr
>= TS3_A0_REGNUM
273 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
274 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
278 /* Return the GDB type object for the "standard" data type
279 of data in register N. */
282 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
284 if (reg_nr
== D10V_PC_REGNUM
)
285 return builtin_type_void_func_ptr
;
286 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
287 return builtin_type_void_data_ptr
;
288 else if (reg_nr
>= a0_regnum (gdbarch
)
289 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
290 return builtin_type_int64
;
292 return builtin_type_int16
;
296 d10v_daddr_p (CORE_ADDR x
)
298 return (((x
) & 0x3000000) == DMEM_START
);
302 d10v_iaddr_p (CORE_ADDR x
)
304 return (((x
) & 0x3000000) == IMEM_START
);
308 d10v_make_daddr (CORE_ADDR x
)
310 return ((x
) | DMEM_START
);
314 d10v_make_iaddr (CORE_ADDR x
)
316 if (d10v_iaddr_p (x
))
317 return x
; /* Idempotency -- x is already in the IMEM space. */
319 return (((x
) << 2) | IMEM_START
);
323 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
325 return (((x
) >> 2) & 0xffff);
329 d10v_convert_daddr_to_raw (CORE_ADDR x
)
331 return ((x
) & 0xffff);
335 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
337 /* Is it a code address? */
338 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
339 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
341 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
342 d10v_convert_iaddr_to_raw (addr
));
346 /* Strip off any upper segment bits. */
347 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
348 d10v_convert_daddr_to_raw (addr
));
353 d10v_pointer_to_address (struct type
*type
, const void *buf
)
355 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
356 /* Is it a code address? */
357 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
358 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
359 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
360 return d10v_make_iaddr (addr
);
362 return d10v_make_daddr (addr
);
365 /* Don't do anything if we have an integer, this way users can type 'x
366 <addr>' w/o having gdb outsmart them. The internal gdb conversions
367 to the correct space are taken care of in the pointer_to_address
368 function. If we don't do this, 'x $fp' wouldn't work. */
370 d10v_integer_to_address (struct type
*type
, void *buf
)
373 val
= unpack_long (type
, buf
);
377 /* Handle the d10v's return_value convention. */
379 static enum return_value_convention
380 d10v_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
381 struct regcache
*regcache
, void *readbuf
,
382 const void *writebuf
)
384 if (TYPE_LENGTH (valtype
) > 8)
385 /* Anything larger than 8 bytes (4 registers) goes on the stack. */
386 return RETURN_VALUE_STRUCT_CONVENTION
;
387 if (TYPE_LENGTH (valtype
) == 5
388 || TYPE_LENGTH (valtype
) == 6)
389 /* Anything 5 or 6 bytes in size goes in memory. Contents don't
390 appear to matter. Note that 7 and 8 byte objects do end up in
392 return RETURN_VALUE_STRUCT_CONVENTION
;
393 if (TYPE_LENGTH (valtype
) == 1)
395 /* All single byte values go in a register stored right-aligned.
396 Note: 2 byte integer values are handled further down. */
399 /* Since TYPE is smaller than the register, there isn't a
400 sign extension problem. Let the extraction truncate the
403 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
,
405 store_unsigned_integer (readbuf
, TYPE_LENGTH (valtype
), regval
);
411 if (TYPE_CODE (valtype
) == TYPE_CODE_INT
)
412 /* Some sort of integer value stored in R0. Use
413 unpack_long since that should handle any required sign
415 regval
= unpack_long (valtype
, writebuf
);
417 /* Some other type. Don't sign-extend the value when
418 storing it in the register. */
419 regval
= extract_unsigned_integer (writebuf
, 1);
420 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, regval
);
422 return RETURN_VALUE_REGISTER_CONVENTION
;
424 if ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
425 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
)
426 && TYPE_NFIELDS (valtype
) > 1
427 && TYPE_FIELD_BITPOS (valtype
, 1) == 8)
428 /* If a composite is 8 bit aligned (determined by looking at the
429 start address of the second field), put it in memory. */
430 return RETURN_VALUE_STRUCT_CONVENTION
;
431 /* Assume it is in registers. */
432 if (writebuf
|| readbuf
)
435 /* Per above, the value is never more than 8 bytes long. */
436 gdb_assert (TYPE_LENGTH (valtype
) <= 8);
437 /* Xfer 2 bytes at a time. */
438 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (valtype
); reg
++)
441 regcache_cooked_read (regcache
, R0_REGNUM
+ reg
,
442 (bfd_byte
*) readbuf
+ reg
* 2);
444 regcache_cooked_write (regcache
, R0_REGNUM
+ reg
,
445 (bfd_byte
*) writebuf
+ reg
* 2);
447 /* Any trailing byte ends up _left_ aligned. */
448 if ((reg
* 2) < TYPE_LENGTH (valtype
))
451 regcache_cooked_read_part (regcache
, R0_REGNUM
+ reg
,
452 0, 1, (bfd_byte
*) readbuf
+ reg
* 2);
454 regcache_cooked_write_part (regcache
, R0_REGNUM
+ reg
,
455 0, 1, (bfd_byte
*) writebuf
+ reg
* 2);
458 return RETURN_VALUE_REGISTER_CONVENTION
;
462 check_prologue (unsigned short op
)
465 if ((op
& 0x7E1F) == 0x6C1F)
469 if ((op
& 0x7E3F) == 0x6E1F)
473 if ((op
& 0x7FE1) == 0x01E1)
485 if ((op
& 0x7E1F) == 0x681E)
489 if ((op
& 0x7E3F) == 0x3A1E)
496 d10v_skip_prologue (CORE_ADDR pc
)
499 unsigned short op1
, op2
;
500 CORE_ADDR func_addr
, func_end
;
501 struct symtab_and_line sal
;
503 /* If we have line debugging information, then the end of the prologue
504 should be the first assembly instruction of the first source line. */
505 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
507 sal
= find_pc_line (func_addr
, 0);
508 if (sal
.end
&& sal
.end
< func_end
)
512 if (target_read_memory (pc
, (char *) &op
, 4))
513 return pc
; /* Can't access it -- assume no prologue. */
517 op
= (unsigned long) read_memory_integer (pc
, 4);
518 if ((op
& 0xC0000000) == 0xC0000000)
520 /* long instruction */
521 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
522 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
523 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
528 /* short instructions */
529 if ((op
& 0xC0000000) == 0x80000000)
531 op2
= (op
& 0x3FFF8000) >> 15;
536 op1
= (op
& 0x3FFF8000) >> 15;
539 if (check_prologue (op1
))
541 if (!check_prologue (op2
))
543 /* If the previous opcode was really part of the
544 prologue and not just a NOP, then we want to
545 break after both instructions. */
559 struct d10v_unwind_cache
561 /* The previous frame's inner most stack address. Used as this
562 frame ID's stack_addr. */
564 /* The frame's base, optionally used by the high-level debug info. */
567 /* How far the SP and r11 (FP) have been offset from the start of
568 the stack frame (as defined by the previous frame's stack
573 /* Table indicating the location of each and every register. */
574 struct trad_frame_saved_reg
*saved_regs
;
578 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
584 if ((op
& 0x7E1F) == 0x6C1F)
586 n
= (op
& 0x1E0) >> 5;
587 info
->sp_offset
-= 2;
588 info
->saved_regs
[n
].addr
= info
->sp_offset
;
593 else if ((op
& 0x7E3F) == 0x6E1F)
595 n
= (op
& 0x1E0) >> 5;
596 info
->sp_offset
-= 4;
597 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ 0;
598 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ 2;
603 if ((op
& 0x7FE1) == 0x01E1)
605 n
= (op
& 0x1E) >> 1;
608 info
->sp_offset
-= n
;
615 info
->uses_frame
= 1;
616 info
->r11_offset
= info
->sp_offset
;
621 if ((op
& 0x7E1F) == 0x6816)
623 n
= (op
& 0x1E0) >> 5;
624 info
->saved_regs
[n
].addr
= info
->r11_offset
;
633 if ((op
& 0x7E1F) == 0x681E)
635 n
= (op
& 0x1E0) >> 5;
636 info
->saved_regs
[n
].addr
= info
->sp_offset
;
641 if ((op
& 0x7E3F) == 0x3A1E)
643 n
= (op
& 0x1E0) >> 5;
644 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ 0;
645 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ 2;
652 /* Put here the code to store, into fi->saved_regs, the addresses of
653 the saved registers of frame described by FRAME_INFO. This
654 includes special registers such as pc and fp saved in special ways
655 in the stack frame. sp is even more special: the address we return
656 for it IS the sp for the next frame. */
658 static struct d10v_unwind_cache
*
659 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
660 void **this_prologue_cache
)
662 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
667 unsigned short op1
, op2
;
669 struct d10v_unwind_cache
*info
;
671 if ((*this_prologue_cache
))
672 return (*this_prologue_cache
);
674 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
675 (*this_prologue_cache
) = info
;
676 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
681 info
->uses_frame
= 0;
682 for (pc
= frame_func_unwind (next_frame
);
683 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
686 op
= get_frame_memory_unsigned (next_frame
, pc
, 4);
687 if ((op
& 0xC0000000) == 0xC0000000)
689 /* long instruction */
690 if ((op
& 0x3FFF0000) == 0x01FF0000)
693 short n
= op
& 0xFFFF;
694 info
->sp_offset
+= n
;
696 else if ((op
& 0x3F0F0000) == 0x340F0000)
698 /* st rn, @(offset,sp) */
699 short offset
= op
& 0xFFFF;
700 short n
= (op
>> 20) & 0xF;
701 info
->saved_regs
[n
].addr
= info
->sp_offset
+ offset
;
703 else if ((op
& 0x3F1F0000) == 0x350F0000)
705 /* st2w rn, @(offset,sp) */
706 short offset
= op
& 0xFFFF;
707 short n
= (op
>> 20) & 0xF;
708 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ offset
+ 0;
709 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ offset
+ 2;
716 /* short instructions */
717 if ((op
& 0xC0000000) == 0x80000000)
719 op2
= (op
& 0x3FFF8000) >> 15;
724 op1
= (op
& 0x3FFF8000) >> 15;
727 if (!prologue_find_regs (info
, op1
, pc
)
728 || !prologue_find_regs (info
, op2
, pc
))
733 info
->size
= -info
->sp_offset
;
735 /* Compute the previous frame's stack pointer (which is also the
736 frame's ID's stack address), and this frame's base pointer. */
737 if (info
->uses_frame
)
739 /* The SP was moved to the FP. This indicates that a new frame
740 was created. Get THIS frame's FP value by unwinding it from
742 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
743 /* The FP points at the last saved register. Adjust the FP back
744 to before the first saved register giving the SP. */
745 prev_sp
= this_base
+ info
->size
;
749 /* Assume that the FP is this frame's SP but with that pushed
750 stack space added back. */
751 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
752 prev_sp
= this_base
+ info
->size
;
755 /* Convert that SP/BASE into real addresses. */
756 info
->prev_sp
= d10v_make_daddr (prev_sp
);
757 info
->base
= d10v_make_daddr (this_base
);
759 /* Adjust all the saved registers so that they contain addresses and
761 for (i
= 0; i
< NUM_REGS
- 1; i
++)
762 if (trad_frame_addr_p (info
->saved_regs
, i
))
764 info
->saved_regs
[i
].addr
= (info
->prev_sp
+ info
->saved_regs
[i
].addr
);
767 /* The call instruction moves the caller's PC in the callee's LR.
768 Since this is an unwind, do the reverse. Copy the location of LR
769 into PC (the address / regnum) so that a request for PC will be
770 converted into a request for the LR. */
771 info
->saved_regs
[D10V_PC_REGNUM
] = info
->saved_regs
[LR_REGNUM
];
773 /* The previous frame's SP needed to be computed. Save the computed
775 trad_frame_set_value (info
->saved_regs
, D10V_SP_REGNUM
,
776 d10v_make_daddr (prev_sp
));
782 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
783 struct frame_info
*frame
, int regnum
, int all
)
785 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
788 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
793 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
794 pc
= get_frame_register_unsigned (frame
, D10V_PC_REGNUM
);
795 psw
= get_frame_register_unsigned (frame
, PSW_REGNUM
);
796 rpt_s
= get_frame_register_unsigned (frame
, frame_map_name_to_regnum (frame
, "rpt_s", -1));
797 rpt_e
= get_frame_register_unsigned (frame
, frame_map_name_to_regnum (frame
, "rpt_e", -1));
798 rpt_c
= get_frame_register_unsigned (frame
, frame_map_name_to_regnum (frame
, "rpt_c", -1));
799 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
800 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
801 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
806 for (group
= 0; group
< 16; group
+= 8)
809 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
810 for (r
= group
; r
< group
+ 8; r
++)
813 tmp
= get_frame_register_unsigned (frame
, r
);
814 fprintf_filtered (file
, " %04lx", (long) tmp
);
816 fprintf_filtered (file
, "\n");
820 /* Note: The IMAP/DMAP registers don't participate in function
821 calls. Don't bother trying to unwind them. */
825 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
828 fprintf_filtered (file
, " ");
829 fprintf_filtered (file
, "IMAP%d %04lx", a
,
830 tdep
->imap_register (current_regcache
, a
));
832 if (nr_dmap_regs (gdbarch
) == 1)
833 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
834 fprintf_filtered (file
, " DMAP %04lx\n",
835 tdep
->dmap_register (current_regcache
, 2));
838 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
840 fprintf_filtered (file
, " DMAP%d %04lx", a
,
841 tdep
->dmap_register (current_regcache
, a
));
843 fprintf_filtered (file
, "\n");
848 char num
[MAX_REGISTER_SIZE
];
850 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
851 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
854 fprintf_filtered (file
, " ");
855 get_frame_register (frame
, a
, num
);
856 for (i
= 0; i
< register_size (gdbarch
, a
); i
++)
858 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
862 fprintf_filtered (file
, "\n");
866 show_regs (char *args
, int from_tty
)
868 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
869 get_current_frame (), -1, 1);
873 d10v_read_pc (ptid_t ptid
)
879 save_ptid
= inferior_ptid
;
880 inferior_ptid
= ptid
;
881 pc
= (int) read_register (D10V_PC_REGNUM
);
882 inferior_ptid
= save_ptid
;
883 retval
= d10v_make_iaddr (pc
);
888 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
892 save_ptid
= inferior_ptid
;
893 inferior_ptid
= ptid
;
894 write_register (D10V_PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
895 inferior_ptid
= save_ptid
;
899 d10v_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
902 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &sp
);
903 return d10v_make_daddr (sp
);
906 /* When arguments must be pushed onto the stack, they go on in reverse
907 order. The below implements a FILO (stack) to do this. */
912 struct stack_item
*prev
;
916 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
917 void *contents
, int len
);
918 static struct stack_item
*
919 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
921 struct stack_item
*si
;
922 si
= xmalloc (sizeof (struct stack_item
));
923 si
->data
= xmalloc (len
);
926 memcpy (si
->data
, contents
, len
);
930 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
931 static struct stack_item
*
932 pop_stack_item (struct stack_item
*si
)
934 struct stack_item
*dead
= si
;
943 d10v_push_dummy_code (struct gdbarch
*gdbarch
,
944 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
945 struct value
**args
, int nargs
,
946 struct type
*value_type
,
947 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
949 /* Allocate space sufficient for a breakpoint. */
951 /* Store the address of that breakpoint taking care to first convert
952 it into a code (IADDR) address from a stack (DADDR) address.
953 This of course assumes that the two virtual addresses map onto
954 the same real address. */
955 (*bp_addr
) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp
));
956 /* d10v always starts the call at the callee's entry point. */
957 (*real_pc
) = funaddr
;
962 d10v_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
963 struct regcache
*regcache
, CORE_ADDR bp_addr
,
964 int nargs
, struct value
**args
, CORE_ADDR sp
,
965 int struct_return
, CORE_ADDR struct_addr
)
968 int regnum
= ARG1_REGNUM
;
969 struct stack_item
*si
= NULL
;
972 /* Set the return address. For the d10v, the return breakpoint is
973 always at BP_ADDR. */
974 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
975 d10v_convert_iaddr_to_raw (bp_addr
));
977 /* If STRUCT_RETURN is true, then the struct return address (in
978 STRUCT_ADDR) will consume the first argument-passing register.
979 Both adjust the register count and store that value. */
982 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
986 /* Fill in registers and arg lists */
987 for (i
= 0; i
< nargs
; i
++)
989 struct value
*arg
= args
[i
];
990 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
991 char *contents
= VALUE_CONTENTS (arg
);
992 int len
= TYPE_LENGTH (type
);
993 int aligned_regnum
= (regnum
+ 1) & ~1;
995 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
996 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
997 /* fits in a single register, do not align */
999 val
= extract_unsigned_integer (contents
, len
);
1000 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1002 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1003 /* value fits in remaining registers, store keeping left
1007 regnum
= aligned_regnum
;
1008 for (b
= 0; b
< (len
& ~1); b
+= 2)
1010 val
= extract_unsigned_integer (&contents
[b
], 2);
1011 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1015 val
= extract_unsigned_integer (&contents
[b
], 1);
1016 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1021 /* arg will go onto stack */
1022 regnum
= ARGN_REGNUM
+ 1;
1023 si
= push_stack_item (si
, contents
, len
);
1029 sp
= (sp
- si
->len
) & ~1;
1030 write_memory (sp
, si
->data
, si
->len
);
1031 si
= pop_stack_item (si
);
1034 /* Finally, update the SP register. */
1035 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1036 d10v_convert_daddr_to_raw (sp
));
1041 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1042 understands. Returns number of bytes that can be transfered
1043 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1044 (segmentation fault). Since the simulator knows all about how the
1045 VM system works, we just call that to do the translation. */
1048 remote_d10v_translate_xfer_address (struct gdbarch
*gdbarch
,
1049 struct regcache
*regcache
,
1050 CORE_ADDR memaddr
, int nr_bytes
,
1051 CORE_ADDR
*targ_addr
, int *targ_len
)
1053 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1056 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
, &out_addr
, regcache
,
1057 tdep
->dmap_register
, tdep
->imap_register
);
1058 *targ_addr
= out_addr
;
1059 *targ_len
= out_len
;
1063 /* The following code implements access to, and display of, the D10V's
1064 instruction trace buffer. The buffer consists of 64K or more
1065 4-byte words of data, of which each words includes an 8-bit count,
1066 an 8-bit segment number, and a 16-bit instruction address.
1068 In theory, the trace buffer is continuously capturing instruction
1069 data that the CPU presents on its "debug bus", but in practice, the
1070 ROMified GDB stub only enables tracing when it continues or steps
1071 the program, and stops tracing when the program stops; so it
1072 actually works for GDB to read the buffer counter out of memory and
1073 then read each trace word. The counter records where the tracing
1074 stops, but there is no record of where it started, so we remember
1075 the PC when we resumed and then search backwards in the trace
1076 buffer for a word that includes that address. This is not perfect,
1077 because you will miss trace data if the resumption PC is the target
1078 of a branch. (The value of the buffer counter is semi-random, any
1079 trace data from a previous program stop is gone.) */
1081 /* The address of the last word recorded in the trace buffer. */
1083 #define DBBC_ADDR (0xd80000)
1085 /* The base of the trace buffer, at least for the "Board_0". */
1087 #define TRACE_BUFFER_BASE (0xf40000)
1089 static void trace_command (char *, int);
1091 static void untrace_command (char *, int);
1093 static void trace_info (char *, int);
1095 static void tdisassemble_command (char *, int);
1097 static void display_trace (int, int);
1099 /* True when instruction traces are being collected. */
1103 /* Remembered PC. */
1105 static CORE_ADDR last_pc
;
1107 /* True when trace output should be displayed whenever program stops. */
1109 static int trace_display
;
1111 /* True when trace listing should include source lines. */
1113 static int default_trace_show_source
= 1;
1124 trace_command (char *args
, int from_tty
)
1126 /* Clear the host-side trace buffer, allocating space if needed. */
1127 trace_data
.size
= 0;
1128 if (trace_data
.counts
== NULL
)
1129 trace_data
.counts
= XCALLOC (65536, short);
1130 if (trace_data
.addrs
== NULL
)
1131 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1135 printf_filtered ("Tracing is now on.\n");
1139 untrace_command (char *args
, int from_tty
)
1143 printf_filtered ("Tracing is now off.\n");
1147 trace_info (char *args
, int from_tty
)
1151 if (trace_data
.size
)
1153 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1155 for (i
= 0; i
< trace_data
.size
; ++i
)
1157 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1159 trace_data
.counts
[i
],
1160 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1161 paddr_nz (trace_data
.addrs
[i
]));
1165 printf_filtered ("No entries in trace buffer.\n");
1167 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1171 d10v_eva_prepare_to_trace (void)
1176 last_pc
= read_register (D10V_PC_REGNUM
);
1179 /* Collect trace data from the target board and format it into a form
1180 more useful for display. */
1183 d10v_eva_get_trace_data (void)
1185 int count
, i
, j
, oldsize
;
1186 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1187 unsigned int last_trace
, trace_word
, next_word
;
1188 unsigned int *tmpspace
;
1193 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1195 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1197 /* Collect buffer contents from the target, stopping when we reach
1198 the word recorded when execution resumed. */
1201 while (last_trace
> 0)
1205 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1206 trace_addr
= trace_word
& 0xffff;
1208 /* Ignore an apparently nonsensical entry. */
1209 if (trace_addr
== 0xffd5)
1211 tmpspace
[count
++] = trace_word
;
1212 if (trace_addr
== last_pc
)
1218 /* Move the data to the host-side trace buffer, adjusting counts to
1219 include the last instruction executed and transforming the address
1220 into something that GDB likes. */
1222 for (i
= 0; i
< count
; ++i
)
1224 trace_word
= tmpspace
[i
];
1225 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1226 trace_addr
= trace_word
& 0xffff;
1227 next_cnt
= (next_word
>> 24) & 0xff;
1228 j
= trace_data
.size
+ count
- i
- 1;
1229 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1230 trace_data
.counts
[j
] = next_cnt
+ 1;
1233 oldsize
= trace_data
.size
;
1234 trace_data
.size
+= count
;
1239 display_trace (oldsize
, trace_data
.size
);
1243 tdisassemble_command (char *arg
, int from_tty
)
1246 CORE_ADDR low
, high
;
1251 high
= trace_data
.size
;
1255 char *space_index
= strchr (arg
, ' ');
1256 if (space_index
== NULL
)
1258 low
= parse_and_eval_address (arg
);
1263 /* Two arguments. */
1264 *space_index
= '\0';
1265 low
= parse_and_eval_address (arg
);
1266 high
= parse_and_eval_address (space_index
+ 1);
1272 printf_filtered ("Dump of trace from %s to %s:\n",
1273 paddr_u (low
), paddr_u (high
));
1275 display_trace (low
, high
);
1277 printf_filtered ("End of trace dump.\n");
1278 gdb_flush (gdb_stdout
);
1282 display_trace (int low
, int high
)
1284 int i
, count
, trace_show_source
, first
, suppress
;
1285 CORE_ADDR next_address
;
1287 trace_show_source
= default_trace_show_source
;
1288 if (!have_full_symbols () && !have_partial_symbols ())
1290 trace_show_source
= 0;
1291 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1292 printf_filtered ("Trace will not display any source.\n");
1297 for (i
= low
; i
< high
; ++i
)
1299 next_address
= trace_data
.addrs
[i
];
1300 count
= trace_data
.counts
[i
];
1304 if (trace_show_source
)
1306 struct symtab_and_line sal
, sal_prev
;
1308 sal_prev
= find_pc_line (next_address
- 4, 0);
1309 sal
= find_pc_line (next_address
, 0);
1313 if (first
|| sal
.line
!= sal_prev
.line
)
1314 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1320 /* FIXME-32x64--assumes sal.pc fits in long. */
1321 printf_filtered ("No source file for address %s.\n",
1322 local_hex_string ((unsigned long) sal
.pc
));
1327 print_address (next_address
, gdb_stdout
);
1328 printf_filtered (":");
1329 printf_filtered ("\t");
1331 next_address
+= gdb_print_insn (next_address
, gdb_stdout
);
1332 printf_filtered ("\n");
1333 gdb_flush (gdb_stdout
);
1339 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1342 frame_unwind_unsigned_register (next_frame
, D10V_PC_REGNUM
, &pc
);
1343 return d10v_make_iaddr (pc
);
1346 /* Given a GDB frame, determine the address of the calling function's
1347 frame. This will be used to create a new GDB frame struct. */
1350 d10v_frame_this_id (struct frame_info
*next_frame
,
1351 void **this_prologue_cache
,
1352 struct frame_id
*this_id
)
1354 struct d10v_unwind_cache
*info
1355 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1360 /* The FUNC is easy. */
1361 func
= frame_func_unwind (next_frame
);
1363 /* Hopefully the prologue analysis either correctly determined the
1364 frame's base (which is the SP from the previous frame), or set
1365 that base to "NULL". */
1366 base
= info
->prev_sp
;
1367 if (base
== STACK_START
|| base
== 0)
1370 id
= frame_id_build (base
, func
);
1376 d10v_frame_prev_register (struct frame_info
*next_frame
,
1377 void **this_prologue_cache
,
1378 int regnum
, int *optimizedp
,
1379 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1380 int *realnump
, void *bufferp
)
1382 struct d10v_unwind_cache
*info
1383 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1384 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1385 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
1388 static const struct frame_unwind d10v_frame_unwind
= {
1391 d10v_frame_prev_register
1394 static const struct frame_unwind
*
1395 d10v_frame_sniffer (struct frame_info
*next_frame
)
1397 return &d10v_frame_unwind
;
1401 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1403 struct d10v_unwind_cache
*info
1404 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1408 static const struct frame_base d10v_frame_base
= {
1410 d10v_frame_base_address
,
1411 d10v_frame_base_address
,
1412 d10v_frame_base_address
1415 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1416 dummy frame. The frame ID's base needs to match the TOS value
1417 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1420 static struct frame_id
1421 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1423 return frame_id_build (d10v_unwind_sp (gdbarch
, next_frame
),
1424 frame_pc_unwind (next_frame
));
1427 static gdbarch_init_ftype d10v_gdbarch_init
;
1429 static struct gdbarch
*
1430 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1432 struct gdbarch
*gdbarch
;
1434 struct gdbarch_tdep
*tdep
;
1435 gdbarch_register_name_ftype
*d10v_register_name
;
1436 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1438 /* Find a candidate among the list of pre-declared architectures. */
1439 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1441 return arches
->gdbarch
;
1443 /* None found, create a new architecture from the information
1445 tdep
= XMALLOC (struct gdbarch_tdep
);
1446 gdbarch
= gdbarch_alloc (&info
, tdep
);
1448 switch (info
.bfd_arch_info
->mach
)
1450 case bfd_mach_d10v_ts2
:
1452 d10v_register_name
= d10v_ts2_register_name
;
1453 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1454 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1455 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1456 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1457 tdep
->imap_register
= d10v_ts2_imap_register
;
1460 case bfd_mach_d10v_ts3
:
1462 d10v_register_name
= d10v_ts3_register_name
;
1463 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1464 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1465 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1466 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1467 tdep
->imap_register
= d10v_ts3_imap_register
;
1471 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1472 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1473 set_gdbarch_unwind_sp (gdbarch
, d10v_unwind_sp
);
1475 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1476 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1477 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1478 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1480 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1481 set_gdbarch_addr_bit (gdbarch
, 32);
1482 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1483 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1484 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1485 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1486 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1487 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1488 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1489 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1490 double'' is 64 bits. */
1491 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1492 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1493 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1494 switch (info
.byte_order
)
1496 case BFD_ENDIAN_BIG
:
1497 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1498 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1499 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1501 case BFD_ENDIAN_LITTLE
:
1502 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1503 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1504 set_gdbarch_long_double_format (gdbarch
,
1505 &floatformat_ieee_double_little
);
1508 internal_error (__FILE__
, __LINE__
,
1509 "d10v_gdbarch_init: bad byte order for float format");
1512 set_gdbarch_return_value (gdbarch
, d10v_return_value
);
1513 set_gdbarch_push_dummy_code (gdbarch
, d10v_push_dummy_code
);
1514 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1516 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1517 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1518 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1519 set_gdbarch_function_start_offset (gdbarch
, 0);
1520 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1522 set_gdbarch_remote_translate_xfer_address (gdbarch
,
1523 remote_d10v_translate_xfer_address
);
1525 set_gdbarch_frame_args_skip (gdbarch
, 0);
1526 set_gdbarch_frameless_function_invocation (gdbarch
,
1527 frameless_look_for_prologue
);
1529 set_gdbarch_frame_align (gdbarch
, d10v_frame_align
);
1531 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1533 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1535 frame_unwind_append_sniffer (gdbarch
, d10v_frame_sniffer
);
1536 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1538 /* Methods for saving / extracting a dummy frame's ID. The ID's
1539 stack address must match the SP value returned by
1540 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
1541 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1543 /* Return the unwound PC value. */
1544 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1546 set_gdbarch_print_insn (gdbarch
, print_insn_d10v
);
1552 _initialize_d10v_tdep (void)
1554 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1556 target_resume_hook
= d10v_eva_prepare_to_trace
;
1557 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1559 deprecate_cmd (add_com ("regs", class_vars
, show_regs
,
1560 "Print all registers"),
1563 add_com ("itrace", class_support
, trace_command
,
1564 "Enable tracing of instruction execution.");
1566 add_com ("iuntrace", class_support
, untrace_command
,
1567 "Disable tracing of instruction execution.");
1569 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1570 "Disassemble the trace buffer.\n\
1571 Two optional arguments specify a range of trace buffer entries\n\
1572 as reported by info trace (NOT addresses!).");
1574 add_info ("itrace", trace_info
,
1575 "Display info about the trace data buffer.");
1577 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1578 "Set automatic display of trace.\n",
1579 "Show automatic display of trace.\n",
1580 NULL
, NULL
, &setlist
, &showlist
);
1581 add_setshow_boolean_cmd ("itracesource", no_class
,
1582 &default_trace_show_source
,
1583 "Set display of source code with trace.\n",
1584 "Show display of source code with trace.\n",
1585 NULL
, NULL
, &setlist
, &showlist
);