gdb/d10v-tdep.c

   1 /* Target-dependent code for Mitsubishi D10V, for GDB.
   2
   3    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software
   4    Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 /*  Contributed by Martin Hunt, hunt@cygnus.com */
  24
  25 #include "defs.h"
  26 #include "frame.h"
  27 #include "obstack.h"
  28 #include "symtab.h"
  29 #include "gdbtypes.h"
  30 #include "gdbcmd.h"
  31 #include "gdbcore.h"
  32 #include "gdb_string.h"
  33 #include "value.h"
  34 #include "inferior.h"
  35 #include "dis-asm.h"
  36 #include "symfile.h"
  37 #include "objfiles.h"
  38 #include "language.h"
  39 #include "arch-utils.h"
  40 #include "regcache.h"
  41
  42 #include "floatformat.h"
  43 #include "gdb/sim-d10v.h"
  44 #include "sim-regno.h"
  45
  46 struct frame_extra_info
  47   {
  48     CORE_ADDR return_pc;
  49     int frameless;
  50     int size;
  51   };
  52
  53 struct gdbarch_tdep
  54   {
  55     int a0_regnum;
  56     int nr_dmap_regs;
  57     unsigned long (*dmap_register) (int nr);
  58     unsigned long (*imap_register) (int nr);
  59   };
  60
  61 /* These are the addresses the D10V-EVA board maps data and
  62    instruction memory to. */
  63
  64 enum memspace {
  65   DMEM_START  = 0x2000000,
  66   IMEM_START  = 0x1000000,
  67   STACK_START = 0x200bffe
  68 };
  69
  70 /* d10v register names. */
  71
  72 enum
  73   {
  74     R0_REGNUM = 0,
  75     R3_REGNUM = 3,
  76     _FP_REGNUM = 11,
  77     LR_REGNUM = 13,
  78     _SP_REGNUM = 15,
  79     PSW_REGNUM = 16,
  80     _PC_REGNUM = 18,
  81     NR_IMAP_REGS = 2,
  82     NR_A_REGS = 2,
  83     TS2_NUM_REGS = 37,
  84     TS3_NUM_REGS = 42,
  85     /* d10v calling convention. */
  86     ARG1_REGNUM = R0_REGNUM,
  87     ARGN_REGNUM = R3_REGNUM,
  88     RET1_REGNUM = R0_REGNUM,
  89   };
  90
  91 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
  92 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
  93
  94 /* Local functions */
  95
  96 extern void _initialize_d10v_tdep (void);
  97
  98 static void d10v_eva_prepare_to_trace (void);
  99
 100 static void d10v_eva_get_trace_data (void);
 101
 102 static int prologue_find_regs (unsigned short op, struct frame_info *fi,
 103                                CORE_ADDR addr);
 104
 105 static void d10v_frame_init_saved_regs (struct frame_info *);
 106
 107 static void do_d10v_pop_frame (struct frame_info *fi);
 108
 109 static int
 110 d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame)
 111 {
 112   if (chain != 0 && frame != NULL)
 113     {
 114       if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 115         return 1;       /* Path back from a call dummy must be valid. */
 116       return ((frame)->pc > IMEM_START
 117               && !inside_main_func (frame->pc));
 118     }
 119   else return 0;
 120 }
 121
 122 static CORE_ADDR
 123 d10v_stack_align (CORE_ADDR len)
 124 {
 125   return (len + 1) & ~1;
 126 }
 127
 128 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
 129    EXTRACT_RETURN_VALUE?  GCC_P is true if compiled with gcc
 130    and TYPE is the type (which is known to be struct, union or array).
 131
 132    The d10v returns anything less than 8 bytes in size in
 133    registers. */
 134
 135 static int
 136 d10v_use_struct_convention (int gcc_p, struct type *type)
 137 {
 138   long alignment;
 139   int i;
 140   /* The d10v only passes a struct in a register when that structure
 141      has an alignment that matches the size of a register. */
 142   /* If the structure doesn't fit in 4 registers, put it on the
 143      stack. */
 144   if (TYPE_LENGTH (type) > 8)
 145     return 1;
 146   /* If the struct contains only one field, don't put it on the stack
 147      - gcc can fit it in one or more registers. */
 148   if (TYPE_NFIELDS (type) == 1)
 149     return 0;
 150   alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0));
 151   for (i = 1; i < TYPE_NFIELDS (type); i++)
 152     {
 153       /* If the alignment changes, just assume it goes on the
 154          stack. */
 155       if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment)
 156         return 1;
 157     }
 158   /* If the alignment is suitable for the d10v's 16 bit registers,
 159      don't put it on the stack. */
 160   if (alignment == 2 || alignment == 4)
 161     return 0;
 162   return 1;
 163 }
 164
 165
 166 static const unsigned char *
 167 d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 168 {
 169   static unsigned char breakpoint[] =
 170   {0x2f, 0x90, 0x5e, 0x00};
 171   *lenptr = sizeof (breakpoint);
 172   return breakpoint;
 173 }
 174
 175 /* Map the REG_NR onto an ascii name.  Return NULL or an empty string
 176    when the reg_nr isn't valid. */
 177
 178 enum ts2_regnums
 179   {
 180     TS2_IMAP0_REGNUM = 32,
 181     TS2_DMAP_REGNUM = 34,
 182     TS2_NR_DMAP_REGS = 1,
 183     TS2_A0_REGNUM = 35
 184   };
 185
 186 static char *
 187 d10v_ts2_register_name (int reg_nr)
 188 {
 189   static char *register_names[] =
 190   {
 191     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 192     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 193     "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
 194     "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
 195     "imap0", "imap1", "dmap", "a0", "a1"
 196   };
 197   if (reg_nr < 0)
 198     return NULL;
 199   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 200     return NULL;
 201   return register_names[reg_nr];
 202 }
 203
 204 enum ts3_regnums
 205   {
 206     TS3_IMAP0_REGNUM = 36,
 207     TS3_DMAP0_REGNUM = 38,
 208     TS3_NR_DMAP_REGS = 4,
 209     TS3_A0_REGNUM = 32
 210   };
 211
 212 static char *
 213 d10v_ts3_register_name (int reg_nr)
 214 {
 215   static char *register_names[] =
 216   {
 217     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 218     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 219     "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
 220     "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
 221     "a0", "a1",
 222     "spi", "spu",
 223     "imap0", "imap1",
 224     "dmap0", "dmap1", "dmap2", "dmap3"
 225   };
 226   if (reg_nr < 0)
 227     return NULL;
 228   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 229     return NULL;
 230   return register_names[reg_nr];
 231 }
 232
 233 /* Access the DMAP/IMAP registers in a target independent way.
 234
 235    Divide the D10V's 64k data space into four 16k segments:
 236    0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
 237    0xc000 -- 0xffff.
 238
 239    On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
 240    0x7fff) always map to the on-chip data RAM, and the fourth always
 241    maps to I/O space.  The third (0x8000 - 0xbfff) can be mapped into
 242    unified memory or instruction memory, under the control of the
 243    single DMAP register.
 244
 245    On the TS3, there are four DMAP registers, each of which controls
 246    one of the segments.  */
 247
 248 static unsigned long
 249 d10v_ts2_dmap_register (int reg_nr)
 250 {
 251   switch (reg_nr)
 252     {
 253     case 0:
 254     case 1:
 255       return 0x2000;
 256     case 2:
 257       return read_register (TS2_DMAP_REGNUM);
 258     default:
 259       return 0;
 260     }
 261 }
 262
 263 static unsigned long
 264 d10v_ts3_dmap_register (int reg_nr)
 265 {
 266   return read_register (TS3_DMAP0_REGNUM + reg_nr);
 267 }
 268
 269 static unsigned long
 270 d10v_dmap_register (int reg_nr)
 271 {
 272   return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
 273 }
 274
 275 static unsigned long
 276 d10v_ts2_imap_register (int reg_nr)
 277 {
 278   return read_register (TS2_IMAP0_REGNUM + reg_nr);
 279 }
 280
 281 static unsigned long
 282 d10v_ts3_imap_register (int reg_nr)
 283 {
 284   return read_register (TS3_IMAP0_REGNUM + reg_nr);
 285 }
 286
 287 static unsigned long
 288 d10v_imap_register (int reg_nr)
 289 {
 290   return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
 291 }
 292
 293 /* MAP GDB's internal register numbering (determined by the layout fo
 294    the REGISTER_BYTE array) onto the simulator's register
 295    numbering. */
 296
 297 static int
 298 d10v_ts2_register_sim_regno (int nr)
 299 {
 300   if (legacy_register_sim_regno (nr) < 0)
 301     return legacy_register_sim_regno (nr);
 302   if (nr >= TS2_IMAP0_REGNUM
 303       && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
 304     return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
 305   if (nr == TS2_DMAP_REGNUM)
 306     return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
 307   if (nr >= TS2_A0_REGNUM
 308       && nr < TS2_A0_REGNUM + NR_A_REGS)
 309     return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
 310   return nr;
 311 }
 312
 313 static int
 314 d10v_ts3_register_sim_regno (int nr)
 315 {
 316   if (legacy_register_sim_regno (nr) < 0)
 317     return legacy_register_sim_regno (nr);
 318   if (nr >= TS3_IMAP0_REGNUM
 319       && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
 320     return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
 321   if (nr >= TS3_DMAP0_REGNUM
 322       && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
 323     return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
 324   if (nr >= TS3_A0_REGNUM
 325       && nr < TS3_A0_REGNUM + NR_A_REGS)
 326     return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
 327   return nr;
 328 }
 329
 330 /* Index within `registers' of the first byte of the space for
 331    register REG_NR.  */
 332
 333 static int
 334 d10v_register_byte (int reg_nr)
 335 {
 336   if (reg_nr < A0_REGNUM)
 337     return (reg_nr * 2);
 338   else if (reg_nr < (A0_REGNUM + NR_A_REGS))
 339     return (A0_REGNUM * 2
 340             + (reg_nr - A0_REGNUM) * 8);
 341   else
 342     return (A0_REGNUM * 2
 343             + NR_A_REGS * 8
 344             + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
 345 }
 346
 347 /* Number of bytes of storage in the actual machine representation for
 348    register REG_NR.  */
 349
 350 static int
 351 d10v_register_raw_size (int reg_nr)
 352 {
 353   if (reg_nr < A0_REGNUM)
 354     return 2;
 355   else if (reg_nr < (A0_REGNUM + NR_A_REGS))
 356     return 8;
 357   else
 358     return 2;
 359 }
 360
 361 /* Return the GDB type object for the "standard" data type
 362    of data in register N.  */
 363
 364 static struct type *
 365 d10v_register_virtual_type (int reg_nr)
 366 {
 367   if (reg_nr == PC_REGNUM)
 368     return builtin_type_void_func_ptr;
 369   else if (reg_nr >= A0_REGNUM
 370       && reg_nr < (A0_REGNUM + NR_A_REGS))
 371     return builtin_type_int64;
 372   else
 373     return builtin_type_int16;
 374 }
 375
 376 static int
 377 d10v_daddr_p (CORE_ADDR x)
 378 {
 379   return (((x) & 0x3000000) == DMEM_START);
 380 }
 381
 382 static int
 383 d10v_iaddr_p (CORE_ADDR x)
 384 {
 385   return (((x) & 0x3000000) == IMEM_START);
 386 }
 387
 388 static CORE_ADDR
 389 d10v_make_daddr (CORE_ADDR x)
 390 {
 391   return ((x) | DMEM_START);
 392 }
 393
 394 static CORE_ADDR
 395 d10v_make_iaddr (CORE_ADDR x)
 396 {
 397   if (d10v_iaddr_p (x))
 398     return x;   /* Idempotency -- x is already in the IMEM space. */
 399   else
 400     return (((x) << 2) | IMEM_START);
 401 }
 402
 403 static CORE_ADDR
 404 d10v_convert_iaddr_to_raw (CORE_ADDR x)
 405 {
 406   return (((x) >> 2) & 0xffff);
 407 }
 408
 409 static CORE_ADDR
 410 d10v_convert_daddr_to_raw (CORE_ADDR x)
 411 {
 412   return ((x) & 0xffff);
 413 }
 414
 415 static void
 416 d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr)
 417 {
 418   /* Is it a code address?  */
 419   if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
 420       || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD)
 421     {
 422       store_unsigned_integer (buf, TYPE_LENGTH (type),
 423                               d10v_convert_iaddr_to_raw (addr));
 424     }
 425   else
 426     {
 427       /* Strip off any upper segment bits.  */
 428       store_unsigned_integer (buf, TYPE_LENGTH (type),
 429                               d10v_convert_daddr_to_raw (addr));
 430     }
 431 }
 432
 433 static CORE_ADDR
 434 d10v_pointer_to_address (struct type *type, void *buf)
 435 {
 436   CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type));
 437
 438   /* Is it a code address?  */
 439   if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
 440       || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
 441       || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type)))
 442     return d10v_make_iaddr (addr);
 443   else
 444     return d10v_make_daddr (addr);
 445 }
 446
 447 static CORE_ADDR
 448 d10v_integer_to_address (struct type *type, void *buf)
 449 {
 450   LONGEST val;
 451   val = unpack_long (type, buf);
 452   if (TYPE_CODE (type) == TYPE_CODE_INT
 453       && TYPE_LENGTH (type) <= TYPE_LENGTH (builtin_type_void_data_ptr))
 454     /* Convert small integers that would would be directly copied into
 455        a pointer variable into an address pointing into data space.  */
 456     return d10v_make_daddr (val & 0xffff);
 457   else
 458     /* The value is too large to fit in a pointer.  Assume this was
 459        intentional and that the user in fact specified a raw address.  */
 460     return val;
 461 }
 462
 463 /* Store the address of the place in which to copy the structure the
 464    subroutine will return.  This is called from call_function.
 465
 466    We store structs through a pointer passed in the first Argument
 467    register. */
 468
 469 static void
 470 d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
 471 {
 472   write_register (ARG1_REGNUM, (addr));
 473 }
 474
 475 /* Write into appropriate registers a function return value
 476    of type TYPE, given in virtual format.
 477
 478    Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
 479
 480 static void
 481 d10v_store_return_value (struct type *type, char *valbuf)
 482 {
 483   write_register_bytes (REGISTER_BYTE (RET1_REGNUM),
 484                         valbuf,
 485                         TYPE_LENGTH (type));
 486 }
 487
 488 /* Extract from an array REGBUF containing the (raw) register state
 489    the address in which a function should return its structure value,
 490    as a CORE_ADDR (or an expression that can be used as one).  */
 491
 492 static CORE_ADDR
 493 d10v_extract_struct_value_address (char *regbuf)
 494 {
 495   return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM),
 496                            REGISTER_RAW_SIZE (ARG1_REGNUM))
 497           | DMEM_START);
 498 }
 499
 500 static CORE_ADDR
 501 d10v_frame_saved_pc (struct frame_info *frame)
 502 {
 503   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 504     return d10v_make_iaddr (generic_read_register_dummy (frame->pc,
 505                                                          frame->frame,
 506                                                          PC_REGNUM));
 507   else
 508     return ((frame)->extra_info->return_pc);
 509 }
 510
 511 /* Immediately after a function call, return the saved pc.  We can't
 512    use frame->return_pc beause that is determined by reading R13 off
 513    the stack and that may not be written yet. */
 514
 515 static CORE_ADDR
 516 d10v_saved_pc_after_call (struct frame_info *frame)
 517 {
 518   return ((read_register (LR_REGNUM) << 2)
 519           | IMEM_START);
 520 }
 521
 522 /* Discard from the stack the innermost frame, restoring all saved
 523    registers.  */
 524
 525 static void
 526 d10v_pop_frame (void)
 527 {
 528   generic_pop_current_frame (do_d10v_pop_frame);
 529 }
 530
 531 static void
 532 do_d10v_pop_frame (struct frame_info *fi)
 533 {
 534   CORE_ADDR fp;
 535   int regnum;
 536   char raw_buffer[8];
 537
 538   fp = FRAME_FP (fi);
 539   /* fill out fsr with the address of where each */
 540   /* register was stored in the frame */
 541   d10v_frame_init_saved_regs (fi);
 542
 543   /* now update the current registers with the old values */
 544   for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
 545     {
 546       if (fi->saved_regs[regnum])
 547         {
 548           read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
 549           write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
 550         }
 551     }
 552   for (regnum = 0; regnum < SP_REGNUM; regnum++)
 553     {
 554       if (fi->saved_regs[regnum])
 555         {
 556           write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
 557         }
 558     }
 559   if (fi->saved_regs[PSW_REGNUM])
 560     {
 561       write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
 562     }
 563
 564   write_register (PC_REGNUM, read_register (LR_REGNUM));
 565   write_register (SP_REGNUM, fp + fi->extra_info->size);
 566   target_store_registers (-1);
 567   flush_cached_frames ();
 568 }
 569
 570 static int
 571 check_prologue (unsigned short op)
 572 {
 573   /* st  rn, @-sp */
 574   if ((op & 0x7E1F) == 0x6C1F)
 575     return 1;
 576
 577   /* st2w  rn, @-sp */
 578   if ((op & 0x7E3F) == 0x6E1F)
 579     return 1;
 580
 581   /* subi  sp, n */
 582   if ((op & 0x7FE1) == 0x01E1)
 583     return 1;
 584
 585   /* mv  r11, sp */
 586   if (op == 0x417E)
 587     return 1;
 588
 589   /* nop */
 590   if (op == 0x5E00)
 591     return 1;
 592
 593   /* st  rn, @sp */
 594   if ((op & 0x7E1F) == 0x681E)
 595     return 1;
 596
 597   /* st2w  rn, @sp */
 598   if ((op & 0x7E3F) == 0x3A1E)
 599     return 1;
 600
 601   return 0;
 602 }
 603
 604 static CORE_ADDR
 605 d10v_skip_prologue (CORE_ADDR pc)
 606 {
 607   unsigned long op;
 608   unsigned short op1, op2;
 609   CORE_ADDR func_addr, func_end;
 610   struct symtab_and_line sal;
 611
 612   /* If we have line debugging information, then the end of the */
 613   /* prologue should the first assembly instruction of  the first source line */
 614   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 615     {
 616       sal = find_pc_line (func_addr, 0);
 617       if (sal.end && sal.end < func_end)
 618         return sal.end;
 619     }
 620
 621   if (target_read_memory (pc, (char *) &op, 4))
 622     return pc;                  /* Can't access it -- assume no prologue. */
 623
 624   while (1)
 625     {
 626       op = (unsigned long) read_memory_integer (pc, 4);
 627       if ((op & 0xC0000000) == 0xC0000000)
 628         {
 629           /* long instruction */
 630           if (((op & 0x3FFF0000) != 0x01FF0000) &&      /* add3 sp,sp,n */
 631               ((op & 0x3F0F0000) != 0x340F0000) &&      /* st  rn, @(offset,sp) */
 632               ((op & 0x3F1F0000) != 0x350F0000))        /* st2w  rn, @(offset,sp) */
 633             break;
 634         }
 635       else
 636         {
 637           /* short instructions */
 638           if ((op & 0xC0000000) == 0x80000000)
 639             {
 640               op2 = (op & 0x3FFF8000) >> 15;
 641               op1 = op & 0x7FFF;
 642             }
 643           else
 644             {
 645               op1 = (op & 0x3FFF8000) >> 15;
 646               op2 = op & 0x7FFF;
 647             }
 648           if (check_prologue (op1))
 649             {
 650               if (!check_prologue (op2))
 651                 {
 652                   /* if the previous opcode was really part of the prologue */
 653                   /* and not just a NOP, then we want to break after both instructions */
 654                   if (op1 != 0x5E00)
 655                     pc += 4;
 656                   break;
 657                 }
 658             }
 659           else
 660             break;
 661         }
 662       pc += 4;
 663     }
 664   return pc;
 665 }
 666
 667 /* Given a GDB frame, determine the address of the calling function's frame.
 668    This will be used to create a new GDB frame struct, and then
 669    INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
 670  */
 671
 672 static CORE_ADDR
 673 d10v_frame_chain (struct frame_info *fi)
 674 {
 675   CORE_ADDR addr;
 676
 677   /* A generic call dummy's frame is the same as caller's.  */
 678   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 679     return fi->frame;
 680
 681   d10v_frame_init_saved_regs (fi);
 682
 683
 684   if (fi->extra_info->return_pc == IMEM_START
 685       || inside_entry_file (fi->extra_info->return_pc))
 686     {
 687       /* This is meant to halt the backtrace at "_start".
 688          Make sure we don't halt it at a generic dummy frame. */
 689       if (!PC_IN_CALL_DUMMY (fi->extra_info->return_pc, 0, 0))
 690         return (CORE_ADDR) 0;
 691     }
 692
 693   if (!fi->saved_regs[FP_REGNUM])
 694     {
 695       if (!fi->saved_regs[SP_REGNUM]
 696           || fi->saved_regs[SP_REGNUM] == STACK_START)
 697         return (CORE_ADDR) 0;
 698
 699       return fi->saved_regs[SP_REGNUM];
 700     }
 701
 702   addr = read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
 703                                        REGISTER_RAW_SIZE (FP_REGNUM));
 704   if (addr == 0)
 705     return (CORE_ADDR) 0;
 706
 707   return d10v_make_daddr (addr);
 708 }
 709
 710 static int next_addr, uses_frame;
 711
 712 static int
 713 prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr)
 714 {
 715   int n;
 716
 717   /* st  rn, @-sp */
 718   if ((op & 0x7E1F) == 0x6C1F)
 719     {
 720       n = (op & 0x1E0) >> 5;
 721       next_addr -= 2;
 722       fi->saved_regs[n] = next_addr;
 723       return 1;
 724     }
 725
 726   /* st2w  rn, @-sp */
 727   else if ((op & 0x7E3F) == 0x6E1F)
 728     {
 729       n = (op & 0x1E0) >> 5;
 730       next_addr -= 4;
 731       fi->saved_regs[n] = next_addr;
 732       fi->saved_regs[n + 1] = next_addr + 2;
 733       return 1;
 734     }
 735
 736   /* subi  sp, n */
 737   if ((op & 0x7FE1) == 0x01E1)
 738     {
 739       n = (op & 0x1E) >> 1;
 740       if (n == 0)
 741         n = 16;
 742       next_addr -= n;
 743       return 1;
 744     }
 745
 746   /* mv  r11, sp */
 747   if (op == 0x417E)
 748     {
 749       uses_frame = 1;
 750       return 1;
 751     }
 752
 753   /* nop */
 754   if (op == 0x5E00)
 755     return 1;
 756
 757   /* st  rn, @sp */
 758   if ((op & 0x7E1F) == 0x681E)
 759     {
 760       n = (op & 0x1E0) >> 5;
 761       fi->saved_regs[n] = next_addr;
 762       return 1;
 763     }
 764
 765   /* st2w  rn, @sp */
 766   if ((op & 0x7E3F) == 0x3A1E)
 767     {
 768       n = (op & 0x1E0) >> 5;
 769       fi->saved_regs[n] = next_addr;
 770       fi->saved_regs[n + 1] = next_addr + 2;
 771       return 1;
 772     }
 773
 774   return 0;
 775 }
 776
 777 /* Put here the code to store, into fi->saved_regs, the addresses of
 778    the saved registers of frame described by FRAME_INFO.  This
 779    includes special registers such as pc and fp saved in special ways
 780    in the stack frame.  sp is even more special: the address we return
 781    for it IS the sp for the next frame. */
 782
 783 static void
 784 d10v_frame_init_saved_regs (struct frame_info *fi)
 785 {
 786   CORE_ADDR fp, pc;
 787   unsigned long op;
 788   unsigned short op1, op2;
 789   int i;
 790
 791   fp = fi->frame;
 792   memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
 793   next_addr = 0;
 794
 795   pc = get_pc_function_start (fi->pc);
 796
 797   uses_frame = 0;
 798   while (1)
 799     {
 800       op = (unsigned long) read_memory_integer (pc, 4);
 801       if ((op & 0xC0000000) == 0xC0000000)
 802         {
 803           /* long instruction */
 804           if ((op & 0x3FFF0000) == 0x01FF0000)
 805             {
 806               /* add3 sp,sp,n */
 807               short n = op & 0xFFFF;
 808               next_addr += n;
 809             }
 810           else if ((op & 0x3F0F0000) == 0x340F0000)
 811             {
 812               /* st  rn, @(offset,sp) */
 813               short offset = op & 0xFFFF;
 814               short n = (op >> 20) & 0xF;
 815               fi->saved_regs[n] = next_addr + offset;
 816             }
 817           else if ((op & 0x3F1F0000) == 0x350F0000)
 818             {
 819               /* st2w  rn, @(offset,sp) */
 820               short offset = op & 0xFFFF;
 821               short n = (op >> 20) & 0xF;
 822               fi->saved_regs[n] = next_addr + offset;
 823               fi->saved_regs[n + 1] = next_addr + offset + 2;
 824             }
 825           else
 826             break;
 827         }
 828       else
 829         {
 830           /* short instructions */
 831           if ((op & 0xC0000000) == 0x80000000)
 832             {
 833               op2 = (op & 0x3FFF8000) >> 15;
 834               op1 = op & 0x7FFF;
 835             }
 836           else
 837             {
 838               op1 = (op & 0x3FFF8000) >> 15;
 839               op2 = op & 0x7FFF;
 840             }
 841           if (!prologue_find_regs (op1, fi, pc)
 842               || !prologue_find_regs (op2, fi, pc))
 843             break;
 844         }
 845       pc += 4;
 846     }
 847
 848   fi->extra_info->size = -next_addr;
 849
 850   if (!(fp & 0xffff))
 851     fp = d10v_make_daddr (read_register (SP_REGNUM));
 852
 853   for (i = 0; i < NUM_REGS - 1; i++)
 854     if (fi->saved_regs[i])
 855       {
 856         fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
 857       }
 858
 859   if (fi->saved_regs[LR_REGNUM])
 860     {
 861       CORE_ADDR return_pc
 862         = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM],
 863                                         REGISTER_RAW_SIZE (LR_REGNUM));
 864       fi->extra_info->return_pc = d10v_make_iaddr (return_pc);
 865     }
 866   else
 867     {
 868       fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM));
 869     }
 870
 871   /* The SP is not normally (ever?) saved, but check anyway */
 872   if (!fi->saved_regs[SP_REGNUM])
 873     {
 874       /* if the FP was saved, that means the current FP is valid, */
 875       /* otherwise, it isn't being used, so we use the SP instead */
 876       if (uses_frame)
 877         fi->saved_regs[SP_REGNUM]
 878           = read_register (FP_REGNUM) + fi->extra_info->size;
 879       else
 880         {
 881           fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
 882           fi->extra_info->frameless = 1;
 883           fi->saved_regs[FP_REGNUM] = 0;
 884         }
 885     }
 886 }
 887
 888 static void
 889 d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
 890 {
 891   fi->extra_info = (struct frame_extra_info *)
 892     frame_obstack_alloc (sizeof (struct frame_extra_info));
 893   frame_saved_regs_zalloc (fi);
 894
 895   fi->extra_info->frameless = 0;
 896   fi->extra_info->size = 0;
 897   fi->extra_info->return_pc = 0;
 898
 899   /* If fi->pc is zero, but this is not the outermost frame,
 900      then let's snatch the return_pc from the callee, so that
 901      PC_IN_CALL_DUMMY will work.  */
 902   if (fi->pc == 0 && fi->level != 0 && fi->next != NULL)
 903     fi->pc = d10v_frame_saved_pc (fi->next);
 904
 905   /* The call dummy doesn't save any registers on the stack, so we can
 906      return now.  */
 907   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 908     {
 909       return;
 910     }
 911   else
 912     {
 913       d10v_frame_init_saved_regs (fi);
 914     }
 915 }
 916
 917 static void
 918 show_regs (char *args, int from_tty)
 919 {
 920   int a;
 921   printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
 922                    (long) read_register (PC_REGNUM),
 923                    (long) d10v_make_iaddr (read_register (PC_REGNUM)),
 924                    (long) read_register (PSW_REGNUM),
 925                    (long) read_register (24),
 926                    (long) read_register (25),
 927                    (long) read_register (23));
 928   printf_filtered ("R0-R7  %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
 929                    (long) read_register (0),
 930                    (long) read_register (1),
 931                    (long) read_register (2),
 932                    (long) read_register (3),
 933                    (long) read_register (4),
 934                    (long) read_register (5),
 935                    (long) read_register (6),
 936                    (long) read_register (7));
 937   printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
 938                    (long) read_register (8),
 939                    (long) read_register (9),
 940                    (long) read_register (10),
 941                    (long) read_register (11),
 942                    (long) read_register (12),
 943                    (long) read_register (13),
 944                    (long) read_register (14),
 945                    (long) read_register (15));
 946   for (a = 0; a < NR_IMAP_REGS; a++)
 947     {
 948       if (a > 0)
 949         printf_filtered ("    ");
 950       printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
 951     }
 952   if (NR_DMAP_REGS == 1)
 953     printf_filtered ("    DMAP %04lx\n", d10v_dmap_register (2));
 954   else
 955     {
 956       for (a = 0; a < NR_DMAP_REGS; a++)
 957         {
 958           printf_filtered ("    DMAP%d %04lx", a, d10v_dmap_register (a));
 959         }
 960       printf_filtered ("\n");
 961     }
 962   printf_filtered ("A0-A%d", NR_A_REGS - 1);
 963   for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
 964     {
 965       char num[MAX_REGISTER_RAW_SIZE];
 966       int i;
 967       printf_filtered ("  ");
 968       read_register_gen (a, (char *) &num);
 969       for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
 970         {
 971           printf_filtered ("%02x", (num[i] & 0xff));
 972         }
 973     }
 974   printf_filtered ("\n");
 975 }
 976
 977 static CORE_ADDR
 978 d10v_read_pc (ptid_t ptid)
 979 {
 980   ptid_t save_ptid;
 981   CORE_ADDR pc;
 982   CORE_ADDR retval;
 983
 984   save_ptid = inferior_ptid;
 985   inferior_ptid = ptid;
 986   pc = (int) read_register (PC_REGNUM);
 987   inferior_ptid = save_ptid;
 988   retval = d10v_make_iaddr (pc);
 989   return retval;
 990 }
 991
 992 static void
 993 d10v_write_pc (CORE_ADDR val, ptid_t ptid)
 994 {
 995   ptid_t save_ptid;
 996
 997   save_ptid = inferior_ptid;
 998   inferior_ptid = ptid;
 999   write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val));
1000   inferior_ptid = save_ptid;
1001 }
1002
1003 static CORE_ADDR
1004 d10v_read_sp (void)
1005 {
1006   return (d10v_make_daddr (read_register (SP_REGNUM)));
1007 }
1008
1009 static void
1010 d10v_write_sp (CORE_ADDR val)
1011 {
1012   write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val));
1013 }
1014
1015 static CORE_ADDR
1016 d10v_read_fp (void)
1017 {
1018   return (d10v_make_daddr (read_register (FP_REGNUM)));
1019 }
1020
1021 /* Function: push_return_address (pc)
1022    Set up the return address for the inferior function call.
1023    Needed for targets where we don't actually execute a JSR/BSR instruction */
1024
1025 static CORE_ADDR
1026 d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1027 {
1028   write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
1029   return sp;
1030 }
1031
1032
1033 /* When arguments must be pushed onto the stack, they go on in reverse
1034    order.  The below implements a FILO (stack) to do this. */
1035
1036 struct stack_item
1037 {
1038   int len;
1039   struct stack_item *prev;
1040   void *data;
1041 };
1042
1043 static struct stack_item *push_stack_item (struct stack_item *prev,
1044                                            void *contents, int len);
1045 static struct stack_item *
1046 push_stack_item (struct stack_item *prev, void *contents, int len)
1047 {
1048   struct stack_item *si;
1049   si = xmalloc (sizeof (struct stack_item));
1050   si->data = xmalloc (len);
1051   si->len = len;
1052   si->prev = prev;
1053   memcpy (si->data, contents, len);
1054   return si;
1055 }
1056
1057 static struct stack_item *pop_stack_item (struct stack_item *si);
1058 static struct stack_item *
1059 pop_stack_item (struct stack_item *si)
1060 {
1061   struct stack_item *dead = si;
1062   si = si->prev;
1063   xfree (dead->data);
1064   xfree (dead);
1065   return si;
1066 }
1067
1068
1069 static CORE_ADDR
1070 d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1071                      int struct_return, CORE_ADDR struct_addr)
1072 {
1073   int i;
1074   int regnum = ARG1_REGNUM;
1075   struct stack_item *si = NULL;
1076
1077   /* Fill in registers and arg lists */
1078   for (i = 0; i < nargs; i++)
1079     {
1080       struct value *arg = args[i];
1081       struct type *type = check_typedef (VALUE_TYPE (arg));
1082       char *contents = VALUE_CONTENTS (arg);
1083       int len = TYPE_LENGTH (type);
1084       /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1085         {
1086           int aligned_regnum = (regnum + 1) & ~1;
1087           if (len <= 2 && regnum <= ARGN_REGNUM)
1088             /* fits in a single register, do not align */
1089             {
1090               long val = extract_unsigned_integer (contents, len);
1091               write_register (regnum++, val);
1092             }
1093           else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
1094             /* value fits in remaining registers, store keeping left
1095                aligned */
1096             {
1097               int b;
1098               regnum = aligned_regnum;
1099               for (b = 0; b < (len & ~1); b += 2)
1100                 {
1101                   long val = extract_unsigned_integer (&contents[b], 2);
1102                   write_register (regnum++, val);
1103                 }
1104               if (b < len)
1105                 {
1106                   long val = extract_unsigned_integer (&contents[b], 1);
1107                   write_register (regnum++, (val << 8));
1108                 }
1109             }
1110           else
1111             {
1112               /* arg will go onto stack */
1113               regnum = ARGN_REGNUM + 1;
1114               si = push_stack_item (si, contents, len);
1115             }
1116         }
1117     }
1118
1119   while (si)
1120     {
1121       sp = (sp - si->len) & ~1;
1122       write_memory (sp, si->data, si->len);
1123       si = pop_stack_item (si);
1124     }
1125
1126   return sp;
1127 }
1128
1129
1130 /* Given a return value in `regbuf' with a type `valtype',
1131    extract and copy its value into `valbuf'.  */
1132
1133 static void
1134 d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES],
1135                            char *valbuf)
1136 {
1137   int len;
1138   /*    printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)));  */
1139     {
1140       len = TYPE_LENGTH (type);
1141       if (len == 1)
1142         {
1143           unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1144           store_unsigned_integer (valbuf, 1, c);
1145         }
1146       else if ((len & 1) == 0)
1147         memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
1148       else
1149         {
1150           /* For return values of odd size, the first byte is in the
1151              least significant part of the first register.  The
1152              remaining bytes in remaining registers. Interestingly,
1153              when such values are passed in, the last byte is in the
1154              most significant byte of that same register - wierd. */
1155           memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
1156         }
1157     }
1158 }
1159
1160 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1161    understands.  Returns number of bytes that can be transfered
1162    starting at TARG_ADDR.  Return ZERO if no bytes can be transfered
1163    (segmentation fault).  Since the simulator knows all about how the
1164    VM system works, we just call that to do the translation. */
1165
1166 static void
1167 remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1168                                     CORE_ADDR *targ_addr, int *targ_len)
1169 {
1170   long out_addr;
1171   long out_len;
1172   out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
1173                                      &out_addr,
1174                                      d10v_dmap_register,
1175                                      d10v_imap_register);
1176   *targ_addr = out_addr;
1177   *targ_len = out_len;
1178 }
1179
1180
1181 /* The following code implements access to, and display of, the D10V's
1182    instruction trace buffer.  The buffer consists of 64K or more
1183    4-byte words of data, of which each words includes an 8-bit count,
1184    an 8-bit segment number, and a 16-bit instruction address.
1185
1186    In theory, the trace buffer is continuously capturing instruction
1187    data that the CPU presents on its "debug bus", but in practice, the
1188    ROMified GDB stub only enables tracing when it continues or steps
1189    the program, and stops tracing when the program stops; so it
1190    actually works for GDB to read the buffer counter out of memory and
1191    then read each trace word.  The counter records where the tracing
1192    stops, but there is no record of where it started, so we remember
1193    the PC when we resumed and then search backwards in the trace
1194    buffer for a word that includes that address.  This is not perfect,
1195    because you will miss trace data if the resumption PC is the target
1196    of a branch.  (The value of the buffer counter is semi-random, any
1197    trace data from a previous program stop is gone.)  */
1198
1199 /* The address of the last word recorded in the trace buffer.  */
1200
1201 #define DBBC_ADDR (0xd80000)
1202
1203 /* The base of the trace buffer, at least for the "Board_0".  */
1204
1205 #define TRACE_BUFFER_BASE (0xf40000)
1206
1207 static void trace_command (char *, int);
1208
1209 static void untrace_command (char *, int);
1210
1211 static void trace_info (char *, int);
1212
1213 static void tdisassemble_command (char *, int);
1214
1215 static void display_trace (int, int);
1216
1217 /* True when instruction traces are being collected.  */
1218
1219 static int tracing;
1220
1221 /* Remembered PC.  */
1222
1223 static CORE_ADDR last_pc;
1224
1225 /* True when trace output should be displayed whenever program stops.  */
1226
1227 static int trace_display;
1228
1229 /* True when trace listing should include source lines.  */
1230
1231 static int default_trace_show_source = 1;
1232
1233 struct trace_buffer
1234   {
1235     int size;
1236     short *counts;
1237     CORE_ADDR *addrs;
1238   }
1239 trace_data;
1240
1241 static void
1242 trace_command (char *args, int from_tty)
1243 {
1244   /* Clear the host-side trace buffer, allocating space if needed.  */
1245   trace_data.size = 0;
1246   if (trace_data.counts == NULL)
1247     trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1248   if (trace_data.addrs == NULL)
1249     trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1250
1251   tracing = 1;
1252
1253   printf_filtered ("Tracing is now on.\n");
1254 }
1255
1256 static void
1257 untrace_command (char *args, int from_tty)
1258 {
1259   tracing = 0;
1260
1261   printf_filtered ("Tracing is now off.\n");
1262 }
1263
1264 static void
1265 trace_info (char *args, int from_tty)
1266 {
1267   int i;
1268
1269   if (trace_data.size)
1270     {
1271       printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1272
1273       for (i = 0; i < trace_data.size; ++i)
1274         {
1275           printf_filtered ("%d: %d instruction%s at 0x%s\n",
1276                            i,
1277                            trace_data.counts[i],
1278                            (trace_data.counts[i] == 1 ? "" : "s"),
1279                            paddr_nz (trace_data.addrs[i]));
1280         }
1281     }
1282   else
1283     printf_filtered ("No entries in trace buffer.\n");
1284
1285   printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1286 }
1287
1288 /* Print the instruction at address MEMADDR in debugged memory,
1289    on STREAM.  Returns length of the instruction, in bytes.  */
1290
1291 static int
1292 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1293 {
1294   /* If there's no disassembler, something is very wrong.  */
1295   if (tm_print_insn == NULL)
1296     internal_error (__FILE__, __LINE__,
1297                     "print_insn: no disassembler");
1298
1299   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1300     tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1301   else
1302     tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1303   return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info);
1304 }
1305
1306 static void
1307 d10v_eva_prepare_to_trace (void)
1308 {
1309   if (!tracing)
1310     return;
1311
1312   last_pc = read_register (PC_REGNUM);
1313 }
1314
1315 /* Collect trace data from the target board and format it into a form
1316    more useful for display.  */
1317
1318 static void
1319 d10v_eva_get_trace_data (void)
1320 {
1321   int count, i, j, oldsize;
1322   int trace_addr, trace_seg, trace_cnt, next_cnt;
1323   unsigned int last_trace, trace_word, next_word;
1324   unsigned int *tmpspace;
1325
1326   if (!tracing)
1327     return;
1328
1329   tmpspace = xmalloc (65536 * sizeof (unsigned int));
1330
1331   last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1332
1333   /* Collect buffer contents from the target, stopping when we reach
1334      the word recorded when execution resumed.  */
1335
1336   count = 0;
1337   while (last_trace > 0)
1338     {
1339       QUIT;
1340       trace_word =
1341         read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1342       trace_addr = trace_word & 0xffff;
1343       last_trace -= 4;
1344       /* Ignore an apparently nonsensical entry.  */
1345       if (trace_addr == 0xffd5)
1346         continue;
1347       tmpspace[count++] = trace_word;
1348       if (trace_addr == last_pc)
1349         break;
1350       if (count > 65535)
1351         break;
1352     }
1353
1354   /* Move the data to the host-side trace buffer, adjusting counts to
1355      include the last instruction executed and transforming the address
1356      into something that GDB likes.  */
1357
1358   for (i = 0; i < count; ++i)
1359     {
1360       trace_word = tmpspace[i];
1361       next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1362       trace_addr = trace_word & 0xffff;
1363       next_cnt = (next_word >> 24) & 0xff;
1364       j = trace_data.size + count - i - 1;
1365       trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1366       trace_data.counts[j] = next_cnt + 1;
1367     }
1368
1369   oldsize = trace_data.size;
1370   trace_data.size += count;
1371
1372   xfree (tmpspace);
1373
1374   if (trace_display)
1375     display_trace (oldsize, trace_data.size);
1376 }
1377
1378 static void
1379 tdisassemble_command (char *arg, int from_tty)
1380 {
1381   int i, count;
1382   CORE_ADDR low, high;
1383   char *space_index;
1384
1385   if (!arg)
1386     {
1387       low = 0;
1388       high = trace_data.size;
1389     }
1390   else if (!(space_index = (char *) strchr (arg, ' ')))
1391     {
1392       low = parse_and_eval_address (arg);
1393       high = low + 5;
1394     }
1395   else
1396     {
1397       /* Two arguments.  */
1398       *space_index = '\0';
1399       low = parse_and_eval_address (arg);
1400       high = parse_and_eval_address (space_index + 1);
1401       if (high < low)
1402         high = low;
1403     }
1404
1405   printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
1406
1407   display_trace (low, high);
1408
1409   printf_filtered ("End of trace dump.\n");
1410   gdb_flush (gdb_stdout);
1411 }
1412
1413 static void
1414 display_trace (int low, int high)
1415 {
1416   int i, count, trace_show_source, first, suppress;
1417   CORE_ADDR next_address;
1418
1419   trace_show_source = default_trace_show_source;
1420   if (!have_full_symbols () && !have_partial_symbols ())
1421     {
1422       trace_show_source = 0;
1423       printf_filtered ("No symbol table is loaded.  Use the \"file\" command.\n");
1424       printf_filtered ("Trace will not display any source.\n");
1425     }
1426
1427   first = 1;
1428   suppress = 0;
1429   for (i = low; i < high; ++i)
1430     {
1431       next_address = trace_data.addrs[i];
1432       count = trace_data.counts[i];
1433       while (count-- > 0)
1434         {
1435           QUIT;
1436           if (trace_show_source)
1437             {
1438               struct symtab_and_line sal, sal_prev;
1439
1440               sal_prev = find_pc_line (next_address - 4, 0);
1441               sal = find_pc_line (next_address, 0);
1442
1443               if (sal.symtab)
1444                 {
1445                   if (first || sal.line != sal_prev.line)
1446                     print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1447                   suppress = 0;
1448                 }
1449               else
1450                 {
1451                   if (!suppress)
1452                     /* FIXME-32x64--assumes sal.pc fits in long.  */
1453                     printf_filtered ("No source file for address %s.\n",
1454                                  local_hex_string ((unsigned long) sal.pc));
1455                   suppress = 1;
1456                 }
1457             }
1458           first = 0;
1459           print_address (next_address, gdb_stdout);
1460           printf_filtered (":");
1461           printf_filtered ("\t");
1462           wrap_here ("    ");
1463           next_address = next_address + print_insn (next_address, gdb_stdout);
1464           printf_filtered ("\n");
1465           gdb_flush (gdb_stdout);
1466         }
1467     }
1468 }
1469
1470
1471 static gdbarch_init_ftype d10v_gdbarch_init;
1472
1473 static struct gdbarch *
1474 d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1475 {
1476   static LONGEST d10v_call_dummy_words[] =
1477   {0};
1478   struct gdbarch *gdbarch;
1479   int d10v_num_regs;
1480   struct gdbarch_tdep *tdep;
1481   gdbarch_register_name_ftype *d10v_register_name;
1482   gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
1483
1484   /* Find a candidate among the list of pre-declared architectures. */
1485   arches = gdbarch_list_lookup_by_info (arches, &info);
1486   if (arches != NULL)
1487     return arches->gdbarch;
1488
1489   /* None found, create a new architecture from the information
1490      provided. */
1491   tdep = XMALLOC (struct gdbarch_tdep);
1492   gdbarch = gdbarch_alloc (&info, tdep);
1493
1494   switch (info.bfd_arch_info->mach)
1495     {
1496     case bfd_mach_d10v_ts2:
1497       d10v_num_regs = 37;
1498       d10v_register_name = d10v_ts2_register_name;
1499       d10v_register_sim_regno = d10v_ts2_register_sim_regno;
1500       tdep->a0_regnum = TS2_A0_REGNUM;
1501       tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
1502       tdep->dmap_register = d10v_ts2_dmap_register;
1503       tdep->imap_register = d10v_ts2_imap_register;
1504       break;
1505     default:
1506     case bfd_mach_d10v_ts3:
1507       d10v_num_regs = 42;
1508       d10v_register_name = d10v_ts3_register_name;
1509       d10v_register_sim_regno = d10v_ts3_register_sim_regno;
1510       tdep->a0_regnum = TS3_A0_REGNUM;
1511       tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
1512       tdep->dmap_register = d10v_ts3_dmap_register;
1513       tdep->imap_register = d10v_ts3_imap_register;
1514       break;
1515     }
1516
1517   set_gdbarch_read_pc (gdbarch, d10v_read_pc);
1518   set_gdbarch_write_pc (gdbarch, d10v_write_pc);
1519   set_gdbarch_read_fp (gdbarch, d10v_read_fp);
1520   set_gdbarch_read_sp (gdbarch, d10v_read_sp);
1521   set_gdbarch_write_sp (gdbarch, d10v_write_sp);
1522
1523   set_gdbarch_num_regs (gdbarch, d10v_num_regs);
1524   set_gdbarch_sp_regnum (gdbarch, 15);
1525   set_gdbarch_fp_regnum (gdbarch, 11);
1526   set_gdbarch_pc_regnum (gdbarch, 18);
1527   set_gdbarch_register_name (gdbarch, d10v_register_name);
1528   set_gdbarch_register_size (gdbarch, 2);
1529   set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
1530   set_gdbarch_register_byte (gdbarch, d10v_register_byte);
1531   set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
1532   set_gdbarch_max_register_raw_size (gdbarch, 8);
1533   set_gdbarch_register_virtual_size (gdbarch, generic_register_size);
1534   set_gdbarch_max_register_virtual_size (gdbarch, 8);
1535   set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
1536
1537   set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1538   set_gdbarch_addr_bit (gdbarch, 32);
1539   set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer);
1540   set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address);
1541   set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address);
1542   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1543   set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1544   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1545   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1546   /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1547      double'' is 64 bits. */
1548   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1549   set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1550   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1551   switch (info.byte_order)
1552     {
1553     case BFD_ENDIAN_BIG:
1554       set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
1555       set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big);
1556       set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
1557       break;
1558     case BFD_ENDIAN_LITTLE:
1559       set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
1560       set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
1561       set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
1562       break;
1563     default:
1564       internal_error (__FILE__, __LINE__,
1565                       "d10v_gdbarch_init: bad byte order for float format");
1566     }
1567
1568   set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1569   set_gdbarch_call_dummy_length (gdbarch, 0);
1570   set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1571   set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1572   set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
1573   set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1574   set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1575   set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1576   set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
1577   set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
1578   set_gdbarch_call_dummy_p (gdbarch, 1);
1579   set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1580   set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1581   set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1582
1583   set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
1584   set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
1585   set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1586   set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
1587
1588   set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
1589   set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
1590   set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
1591   set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
1592
1593   set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
1594   set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
1595
1596   set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
1597
1598   set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
1599   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1600   set_gdbarch_decr_pc_after_break (gdbarch, 4);
1601   set_gdbarch_function_start_offset (gdbarch, 0);
1602   set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
1603
1604   set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
1605
1606   set_gdbarch_frame_args_skip (gdbarch, 0);
1607   set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1608   set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
1609   set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
1610   set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
1611   set_gdbarch_frame_args_address (gdbarch, default_frame_address);
1612   set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
1613   set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
1614   set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1615   set_gdbarch_stack_align (gdbarch, d10v_stack_align);
1616
1617   set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno);
1618   set_gdbarch_extra_stack_alignment_needed (gdbarch, 0);
1619
1620   return gdbarch;
1621 }
1622
1623
1624 extern void (*target_resume_hook) (void);
1625 extern void (*target_wait_loop_hook) (void);
1626
1627 void
1628 _initialize_d10v_tdep (void)
1629 {
1630   register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
1631
1632   tm_print_insn = print_insn_d10v;
1633
1634   target_resume_hook = d10v_eva_prepare_to_trace;
1635   target_wait_loop_hook = d10v_eva_get_trace_data;
1636
1637   add_com ("regs", class_vars, show_regs, "Print all registers");
1638
1639   add_com ("itrace", class_support, trace_command,
1640            "Enable tracing of instruction execution.");
1641
1642   add_com ("iuntrace", class_support, untrace_command,
1643            "Disable tracing of instruction execution.");
1644
1645   add_com ("itdisassemble", class_vars, tdisassemble_command,
1646            "Disassemble the trace buffer.\n\
1647 Two optional arguments specify a range of trace buffer entries\n\
1648 as reported by info trace (NOT addresses!).");
1649
1650   add_info ("itrace", trace_info,
1651             "Display info about the trace data buffer.");
1652
1653   add_show_from_set (add_set_cmd ("itracedisplay", no_class,
1654                                   var_integer, (char *) &trace_display,
1655                              "Set automatic display of trace.\n", &setlist),
1656                      &showlist);
1657   add_show_from_set (add_set_cmd ("itracesource", no_class,
1658                            var_integer, (char *) &default_trace_show_source,
1659                       "Set display of source code with trace.\n", &setlist),
1660                      &showlist);
1661
1662 }