1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
47 #include "trad-frame.h"
49 #include "gdb_assert.h"
55 unsigned long (*dmap_register
) (void *regcache
, int nr
);
56 unsigned long (*imap_register
) (void *regcache
, int nr
);
59 /* These are the addresses the D10V-EVA board maps data and
60 instruction memory to. */
63 DMEM_START
= 0x2000000,
64 IMEM_START
= 0x1000000,
65 STACK_START
= 0x200bffe
68 /* d10v register names. */
83 /* d10v calling convention. */
84 ARG1_REGNUM
= R0_REGNUM
,
85 ARGN_REGNUM
= R3_REGNUM
,
86 RET1_REGNUM
= R0_REGNUM
,
90 nr_dmap_regs (struct gdbarch
*gdbarch
)
92 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
96 a0_regnum (struct gdbarch
*gdbarch
)
98 return gdbarch_tdep (gdbarch
)->a0_regnum
;
101 /* Local functions */
103 extern void _initialize_d10v_tdep (void);
105 static void d10v_eva_prepare_to_trace (void);
107 static void d10v_eva_get_trace_data (void);
110 d10v_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
112 /* Align to the size of an instruction (so that they can safely be
113 pushed onto the stack. */
117 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
118 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
119 and TYPE is the type (which is known to be struct, union or array).
121 The d10v returns anything less than 8 bytes in size in
125 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
129 /* The d10v only passes a struct in a register when that structure
130 has an alignment that matches the size of a register. */
131 /* If the structure doesn't fit in 4 registers, put it on the
133 if (TYPE_LENGTH (type
) > 8)
135 /* If the struct contains only one field, don't put it on the stack
136 - gcc can fit it in one or more registers. */
137 if (TYPE_NFIELDS (type
) == 1)
139 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
140 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
142 /* If the alignment changes, just assume it goes on the
144 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
147 /* If the alignment is suitable for the d10v's 16 bit registers,
148 don't put it on the stack. */
149 if (alignment
== 2 || alignment
== 4)
155 static const unsigned char *
156 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
158 static unsigned char breakpoint
[] =
159 {0x2f, 0x90, 0x5e, 0x00};
160 *lenptr
= sizeof (breakpoint
);
164 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
165 when the reg_nr isn't valid. */
169 TS2_IMAP0_REGNUM
= 32,
170 TS2_DMAP_REGNUM
= 34,
171 TS2_NR_DMAP_REGS
= 1,
176 d10v_ts2_register_name (int reg_nr
)
178 static char *register_names
[] =
180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
182 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
183 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
184 "imap0", "imap1", "dmap", "a0", "a1"
188 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
190 return register_names
[reg_nr
];
195 TS3_IMAP0_REGNUM
= 36,
196 TS3_DMAP0_REGNUM
= 38,
197 TS3_NR_DMAP_REGS
= 4,
202 d10v_ts3_register_name (int reg_nr
)
204 static char *register_names
[] =
206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
209 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
213 "dmap0", "dmap1", "dmap2", "dmap3"
217 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
219 return register_names
[reg_nr
];
222 /* Access the DMAP/IMAP registers in a target independent way.
224 Divide the D10V's 64k data space into four 16k segments:
225 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
228 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
229 0x7fff) always map to the on-chip data RAM, and the fourth always
230 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
231 unified memory or instruction memory, under the control of the
232 single DMAP register.
234 On the TS3, there are four DMAP registers, each of which controls
235 one of the segments. */
238 d10v_ts2_dmap_register (void *regcache
, int reg_nr
)
248 regcache_cooked_read_unsigned (regcache
, TS2_DMAP_REGNUM
, ®
);
257 d10v_ts3_dmap_register (void *regcache
, int reg_nr
)
260 regcache_cooked_read_unsigned (regcache
, TS3_DMAP0_REGNUM
+ reg_nr
, ®
);
265 d10v_ts2_imap_register (void *regcache
, int reg_nr
)
268 regcache_cooked_read_unsigned (regcache
, TS2_IMAP0_REGNUM
+ reg_nr
, ®
);
273 d10v_ts3_imap_register (void *regcache
, int reg_nr
)
276 regcache_cooked_read_unsigned (regcache
, TS3_IMAP0_REGNUM
+ reg_nr
, ®
);
280 /* MAP GDB's internal register numbering (determined by the layout fo
281 the REGISTER_BYTE array) onto the simulator's register
285 d10v_ts2_register_sim_regno (int nr
)
287 /* Only makes sense to supply raw registers. */
288 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
289 if (nr
>= TS2_IMAP0_REGNUM
290 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
291 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
292 if (nr
== TS2_DMAP_REGNUM
)
293 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
294 if (nr
>= TS2_A0_REGNUM
295 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
296 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
301 d10v_ts3_register_sim_regno (int nr
)
303 /* Only makes sense to supply raw registers. */
304 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
305 if (nr
>= TS3_IMAP0_REGNUM
306 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
307 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
308 if (nr
>= TS3_DMAP0_REGNUM
309 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
310 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
311 if (nr
>= TS3_A0_REGNUM
312 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
313 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
317 /* Return the GDB type object for the "standard" data type
318 of data in register N. */
321 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
323 if (reg_nr
== D10V_PC_REGNUM
)
324 return builtin_type_void_func_ptr
;
325 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
326 return builtin_type_void_data_ptr
;
327 else if (reg_nr
>= a0_regnum (gdbarch
)
328 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
329 return builtin_type_int64
;
331 return builtin_type_int16
;
335 d10v_daddr_p (CORE_ADDR x
)
337 return (((x
) & 0x3000000) == DMEM_START
);
341 d10v_iaddr_p (CORE_ADDR x
)
343 return (((x
) & 0x3000000) == IMEM_START
);
347 d10v_make_daddr (CORE_ADDR x
)
349 return ((x
) | DMEM_START
);
353 d10v_make_iaddr (CORE_ADDR x
)
355 if (d10v_iaddr_p (x
))
356 return x
; /* Idempotency -- x is already in the IMEM space. */
358 return (((x
) << 2) | IMEM_START
);
362 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
364 return (((x
) >> 2) & 0xffff);
368 d10v_convert_daddr_to_raw (CORE_ADDR x
)
370 return ((x
) & 0xffff);
374 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
376 /* Is it a code address? */
377 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
378 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
380 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
381 d10v_convert_iaddr_to_raw (addr
));
385 /* Strip off any upper segment bits. */
386 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
387 d10v_convert_daddr_to_raw (addr
));
392 d10v_pointer_to_address (struct type
*type
, const void *buf
)
394 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
395 /* Is it a code address? */
396 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
397 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
398 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
399 return d10v_make_iaddr (addr
);
401 return d10v_make_daddr (addr
);
404 /* Don't do anything if we have an integer, this way users can type 'x
405 <addr>' w/o having gdb outsmart them. The internal gdb conversions
406 to the correct space are taken care of in the pointer_to_address
407 function. If we don't do this, 'x $fp' wouldn't work. */
409 d10v_integer_to_address (struct type
*type
, void *buf
)
412 val
= unpack_long (type
, buf
);
416 /* Write into appropriate registers a function return value
417 of type TYPE, given in virtual format.
419 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
422 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
425 /* Only char return values need to be shifted right within the first
427 if (TYPE_LENGTH (type
) == 1
428 && TYPE_CODE (type
) == TYPE_CODE_INT
)
431 tmp
[1] = *(bfd_byte
*)valbuf
;
432 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
437 /* A structure is never more than 8 bytes long. See
438 use_struct_convention(). */
439 gdb_assert (TYPE_LENGTH (type
) <= 8);
440 /* Write out most registers, stop loop before trying to write
441 out any dangling byte at the end of the buffer. */
442 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
444 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
445 (bfd_byte
*) valbuf
+ reg
* 2);
447 /* Write out any dangling byte at the end of the buffer. */
448 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
449 regcache_cooked_write_part (regcache
, reg
, 0, 1,
450 (bfd_byte
*) valbuf
+ reg
* 2);
454 /* Extract from an array REGBUF containing the (raw) register state
455 the address in which a function should return its structure value,
456 as a CORE_ADDR (or an expression that can be used as one). */
459 d10v_extract_struct_value_address (struct regcache
*regcache
)
462 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
463 return (addr
| DMEM_START
);
467 check_prologue (unsigned short op
)
470 if ((op
& 0x7E1F) == 0x6C1F)
474 if ((op
& 0x7E3F) == 0x6E1F)
478 if ((op
& 0x7FE1) == 0x01E1)
490 if ((op
& 0x7E1F) == 0x681E)
494 if ((op
& 0x7E3F) == 0x3A1E)
501 d10v_skip_prologue (CORE_ADDR pc
)
504 unsigned short op1
, op2
;
505 CORE_ADDR func_addr
, func_end
;
506 struct symtab_and_line sal
;
508 /* If we have line debugging information, then the end of the */
509 /* prologue should the first assembly instruction of the first source line */
510 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
512 sal
= find_pc_line (func_addr
, 0);
513 if (sal
.end
&& sal
.end
< func_end
)
517 if (target_read_memory (pc
, (char *) &op
, 4))
518 return pc
; /* Can't access it -- assume no prologue. */
522 op
= (unsigned long) read_memory_integer (pc
, 4);
523 if ((op
& 0xC0000000) == 0xC0000000)
525 /* long instruction */
526 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
527 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
528 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
533 /* short instructions */
534 if ((op
& 0xC0000000) == 0x80000000)
536 op2
= (op
& 0x3FFF8000) >> 15;
541 op1
= (op
& 0x3FFF8000) >> 15;
544 if (check_prologue (op1
))
546 if (!check_prologue (op2
))
548 /* if the previous opcode was really part of the prologue */
549 /* and not just a NOP, then we want to break after both instructions */
563 struct d10v_unwind_cache
565 /* The previous frame's inner most stack address. Used as this
566 frame ID's stack_addr. */
568 /* The frame's base, optionally used by the high-level debug info. */
571 /* How far the SP and r11 (FP) have been offset from the start of
572 the stack frame (as defined by the previous frame's stack
577 /* Table indicating the location of each and every register. */
578 struct trad_frame_saved_reg
*saved_regs
;
582 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
588 if ((op
& 0x7E1F) == 0x6C1F)
590 n
= (op
& 0x1E0) >> 5;
591 info
->sp_offset
-= 2;
592 info
->saved_regs
[n
].addr
= info
->sp_offset
;
597 else if ((op
& 0x7E3F) == 0x6E1F)
599 n
= (op
& 0x1E0) >> 5;
600 info
->sp_offset
-= 4;
601 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ 0;
602 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ 2;
607 if ((op
& 0x7FE1) == 0x01E1)
609 n
= (op
& 0x1E) >> 1;
612 info
->sp_offset
-= n
;
619 info
->uses_frame
= 1;
620 info
->r11_offset
= info
->sp_offset
;
625 if ((op
& 0x7E1F) == 0x6816)
627 n
= (op
& 0x1E0) >> 5;
628 info
->saved_regs
[n
].addr
= info
->r11_offset
;
637 if ((op
& 0x7E1F) == 0x681E)
639 n
= (op
& 0x1E0) >> 5;
640 info
->saved_regs
[n
].addr
= info
->sp_offset
;
645 if ((op
& 0x7E3F) == 0x3A1E)
647 n
= (op
& 0x1E0) >> 5;
648 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ 0;
649 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ 2;
656 /* Put here the code to store, into fi->saved_regs, the addresses of
657 the saved registers of frame described by FRAME_INFO. This
658 includes special registers such as pc and fp saved in special ways
659 in the stack frame. sp is even more special: the address we return
660 for it IS the sp for the next frame. */
662 static struct d10v_unwind_cache
*
663 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
664 void **this_prologue_cache
)
666 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
671 unsigned short op1
, op2
;
673 struct d10v_unwind_cache
*info
;
675 if ((*this_prologue_cache
))
676 return (*this_prologue_cache
);
678 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
679 (*this_prologue_cache
) = info
;
680 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
685 info
->uses_frame
= 0;
686 for (pc
= frame_func_unwind (next_frame
);
687 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
690 op
= get_frame_memory_unsigned (next_frame
, pc
, 4);
691 if ((op
& 0xC0000000) == 0xC0000000)
693 /* long instruction */
694 if ((op
& 0x3FFF0000) == 0x01FF0000)
697 short n
= op
& 0xFFFF;
698 info
->sp_offset
+= n
;
700 else if ((op
& 0x3F0F0000) == 0x340F0000)
702 /* st rn, @(offset,sp) */
703 short offset
= op
& 0xFFFF;
704 short n
= (op
>> 20) & 0xF;
705 info
->saved_regs
[n
].addr
= info
->sp_offset
+ offset
;
707 else if ((op
& 0x3F1F0000) == 0x350F0000)
709 /* st2w rn, @(offset,sp) */
710 short offset
= op
& 0xFFFF;
711 short n
= (op
>> 20) & 0xF;
712 info
->saved_regs
[n
+ 0].addr
= info
->sp_offset
+ offset
+ 0;
713 info
->saved_regs
[n
+ 1].addr
= info
->sp_offset
+ offset
+ 2;
720 /* short instructions */
721 if ((op
& 0xC0000000) == 0x80000000)
723 op2
= (op
& 0x3FFF8000) >> 15;
728 op1
= (op
& 0x3FFF8000) >> 15;
731 if (!prologue_find_regs (info
, op1
, pc
)
732 || !prologue_find_regs (info
, op2
, pc
))
737 info
->size
= -info
->sp_offset
;
739 /* Compute the previous frame's stack pointer (which is also the
740 frame's ID's stack address), and this frame's base pointer. */
741 if (info
->uses_frame
)
743 /* The SP was moved to the FP. This indicates that a new frame
744 was created. Get THIS frame's FP value by unwinding it from
746 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
747 /* The FP points at the last saved register. Adjust the FP back
748 to before the first saved register giving the SP. */
749 prev_sp
= this_base
+ info
->size
;
753 /* Assume that the FP is this frame's SP but with that pushed
754 stack space added back. */
755 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
756 prev_sp
= this_base
+ info
->size
;
759 /* Convert that SP/BASE into real addresses. */
760 info
->prev_sp
= d10v_make_daddr (prev_sp
);
761 info
->base
= d10v_make_daddr (this_base
);
763 /* Adjust all the saved registers so that they contain addresses and
765 for (i
= 0; i
< NUM_REGS
- 1; i
++)
766 if (trad_frame_addr_p (info
->saved_regs
, i
))
768 info
->saved_regs
[i
].addr
= (info
->prev_sp
+ info
->saved_regs
[i
].addr
);
771 /* The call instruction moves the caller's PC in the callee's LR.
772 Since this is an unwind, do the reverse. Copy the location of LR
773 into PC (the address / regnum) so that a request for PC will be
774 converted into a request for the LR. */
775 info
->saved_regs
[D10V_PC_REGNUM
] = info
->saved_regs
[LR_REGNUM
];
777 /* The previous frame's SP needed to be computed. Save the computed
779 trad_frame_set_value (info
->saved_regs
, D10V_SP_REGNUM
,
780 d10v_make_daddr (prev_sp
));
786 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
787 struct frame_info
*frame
, int regnum
, int all
)
789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
792 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
797 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
798 frame_read_unsigned_register (frame
, D10V_PC_REGNUM
, &pc
);
799 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
800 frame_read_unsigned_register (frame
, frame_map_name_to_regnum (frame
, "rpt_s", -1), &rpt_s
);
801 frame_read_unsigned_register (frame
, frame_map_name_to_regnum (frame
, "rpt_e", -1), &rpt_e
);
802 frame_read_unsigned_register (frame
, frame_map_name_to_regnum (frame
, "rpt_c", -1), &rpt_c
);
803 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
804 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
805 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
810 for (group
= 0; group
< 16; group
+= 8)
813 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
814 for (r
= group
; r
< group
+ 8; r
++)
817 frame_read_unsigned_register (frame
, r
, &tmp
);
818 fprintf_filtered (file
, " %04lx", (long) tmp
);
820 fprintf_filtered (file
, "\n");
824 /* Note: The IMAP/DMAP registers don't participate in function
825 calls. Don't bother trying to unwind them. */
829 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
832 fprintf_filtered (file
, " ");
833 fprintf_filtered (file
, "IMAP%d %04lx", a
,
834 tdep
->imap_register (current_regcache
, a
));
836 if (nr_dmap_regs (gdbarch
) == 1)
837 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
838 fprintf_filtered (file
, " DMAP %04lx\n",
839 tdep
->dmap_register (current_regcache
, 2));
842 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
844 fprintf_filtered (file
, " DMAP%d %04lx", a
,
845 tdep
->dmap_register (current_regcache
, a
));
847 fprintf_filtered (file
, "\n");
852 char num
[MAX_REGISTER_SIZE
];
854 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
855 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
858 fprintf_filtered (file
, " ");
859 frame_read_register (frame
, a
, num
);
860 for (i
= 0; i
< register_size (gdbarch
, a
); i
++)
862 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
866 fprintf_filtered (file
, "\n");
870 show_regs (char *args
, int from_tty
)
872 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
873 get_current_frame (), -1, 1);
877 d10v_read_pc (ptid_t ptid
)
883 save_ptid
= inferior_ptid
;
884 inferior_ptid
= ptid
;
885 pc
= (int) read_register (D10V_PC_REGNUM
);
886 inferior_ptid
= save_ptid
;
887 retval
= d10v_make_iaddr (pc
);
892 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
896 save_ptid
= inferior_ptid
;
897 inferior_ptid
= ptid
;
898 write_register (D10V_PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
899 inferior_ptid
= save_ptid
;
903 d10v_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
906 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &sp
);
907 return d10v_make_daddr (sp
);
910 /* When arguments must be pushed onto the stack, they go on in reverse
911 order. The below implements a FILO (stack) to do this. */
916 struct stack_item
*prev
;
920 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
921 void *contents
, int len
);
922 static struct stack_item
*
923 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
925 struct stack_item
*si
;
926 si
= xmalloc (sizeof (struct stack_item
));
927 si
->data
= xmalloc (len
);
930 memcpy (si
->data
, contents
, len
);
934 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
935 static struct stack_item
*
936 pop_stack_item (struct stack_item
*si
)
938 struct stack_item
*dead
= si
;
947 d10v_push_dummy_code (struct gdbarch
*gdbarch
,
948 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
949 struct value
**args
, int nargs
,
950 struct type
*value_type
,
951 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
953 /* Allocate space sufficient for a breakpoint. */
955 /* Store the address of that breakpoint taking care to first convert
956 it into a code (IADDR) address from a stack (DADDR) address.
957 This of course assumes that the two virtual addresses map onto
958 the same real address. */
959 (*bp_addr
) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp
));
960 /* d10v always starts the call at the callee's entry point. */
961 (*real_pc
) = funaddr
;
966 d10v_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
967 struct regcache
*regcache
, CORE_ADDR bp_addr
,
968 int nargs
, struct value
**args
, CORE_ADDR sp
, int struct_return
,
969 CORE_ADDR struct_addr
)
972 int regnum
= ARG1_REGNUM
;
973 struct stack_item
*si
= NULL
;
976 /* Set the return address. For the d10v, the return breakpoint is
977 always at BP_ADDR. */
978 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
979 d10v_convert_iaddr_to_raw (bp_addr
));
981 /* If STRUCT_RETURN is true, then the struct return address (in
982 STRUCT_ADDR) will consume the first argument-passing register.
983 Both adjust the register count and store that value. */
986 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
990 /* Fill in registers and arg lists */
991 for (i
= 0; i
< nargs
; i
++)
993 struct value
*arg
= args
[i
];
994 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
995 char *contents
= VALUE_CONTENTS (arg
);
996 int len
= TYPE_LENGTH (type
);
997 int aligned_regnum
= (regnum
+ 1) & ~1;
999 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1000 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1001 /* fits in a single register, do not align */
1003 val
= extract_unsigned_integer (contents
, len
);
1004 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1006 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1007 /* value fits in remaining registers, store keeping left
1011 regnum
= aligned_regnum
;
1012 for (b
= 0; b
< (len
& ~1); b
+= 2)
1014 val
= extract_unsigned_integer (&contents
[b
], 2);
1015 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1019 val
= extract_unsigned_integer (&contents
[b
], 1);
1020 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1025 /* arg will go onto stack */
1026 regnum
= ARGN_REGNUM
+ 1;
1027 si
= push_stack_item (si
, contents
, len
);
1033 sp
= (sp
- si
->len
) & ~1;
1034 write_memory (sp
, si
->data
, si
->len
);
1035 si
= pop_stack_item (si
);
1038 /* Finally, update the SP register. */
1039 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1040 d10v_convert_daddr_to_raw (sp
));
1046 /* Given a return value in `regbuf' with a type `valtype',
1047 extract and copy its value into `valbuf'. */
1050 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1054 if (TYPE_LENGTH (type
) == 1)
1057 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1058 store_unsigned_integer (valbuf
, 1, c
);
1062 /* For return values of odd size, the first byte is in the
1063 least significant part of the first register. The
1064 remaining bytes in remaining registers. Interestingly, when
1065 such values are passed in, the last byte is in the most
1066 significant byte of that same register - wierd. */
1067 int reg
= RET1_REGNUM
;
1069 if (TYPE_LENGTH (type
) & 1)
1071 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1072 (bfd_byte
*)valbuf
+ off
);
1076 /* Transfer the remaining registers. */
1077 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1079 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1080 (bfd_byte
*) valbuf
+ off
);
1085 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1086 understands. Returns number of bytes that can be transfered
1087 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1088 (segmentation fault). Since the simulator knows all about how the
1089 VM system works, we just call that to do the translation. */
1092 remote_d10v_translate_xfer_address (struct gdbarch
*gdbarch
,
1093 struct regcache
*regcache
,
1094 CORE_ADDR memaddr
, int nr_bytes
,
1095 CORE_ADDR
*targ_addr
, int *targ_len
)
1097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1100 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
, &out_addr
, regcache
,
1101 tdep
->dmap_register
, tdep
->imap_register
);
1102 *targ_addr
= out_addr
;
1103 *targ_len
= out_len
;
1107 /* The following code implements access to, and display of, the D10V's
1108 instruction trace buffer. The buffer consists of 64K or more
1109 4-byte words of data, of which each words includes an 8-bit count,
1110 an 8-bit segment number, and a 16-bit instruction address.
1112 In theory, the trace buffer is continuously capturing instruction
1113 data that the CPU presents on its "debug bus", but in practice, the
1114 ROMified GDB stub only enables tracing when it continues or steps
1115 the program, and stops tracing when the program stops; so it
1116 actually works for GDB to read the buffer counter out of memory and
1117 then read each trace word. The counter records where the tracing
1118 stops, but there is no record of where it started, so we remember
1119 the PC when we resumed and then search backwards in the trace
1120 buffer for a word that includes that address. This is not perfect,
1121 because you will miss trace data if the resumption PC is the target
1122 of a branch. (The value of the buffer counter is semi-random, any
1123 trace data from a previous program stop is gone.) */
1125 /* The address of the last word recorded in the trace buffer. */
1127 #define DBBC_ADDR (0xd80000)
1129 /* The base of the trace buffer, at least for the "Board_0". */
1131 #define TRACE_BUFFER_BASE (0xf40000)
1133 static void trace_command (char *, int);
1135 static void untrace_command (char *, int);
1137 static void trace_info (char *, int);
1139 static void tdisassemble_command (char *, int);
1141 static void display_trace (int, int);
1143 /* True when instruction traces are being collected. */
1147 /* Remembered PC. */
1149 static CORE_ADDR last_pc
;
1151 /* True when trace output should be displayed whenever program stops. */
1153 static int trace_display
;
1155 /* True when trace listing should include source lines. */
1157 static int default_trace_show_source
= 1;
1168 trace_command (char *args
, int from_tty
)
1170 /* Clear the host-side trace buffer, allocating space if needed. */
1171 trace_data
.size
= 0;
1172 if (trace_data
.counts
== NULL
)
1173 trace_data
.counts
= XCALLOC (65536, short);
1174 if (trace_data
.addrs
== NULL
)
1175 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1179 printf_filtered ("Tracing is now on.\n");
1183 untrace_command (char *args
, int from_tty
)
1187 printf_filtered ("Tracing is now off.\n");
1191 trace_info (char *args
, int from_tty
)
1195 if (trace_data
.size
)
1197 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1199 for (i
= 0; i
< trace_data
.size
; ++i
)
1201 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1203 trace_data
.counts
[i
],
1204 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1205 paddr_nz (trace_data
.addrs
[i
]));
1209 printf_filtered ("No entries in trace buffer.\n");
1211 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1215 d10v_eva_prepare_to_trace (void)
1220 last_pc
= read_register (D10V_PC_REGNUM
);
1223 /* Collect trace data from the target board and format it into a form
1224 more useful for display. */
1227 d10v_eva_get_trace_data (void)
1229 int count
, i
, j
, oldsize
;
1230 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1231 unsigned int last_trace
, trace_word
, next_word
;
1232 unsigned int *tmpspace
;
1237 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1239 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1241 /* Collect buffer contents from the target, stopping when we reach
1242 the word recorded when execution resumed. */
1245 while (last_trace
> 0)
1249 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1250 trace_addr
= trace_word
& 0xffff;
1252 /* Ignore an apparently nonsensical entry. */
1253 if (trace_addr
== 0xffd5)
1255 tmpspace
[count
++] = trace_word
;
1256 if (trace_addr
== last_pc
)
1262 /* Move the data to the host-side trace buffer, adjusting counts to
1263 include the last instruction executed and transforming the address
1264 into something that GDB likes. */
1266 for (i
= 0; i
< count
; ++i
)
1268 trace_word
= tmpspace
[i
];
1269 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1270 trace_addr
= trace_word
& 0xffff;
1271 next_cnt
= (next_word
>> 24) & 0xff;
1272 j
= trace_data
.size
+ count
- i
- 1;
1273 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1274 trace_data
.counts
[j
] = next_cnt
+ 1;
1277 oldsize
= trace_data
.size
;
1278 trace_data
.size
+= count
;
1283 display_trace (oldsize
, trace_data
.size
);
1287 tdisassemble_command (char *arg
, int from_tty
)
1290 CORE_ADDR low
, high
;
1295 high
= trace_data
.size
;
1299 char *space_index
= strchr (arg
, ' ');
1300 if (space_index
== NULL
)
1302 low
= parse_and_eval_address (arg
);
1307 /* Two arguments. */
1308 *space_index
= '\0';
1309 low
= parse_and_eval_address (arg
);
1310 high
= parse_and_eval_address (space_index
+ 1);
1316 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1318 display_trace (low
, high
);
1320 printf_filtered ("End of trace dump.\n");
1321 gdb_flush (gdb_stdout
);
1325 display_trace (int low
, int high
)
1327 int i
, count
, trace_show_source
, first
, suppress
;
1328 CORE_ADDR next_address
;
1330 trace_show_source
= default_trace_show_source
;
1331 if (!have_full_symbols () && !have_partial_symbols ())
1333 trace_show_source
= 0;
1334 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1335 printf_filtered ("Trace will not display any source.\n");
1340 for (i
= low
; i
< high
; ++i
)
1342 next_address
= trace_data
.addrs
[i
];
1343 count
= trace_data
.counts
[i
];
1347 if (trace_show_source
)
1349 struct symtab_and_line sal
, sal_prev
;
1351 sal_prev
= find_pc_line (next_address
- 4, 0);
1352 sal
= find_pc_line (next_address
, 0);
1356 if (first
|| sal
.line
!= sal_prev
.line
)
1357 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1363 /* FIXME-32x64--assumes sal.pc fits in long. */
1364 printf_filtered ("No source file for address %s.\n",
1365 local_hex_string ((unsigned long) sal
.pc
));
1370 print_address (next_address
, gdb_stdout
);
1371 printf_filtered (":");
1372 printf_filtered ("\t");
1374 next_address
+= gdb_print_insn (next_address
, gdb_stdout
);
1375 printf_filtered ("\n");
1376 gdb_flush (gdb_stdout
);
1382 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1385 frame_unwind_unsigned_register (next_frame
, D10V_PC_REGNUM
, &pc
);
1386 return d10v_make_iaddr (pc
);
1389 /* Given a GDB frame, determine the address of the calling function's
1390 frame. This will be used to create a new GDB frame struct. */
1393 d10v_frame_this_id (struct frame_info
*next_frame
,
1394 void **this_prologue_cache
,
1395 struct frame_id
*this_id
)
1397 struct d10v_unwind_cache
*info
1398 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1403 /* The FUNC is easy. */
1404 func
= frame_func_unwind (next_frame
);
1406 /* This is meant to halt the backtrace at "_start". Make sure we
1407 don't halt it at a generic dummy frame. */
1408 if (func
<= IMEM_START
|| inside_entry_file (func
))
1411 /* Hopefully the prologue analysis either correctly determined the
1412 frame's base (which is the SP from the previous frame), or set
1413 that base to "NULL". */
1414 base
= info
->prev_sp
;
1415 if (base
== STACK_START
|| base
== 0)
1418 id
= frame_id_build (base
, func
);
1424 d10v_frame_prev_register (struct frame_info
*next_frame
,
1425 void **this_prologue_cache
,
1426 int regnum
, int *optimizedp
,
1427 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1428 int *realnump
, void *bufferp
)
1430 struct d10v_unwind_cache
*info
1431 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1432 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1433 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
1436 static const struct frame_unwind d10v_frame_unwind
= {
1439 d10v_frame_prev_register
1442 static const struct frame_unwind
*
1443 d10v_frame_sniffer (struct frame_info
*next_frame
)
1445 return &d10v_frame_unwind
;
1449 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1451 struct d10v_unwind_cache
*info
1452 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1456 static const struct frame_base d10v_frame_base
= {
1458 d10v_frame_base_address
,
1459 d10v_frame_base_address
,
1460 d10v_frame_base_address
1463 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1464 dummy frame. The frame ID's base needs to match the TOS value
1465 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1468 static struct frame_id
1469 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1471 return frame_id_build (d10v_unwind_sp (gdbarch
, next_frame
),
1472 frame_pc_unwind (next_frame
));
1475 static gdbarch_init_ftype d10v_gdbarch_init
;
1477 static struct gdbarch
*
1478 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1480 struct gdbarch
*gdbarch
;
1482 struct gdbarch_tdep
*tdep
;
1483 gdbarch_register_name_ftype
*d10v_register_name
;
1484 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1486 /* Find a candidate among the list of pre-declared architectures. */
1487 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1489 return arches
->gdbarch
;
1491 /* None found, create a new architecture from the information
1493 tdep
= XMALLOC (struct gdbarch_tdep
);
1494 gdbarch
= gdbarch_alloc (&info
, tdep
);
1496 switch (info
.bfd_arch_info
->mach
)
1498 case bfd_mach_d10v_ts2
:
1500 d10v_register_name
= d10v_ts2_register_name
;
1501 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1502 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1503 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1504 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1505 tdep
->imap_register
= d10v_ts2_imap_register
;
1508 case bfd_mach_d10v_ts3
:
1510 d10v_register_name
= d10v_ts3_register_name
;
1511 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1512 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1513 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1514 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1515 tdep
->imap_register
= d10v_ts3_imap_register
;
1519 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1520 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1521 set_gdbarch_unwind_sp (gdbarch
, d10v_unwind_sp
);
1523 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1524 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1525 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1526 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1528 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1529 set_gdbarch_addr_bit (gdbarch
, 32);
1530 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1531 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1532 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1533 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1534 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1535 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1536 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1537 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1538 double'' is 64 bits. */
1539 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1540 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1541 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1542 switch (info
.byte_order
)
1544 case BFD_ENDIAN_BIG
:
1545 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1546 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1547 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1549 case BFD_ENDIAN_LITTLE
:
1550 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1551 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1552 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1555 internal_error (__FILE__
, __LINE__
,
1556 "d10v_gdbarch_init: bad byte order for float format");
1559 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1560 set_gdbarch_push_dummy_code (gdbarch
, d10v_push_dummy_code
);
1561 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1562 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1563 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1564 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1566 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1567 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1568 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1569 set_gdbarch_function_start_offset (gdbarch
, 0);
1570 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1572 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1574 set_gdbarch_frame_args_skip (gdbarch
, 0);
1575 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1577 set_gdbarch_frame_align (gdbarch
, d10v_frame_align
);
1579 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1581 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1583 frame_unwind_append_sniffer (gdbarch
, d10v_frame_sniffer
);
1584 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1586 /* Methods for saving / extracting a dummy frame's ID. The ID's
1587 stack address must match the SP value returned by
1588 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
1589 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1591 /* Return the unwound PC value. */
1592 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1594 set_gdbarch_print_insn (gdbarch
, print_insn_d10v
);
1600 _initialize_d10v_tdep (void)
1602 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1604 target_resume_hook
= d10v_eva_prepare_to_trace
;
1605 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1607 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1610 add_com ("itrace", class_support
, trace_command
,
1611 "Enable tracing of instruction execution.");
1613 add_com ("iuntrace", class_support
, untrace_command
,
1614 "Disable tracing of instruction execution.");
1616 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1617 "Disassemble the trace buffer.\n\
1618 Two optional arguments specify a range of trace buffer entries\n\
1619 as reported by info trace (NOT addresses!).");
1621 add_info ("itrace", trace_info
,
1622 "Display info about the trace data buffer.");
1624 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1625 "Set automatic display of trace.\n",
1626 "Show automatic display of trace.\n",
1627 NULL
, NULL
, &setlist
, &showlist
);
1628 add_setshow_boolean_cmd ("itracesource", no_class
,
1629 &default_trace_show_source
,
1630 "Set display of source code with trace.\n",
1631 "Show display of source code with trace.\n",
1632 NULL
, NULL
, &setlist
, &showlist
);