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[deliverable/binutils-gdb.git] / gdb / d10v-tdep.c
1 /* Target-dependent code for Mitsubishi D10V, for GDB.
2
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software
4 Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
24
25 #include "defs.h"
26 #include "frame.h"
27 #include "obstack.h"
28 #include "symtab.h"
29 #include "gdbtypes.h"
30 #include "gdbcmd.h"
31 #include "gdbcore.h"
32 #include "gdb_string.h"
33 #include "value.h"
34 #include "inferior.h"
35 #include "dis-asm.h"
36 #include "symfile.h"
37 #include "objfiles.h"
38 #include "language.h"
39 #include "arch-utils.h"
40 #include "regcache.h"
41
42 #include "floatformat.h"
43 #include "sim-d10v.h"
44
45 struct frame_extra_info
46 {
47 CORE_ADDR return_pc;
48 int frameless;
49 int size;
50 };
51
52 struct gdbarch_tdep
53 {
54 int a0_regnum;
55 int nr_dmap_regs;
56 unsigned long (*dmap_register) (int nr);
57 unsigned long (*imap_register) (int nr);
58 };
59
60 /* These are the addresses the D10V-EVA board maps data and
61 instruction memory to. */
62
63 #define DMEM_START 0x2000000
64 #define IMEM_START 0x1000000
65 #define STACK_START 0x200bffe
66
67 /* d10v register names. */
68
69 enum
70 {
71 R0_REGNUM = 0,
72 LR_REGNUM = 13,
73 PSW_REGNUM = 16,
74 NR_IMAP_REGS = 2,
75 NR_A_REGS = 2
76 };
77 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
78 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
79
80 /* d10v calling convention. */
81
82 #define ARG1_REGNUM R0_REGNUM
83 #define ARGN_REGNUM 3
84 #define RET1_REGNUM R0_REGNUM
85
86 /* Local functions */
87
88 extern void _initialize_d10v_tdep (void);
89
90 static void d10v_eva_prepare_to_trace (void);
91
92 static void d10v_eva_get_trace_data (void);
93
94 static int prologue_find_regs (unsigned short op, struct frame_info *fi,
95 CORE_ADDR addr);
96
97 static void d10v_frame_init_saved_regs (struct frame_info *);
98
99 static void do_d10v_pop_frame (struct frame_info *fi);
100
101 static int
102 d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame)
103 {
104 return ((chain) != 0 && (frame) != 0
105 && (frame)->pc > IMEM_START
106 && !inside_entry_file (FRAME_SAVED_PC (frame)));
107 }
108
109 static CORE_ADDR
110 d10v_stack_align (CORE_ADDR len)
111 {
112 return (len + 1) & ~1;
113 }
114
115 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
116 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
117 and TYPE is the type (which is known to be struct, union or array).
118
119 The d10v returns anything less than 8 bytes in size in
120 registers. */
121
122 static int
123 d10v_use_struct_convention (int gcc_p, struct type *type)
124 {
125 long alignment;
126 int i;
127 /* The d10v only passes a struct in a register when that structure
128 has an alignment that matches the size of a register. */
129 /* If the structure doesn't fit in 4 registers, put it on the
130 stack. */
131 if (TYPE_LENGTH (type) > 8)
132 return 1;
133 /* If the struct contains only one field, don't put it on the stack
134 - gcc can fit it in one or more registers. */
135 if (TYPE_NFIELDS (type) == 1)
136 return 0;
137 alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0));
138 for (i = 1; i < TYPE_NFIELDS (type); i++)
139 {
140 /* If the alignment changes, just assume it goes on the
141 stack. */
142 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment)
143 return 1;
144 }
145 /* If the alignment is suitable for the d10v's 16 bit registers,
146 don't put it on the stack. */
147 if (alignment == 2 || alignment == 4)
148 return 0;
149 return 1;
150 }
151
152
153 static unsigned char *
154 d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
155 {
156 static unsigned char breakpoint[] =
157 {0x2f, 0x90, 0x5e, 0x00};
158 *lenptr = sizeof (breakpoint);
159 return breakpoint;
160 }
161
162 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
163 when the reg_nr isn't valid. */
164
165 enum ts2_regnums
166 {
167 TS2_IMAP0_REGNUM = 32,
168 TS2_DMAP_REGNUM = 34,
169 TS2_NR_DMAP_REGS = 1,
170 TS2_A0_REGNUM = 35
171 };
172
173 static char *
174 d10v_ts2_register_name (int reg_nr)
175 {
176 static char *register_names[] =
177 {
178 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
179 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
180 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
181 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
182 "imap0", "imap1", "dmap", "a0", "a1"
183 };
184 if (reg_nr < 0)
185 return NULL;
186 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
187 return NULL;
188 return register_names[reg_nr];
189 }
190
191 enum ts3_regnums
192 {
193 TS3_IMAP0_REGNUM = 36,
194 TS3_DMAP0_REGNUM = 38,
195 TS3_NR_DMAP_REGS = 4,
196 TS3_A0_REGNUM = 32
197 };
198
199 static char *
200 d10v_ts3_register_name (int reg_nr)
201 {
202 static char *register_names[] =
203 {
204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
206 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
207 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
208 "a0", "a1",
209 "spi", "spu",
210 "imap0", "imap1",
211 "dmap0", "dmap1", "dmap2", "dmap3"
212 };
213 if (reg_nr < 0)
214 return NULL;
215 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
216 return NULL;
217 return register_names[reg_nr];
218 }
219
220 /* Access the DMAP/IMAP registers in a target independent way.
221
222 Divide the D10V's 64k data space into four 16k segments:
223 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
224 0xc000 -- 0xffff.
225
226 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
227 0x7fff) always map to the on-chip data RAM, and the fourth always
228 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
229 unified memory or instruction memory, under the control of the
230 single DMAP register.
231
232 On the TS3, there are four DMAP registers, each of which controls
233 one of the segments. */
234
235 static unsigned long
236 d10v_ts2_dmap_register (int reg_nr)
237 {
238 switch (reg_nr)
239 {
240 case 0:
241 case 1:
242 return 0x2000;
243 case 2:
244 return read_register (TS2_DMAP_REGNUM);
245 default:
246 return 0;
247 }
248 }
249
250 static unsigned long
251 d10v_ts3_dmap_register (int reg_nr)
252 {
253 return read_register (TS3_DMAP0_REGNUM + reg_nr);
254 }
255
256 static unsigned long
257 d10v_dmap_register (int reg_nr)
258 {
259 return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr);
260 }
261
262 static unsigned long
263 d10v_ts2_imap_register (int reg_nr)
264 {
265 return read_register (TS2_IMAP0_REGNUM + reg_nr);
266 }
267
268 static unsigned long
269 d10v_ts3_imap_register (int reg_nr)
270 {
271 return read_register (TS3_IMAP0_REGNUM + reg_nr);
272 }
273
274 static unsigned long
275 d10v_imap_register (int reg_nr)
276 {
277 return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr);
278 }
279
280 /* MAP GDB's internal register numbering (determined by the layout fo
281 the REGISTER_BYTE array) onto the simulator's register
282 numbering. */
283
284 static int
285 d10v_ts2_register_sim_regno (int nr)
286 {
287 if (nr >= TS2_IMAP0_REGNUM
288 && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS)
289 return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
290 if (nr == TS2_DMAP_REGNUM)
291 return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM;
292 if (nr >= TS2_A0_REGNUM
293 && nr < TS2_A0_REGNUM + NR_A_REGS)
294 return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM;
295 return nr;
296 }
297
298 static int
299 d10v_ts3_register_sim_regno (int nr)
300 {
301 if (nr >= TS3_IMAP0_REGNUM
302 && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS)
303 return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM;
304 if (nr >= TS3_DMAP0_REGNUM
305 && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS)
306 return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM;
307 if (nr >= TS3_A0_REGNUM
308 && nr < TS3_A0_REGNUM + NR_A_REGS)
309 return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM;
310 return nr;
311 }
312
313 /* Index within `registers' of the first byte of the space for
314 register REG_NR. */
315
316 static int
317 d10v_register_byte (int reg_nr)
318 {
319 if (reg_nr < A0_REGNUM)
320 return (reg_nr * 2);
321 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
322 return (A0_REGNUM * 2
323 + (reg_nr - A0_REGNUM) * 8);
324 else
325 return (A0_REGNUM * 2
326 + NR_A_REGS * 8
327 + (reg_nr - A0_REGNUM - NR_A_REGS) * 2);
328 }
329
330 /* Number of bytes of storage in the actual machine representation for
331 register REG_NR. */
332
333 static int
334 d10v_register_raw_size (int reg_nr)
335 {
336 if (reg_nr < A0_REGNUM)
337 return 2;
338 else if (reg_nr < (A0_REGNUM + NR_A_REGS))
339 return 8;
340 else
341 return 2;
342 }
343
344 /* Return the GDB type object for the "standard" data type
345 of data in register N. */
346
347 static struct type *
348 d10v_register_virtual_type (int reg_nr)
349 {
350 if (reg_nr == PC_REGNUM)
351 return builtin_type_void_func_ptr;
352 else if (reg_nr >= A0_REGNUM
353 && reg_nr < (A0_REGNUM + NR_A_REGS))
354 return builtin_type_int64;
355 else
356 return builtin_type_int16;
357 }
358
359 static CORE_ADDR
360 d10v_make_daddr (CORE_ADDR x)
361 {
362 return ((x) | DMEM_START);
363 }
364
365 static CORE_ADDR
366 d10v_make_iaddr (CORE_ADDR x)
367 {
368 return (((x) << 2) | IMEM_START);
369 }
370
371 static int
372 d10v_daddr_p (CORE_ADDR x)
373 {
374 return (((x) & 0x3000000) == DMEM_START);
375 }
376
377 static int
378 d10v_iaddr_p (CORE_ADDR x)
379 {
380 return (((x) & 0x3000000) == IMEM_START);
381 }
382
383
384 static CORE_ADDR
385 d10v_convert_iaddr_to_raw (CORE_ADDR x)
386 {
387 return (((x) >> 2) & 0xffff);
388 }
389
390 static CORE_ADDR
391 d10v_convert_daddr_to_raw (CORE_ADDR x)
392 {
393 return ((x) & 0xffff);
394 }
395
396 static void
397 d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr)
398 {
399 /* Is it a code address? */
400 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
401 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD)
402 {
403 store_unsigned_integer (buf, TYPE_LENGTH (type),
404 d10v_convert_iaddr_to_raw (addr));
405 }
406 else
407 {
408 /* Strip off any upper segment bits. */
409 store_unsigned_integer (buf, TYPE_LENGTH (type),
410 d10v_convert_daddr_to_raw (addr));
411 }
412 }
413
414 static CORE_ADDR
415 d10v_pointer_to_address (struct type *type, void *buf)
416 {
417 CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type));
418
419 /* Is it a code address? */
420 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
421 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
422 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type)))
423 return d10v_make_iaddr (addr);
424 else
425 return d10v_make_daddr (addr);
426 }
427
428 static CORE_ADDR
429 d10v_integer_to_address (struct type *type, void *buf)
430 {
431 LONGEST val;
432 val = unpack_long (type, buf);
433 if (TYPE_CODE (type) == TYPE_CODE_INT
434 && TYPE_LENGTH (type) <= TYPE_LENGTH (builtin_type_void_data_ptr))
435 /* Convert small integers that would would be directly copied into
436 a pointer variable into an address pointing into data space. */
437 return d10v_make_daddr (val & 0xffff);
438 else
439 /* The value is too large to fit in a pointer. Assume this was
440 intentional and that the user in fact specified a raw address. */
441 return val;
442 }
443
444 /* Store the address of the place in which to copy the structure the
445 subroutine will return. This is called from call_function.
446
447 We store structs through a pointer passed in the first Argument
448 register. */
449
450 static void
451 d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
452 {
453 write_register (ARG1_REGNUM, (addr));
454 }
455
456 /* Write into appropriate registers a function return value
457 of type TYPE, given in virtual format.
458
459 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
460
461 static void
462 d10v_store_return_value (struct type *type, char *valbuf)
463 {
464 write_register_bytes (REGISTER_BYTE (RET1_REGNUM),
465 valbuf,
466 TYPE_LENGTH (type));
467 }
468
469 /* Extract from an array REGBUF containing the (raw) register state
470 the address in which a function should return its structure value,
471 as a CORE_ADDR (or an expression that can be used as one). */
472
473 static CORE_ADDR
474 d10v_extract_struct_value_address (char *regbuf)
475 {
476 return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM),
477 REGISTER_RAW_SIZE (ARG1_REGNUM))
478 | DMEM_START);
479 }
480
481 static CORE_ADDR
482 d10v_frame_saved_pc (struct frame_info *frame)
483 {
484 return ((frame)->extra_info->return_pc);
485 }
486
487 /* Immediately after a function call, return the saved pc. We can't
488 use frame->return_pc beause that is determined by reading R13 off
489 the stack and that may not be written yet. */
490
491 static CORE_ADDR
492 d10v_saved_pc_after_call (struct frame_info *frame)
493 {
494 return ((read_register (LR_REGNUM) << 2)
495 | IMEM_START);
496 }
497
498 /* Discard from the stack the innermost frame, restoring all saved
499 registers. */
500
501 static void
502 d10v_pop_frame (void)
503 {
504 generic_pop_current_frame (do_d10v_pop_frame);
505 }
506
507 static void
508 do_d10v_pop_frame (struct frame_info *fi)
509 {
510 CORE_ADDR fp;
511 int regnum;
512 char raw_buffer[8];
513
514 fp = FRAME_FP (fi);
515 /* fill out fsr with the address of where each */
516 /* register was stored in the frame */
517 d10v_frame_init_saved_regs (fi);
518
519 /* now update the current registers with the old values */
520 for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++)
521 {
522 if (fi->saved_regs[regnum])
523 {
524 read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum));
525 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum));
526 }
527 }
528 for (regnum = 0; regnum < SP_REGNUM; regnum++)
529 {
530 if (fi->saved_regs[regnum])
531 {
532 write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)));
533 }
534 }
535 if (fi->saved_regs[PSW_REGNUM])
536 {
537 write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM)));
538 }
539
540 write_register (PC_REGNUM, read_register (LR_REGNUM));
541 write_register (SP_REGNUM, fp + fi->extra_info->size);
542 target_store_registers (-1);
543 flush_cached_frames ();
544 }
545
546 static int
547 check_prologue (unsigned short op)
548 {
549 /* st rn, @-sp */
550 if ((op & 0x7E1F) == 0x6C1F)
551 return 1;
552
553 /* st2w rn, @-sp */
554 if ((op & 0x7E3F) == 0x6E1F)
555 return 1;
556
557 /* subi sp, n */
558 if ((op & 0x7FE1) == 0x01E1)
559 return 1;
560
561 /* mv r11, sp */
562 if (op == 0x417E)
563 return 1;
564
565 /* nop */
566 if (op == 0x5E00)
567 return 1;
568
569 /* st rn, @sp */
570 if ((op & 0x7E1F) == 0x681E)
571 return 1;
572
573 /* st2w rn, @sp */
574 if ((op & 0x7E3F) == 0x3A1E)
575 return 1;
576
577 return 0;
578 }
579
580 static CORE_ADDR
581 d10v_skip_prologue (CORE_ADDR pc)
582 {
583 unsigned long op;
584 unsigned short op1, op2;
585 CORE_ADDR func_addr, func_end;
586 struct symtab_and_line sal;
587
588 /* If we have line debugging information, then the end of the */
589 /* prologue should the first assembly instruction of the first source line */
590 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
591 {
592 sal = find_pc_line (func_addr, 0);
593 if (sal.end && sal.end < func_end)
594 return sal.end;
595 }
596
597 if (target_read_memory (pc, (char *) &op, 4))
598 return pc; /* Can't access it -- assume no prologue. */
599
600 while (1)
601 {
602 op = (unsigned long) read_memory_integer (pc, 4);
603 if ((op & 0xC0000000) == 0xC0000000)
604 {
605 /* long instruction */
606 if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
607 ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
608 ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
609 break;
610 }
611 else
612 {
613 /* short instructions */
614 if ((op & 0xC0000000) == 0x80000000)
615 {
616 op2 = (op & 0x3FFF8000) >> 15;
617 op1 = op & 0x7FFF;
618 }
619 else
620 {
621 op1 = (op & 0x3FFF8000) >> 15;
622 op2 = op & 0x7FFF;
623 }
624 if (check_prologue (op1))
625 {
626 if (!check_prologue (op2))
627 {
628 /* if the previous opcode was really part of the prologue */
629 /* and not just a NOP, then we want to break after both instructions */
630 if (op1 != 0x5E00)
631 pc += 4;
632 break;
633 }
634 }
635 else
636 break;
637 }
638 pc += 4;
639 }
640 return pc;
641 }
642
643 /* Given a GDB frame, determine the address of the calling function's frame.
644 This will be used to create a new GDB frame struct, and then
645 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
646 */
647
648 static CORE_ADDR
649 d10v_frame_chain (struct frame_info *fi)
650 {
651 d10v_frame_init_saved_regs (fi);
652
653 if (fi->extra_info->return_pc == IMEM_START
654 || inside_entry_file (fi->extra_info->return_pc))
655 return (CORE_ADDR) 0;
656
657 if (!fi->saved_regs[FP_REGNUM])
658 {
659 if (!fi->saved_regs[SP_REGNUM]
660 || fi->saved_regs[SP_REGNUM] == STACK_START)
661 return (CORE_ADDR) 0;
662
663 return fi->saved_regs[SP_REGNUM];
664 }
665
666 if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
667 REGISTER_RAW_SIZE (FP_REGNUM)))
668 return (CORE_ADDR) 0;
669
670 return d10v_make_daddr (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM],
671 REGISTER_RAW_SIZE (FP_REGNUM)));
672 }
673
674 static int next_addr, uses_frame;
675
676 static int
677 prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr)
678 {
679 int n;
680
681 /* st rn, @-sp */
682 if ((op & 0x7E1F) == 0x6C1F)
683 {
684 n = (op & 0x1E0) >> 5;
685 next_addr -= 2;
686 fi->saved_regs[n] = next_addr;
687 return 1;
688 }
689
690 /* st2w rn, @-sp */
691 else if ((op & 0x7E3F) == 0x6E1F)
692 {
693 n = (op & 0x1E0) >> 5;
694 next_addr -= 4;
695 fi->saved_regs[n] = next_addr;
696 fi->saved_regs[n + 1] = next_addr + 2;
697 return 1;
698 }
699
700 /* subi sp, n */
701 if ((op & 0x7FE1) == 0x01E1)
702 {
703 n = (op & 0x1E) >> 1;
704 if (n == 0)
705 n = 16;
706 next_addr -= n;
707 return 1;
708 }
709
710 /* mv r11, sp */
711 if (op == 0x417E)
712 {
713 uses_frame = 1;
714 return 1;
715 }
716
717 /* nop */
718 if (op == 0x5E00)
719 return 1;
720
721 /* st rn, @sp */
722 if ((op & 0x7E1F) == 0x681E)
723 {
724 n = (op & 0x1E0) >> 5;
725 fi->saved_regs[n] = next_addr;
726 return 1;
727 }
728
729 /* st2w rn, @sp */
730 if ((op & 0x7E3F) == 0x3A1E)
731 {
732 n = (op & 0x1E0) >> 5;
733 fi->saved_regs[n] = next_addr;
734 fi->saved_regs[n + 1] = next_addr + 2;
735 return 1;
736 }
737
738 return 0;
739 }
740
741 /* Put here the code to store, into fi->saved_regs, the addresses of
742 the saved registers of frame described by FRAME_INFO. This
743 includes special registers such as pc and fp saved in special ways
744 in the stack frame. sp is even more special: the address we return
745 for it IS the sp for the next frame. */
746
747 static void
748 d10v_frame_init_saved_regs (struct frame_info *fi)
749 {
750 CORE_ADDR fp, pc;
751 unsigned long op;
752 unsigned short op1, op2;
753 int i;
754
755 fp = fi->frame;
756 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
757 next_addr = 0;
758
759 pc = get_pc_function_start (fi->pc);
760
761 uses_frame = 0;
762 while (1)
763 {
764 op = (unsigned long) read_memory_integer (pc, 4);
765 if ((op & 0xC0000000) == 0xC0000000)
766 {
767 /* long instruction */
768 if ((op & 0x3FFF0000) == 0x01FF0000)
769 {
770 /* add3 sp,sp,n */
771 short n = op & 0xFFFF;
772 next_addr += n;
773 }
774 else if ((op & 0x3F0F0000) == 0x340F0000)
775 {
776 /* st rn, @(offset,sp) */
777 short offset = op & 0xFFFF;
778 short n = (op >> 20) & 0xF;
779 fi->saved_regs[n] = next_addr + offset;
780 }
781 else if ((op & 0x3F1F0000) == 0x350F0000)
782 {
783 /* st2w rn, @(offset,sp) */
784 short offset = op & 0xFFFF;
785 short n = (op >> 20) & 0xF;
786 fi->saved_regs[n] = next_addr + offset;
787 fi->saved_regs[n + 1] = next_addr + offset + 2;
788 }
789 else
790 break;
791 }
792 else
793 {
794 /* short instructions */
795 if ((op & 0xC0000000) == 0x80000000)
796 {
797 op2 = (op & 0x3FFF8000) >> 15;
798 op1 = op & 0x7FFF;
799 }
800 else
801 {
802 op1 = (op & 0x3FFF8000) >> 15;
803 op2 = op & 0x7FFF;
804 }
805 if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc))
806 break;
807 }
808 pc += 4;
809 }
810
811 fi->extra_info->size = -next_addr;
812
813 if (!(fp & 0xffff))
814 fp = d10v_make_daddr (read_register (SP_REGNUM));
815
816 for (i = 0; i < NUM_REGS - 1; i++)
817 if (fi->saved_regs[i])
818 {
819 fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]);
820 }
821
822 if (fi->saved_regs[LR_REGNUM])
823 {
824 CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM));
825 fi->extra_info->return_pc = d10v_make_iaddr (return_pc);
826 }
827 else
828 {
829 fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM));
830 }
831
832 /* th SP is not normally (ever?) saved, but check anyway */
833 if (!fi->saved_regs[SP_REGNUM])
834 {
835 /* if the FP was saved, that means the current FP is valid, */
836 /* otherwise, it isn't being used, so we use the SP instead */
837 if (uses_frame)
838 fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size;
839 else
840 {
841 fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size;
842 fi->extra_info->frameless = 1;
843 fi->saved_regs[FP_REGNUM] = 0;
844 }
845 }
846 }
847
848 static void
849 d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
850 {
851 fi->extra_info = (struct frame_extra_info *)
852 frame_obstack_alloc (sizeof (struct frame_extra_info));
853 frame_saved_regs_zalloc (fi);
854
855 fi->extra_info->frameless = 0;
856 fi->extra_info->size = 0;
857 fi->extra_info->return_pc = 0;
858
859 /* The call dummy doesn't save any registers on the stack, so we can
860 return now. */
861 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
862 {
863 return;
864 }
865 else
866 {
867 d10v_frame_init_saved_regs (fi);
868 }
869 }
870
871 static void
872 show_regs (char *args, int from_tty)
873 {
874 int a;
875 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
876 (long) read_register (PC_REGNUM),
877 (long) d10v_make_iaddr (read_register (PC_REGNUM)),
878 (long) read_register (PSW_REGNUM),
879 (long) read_register (24),
880 (long) read_register (25),
881 (long) read_register (23));
882 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
883 (long) read_register (0),
884 (long) read_register (1),
885 (long) read_register (2),
886 (long) read_register (3),
887 (long) read_register (4),
888 (long) read_register (5),
889 (long) read_register (6),
890 (long) read_register (7));
891 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
892 (long) read_register (8),
893 (long) read_register (9),
894 (long) read_register (10),
895 (long) read_register (11),
896 (long) read_register (12),
897 (long) read_register (13),
898 (long) read_register (14),
899 (long) read_register (15));
900 for (a = 0; a < NR_IMAP_REGS; a++)
901 {
902 if (a > 0)
903 printf_filtered (" ");
904 printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
905 }
906 if (NR_DMAP_REGS == 1)
907 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
908 else
909 {
910 for (a = 0; a < NR_DMAP_REGS; a++)
911 {
912 printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a));
913 }
914 printf_filtered ("\n");
915 }
916 printf_filtered ("A0-A%d", NR_A_REGS - 1);
917 for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
918 {
919 char num[MAX_REGISTER_RAW_SIZE];
920 int i;
921 printf_filtered (" ");
922 read_register_gen (a, (char *) &num);
923 for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
924 {
925 printf_filtered ("%02x", (num[i] & 0xff));
926 }
927 }
928 printf_filtered ("\n");
929 }
930
931 static CORE_ADDR
932 d10v_read_pc (ptid_t ptid)
933 {
934 ptid_t save_ptid;
935 CORE_ADDR pc;
936 CORE_ADDR retval;
937
938 save_ptid = inferior_ptid;
939 inferior_ptid = ptid;
940 pc = (int) read_register (PC_REGNUM);
941 inferior_ptid = save_ptid;
942 retval = d10v_make_iaddr (pc);
943 return retval;
944 }
945
946 static void
947 d10v_write_pc (CORE_ADDR val, ptid_t ptid)
948 {
949 ptid_t save_ptid;
950
951 save_ptid = inferior_ptid;
952 inferior_ptid = ptid;
953 write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val));
954 inferior_ptid = save_ptid;
955 }
956
957 static CORE_ADDR
958 d10v_read_sp (void)
959 {
960 return (d10v_make_daddr (read_register (SP_REGNUM)));
961 }
962
963 static void
964 d10v_write_sp (CORE_ADDR val)
965 {
966 write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val));
967 }
968
969 static CORE_ADDR
970 d10v_read_fp (void)
971 {
972 return (d10v_make_daddr (read_register (FP_REGNUM)));
973 }
974
975 /* Function: push_return_address (pc)
976 Set up the return address for the inferior function call.
977 Needed for targets where we don't actually execute a JSR/BSR instruction */
978
979 static CORE_ADDR
980 d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
981 {
982 write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
983 return sp;
984 }
985
986
987 /* When arguments must be pushed onto the stack, they go on in reverse
988 order. The below implements a FILO (stack) to do this. */
989
990 struct stack_item
991 {
992 int len;
993 struct stack_item *prev;
994 void *data;
995 };
996
997 static struct stack_item *push_stack_item (struct stack_item *prev,
998 void *contents, int len);
999 static struct stack_item *
1000 push_stack_item (struct stack_item *prev, void *contents, int len)
1001 {
1002 struct stack_item *si;
1003 si = xmalloc (sizeof (struct stack_item));
1004 si->data = xmalloc (len);
1005 si->len = len;
1006 si->prev = prev;
1007 memcpy (si->data, contents, len);
1008 return si;
1009 }
1010
1011 static struct stack_item *pop_stack_item (struct stack_item *si);
1012 static struct stack_item *
1013 pop_stack_item (struct stack_item *si)
1014 {
1015 struct stack_item *dead = si;
1016 si = si->prev;
1017 xfree (dead->data);
1018 xfree (dead);
1019 return si;
1020 }
1021
1022
1023 static CORE_ADDR
1024 d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1025 int struct_return, CORE_ADDR struct_addr)
1026 {
1027 int i;
1028 int regnum = ARG1_REGNUM;
1029 struct stack_item *si = NULL;
1030
1031 /* Fill in registers and arg lists */
1032 for (i = 0; i < nargs; i++)
1033 {
1034 struct value *arg = args[i];
1035 struct type *type = check_typedef (VALUE_TYPE (arg));
1036 char *contents = VALUE_CONTENTS (arg);
1037 int len = TYPE_LENGTH (type);
1038 /* printf ("push: type=%d len=%d\n", type->code, len); */
1039 {
1040 int aligned_regnum = (regnum + 1) & ~1;
1041 if (len <= 2 && regnum <= ARGN_REGNUM)
1042 /* fits in a single register, do not align */
1043 {
1044 long val = extract_unsigned_integer (contents, len);
1045 write_register (regnum++, val);
1046 }
1047 else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
1048 /* value fits in remaining registers, store keeping left
1049 aligned */
1050 {
1051 int b;
1052 regnum = aligned_regnum;
1053 for (b = 0; b < (len & ~1); b += 2)
1054 {
1055 long val = extract_unsigned_integer (&contents[b], 2);
1056 write_register (regnum++, val);
1057 }
1058 if (b < len)
1059 {
1060 long val = extract_unsigned_integer (&contents[b], 1);
1061 write_register (regnum++, (val << 8));
1062 }
1063 }
1064 else
1065 {
1066 /* arg will go onto stack */
1067 regnum = ARGN_REGNUM + 1;
1068 si = push_stack_item (si, contents, len);
1069 }
1070 }
1071 }
1072
1073 while (si)
1074 {
1075 sp = (sp - si->len) & ~1;
1076 write_memory (sp, si->data, si->len);
1077 si = pop_stack_item (si);
1078 }
1079
1080 return sp;
1081 }
1082
1083
1084 /* Given a return value in `regbuf' with a type `valtype',
1085 extract and copy its value into `valbuf'. */
1086
1087 static void
1088 d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES],
1089 char *valbuf)
1090 {
1091 int len;
1092 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1093 {
1094 len = TYPE_LENGTH (type);
1095 if (len == 1)
1096 {
1097 unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
1098 store_unsigned_integer (valbuf, 1, c);
1099 }
1100 else if ((len & 1) == 0)
1101 memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
1102 else
1103 {
1104 /* For return values of odd size, the first byte is in the
1105 least significant part of the first register. The
1106 remaining bytes in remaining registers. Interestingly,
1107 when such values are passed in, the last byte is in the
1108 most significant byte of that same register - wierd. */
1109 memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
1110 }
1111 }
1112 }
1113
1114 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1115 understands. Returns number of bytes that can be transfered
1116 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1117 (segmentation fault). Since the simulator knows all about how the
1118 VM system works, we just call that to do the translation. */
1119
1120 static void
1121 remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
1122 CORE_ADDR *targ_addr, int *targ_len)
1123 {
1124 long out_addr;
1125 long out_len;
1126 out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
1127 &out_addr,
1128 d10v_dmap_register,
1129 d10v_imap_register);
1130 *targ_addr = out_addr;
1131 *targ_len = out_len;
1132 }
1133
1134
1135 /* The following code implements access to, and display of, the D10V's
1136 instruction trace buffer. The buffer consists of 64K or more
1137 4-byte words of data, of which each words includes an 8-bit count,
1138 an 8-bit segment number, and a 16-bit instruction address.
1139
1140 In theory, the trace buffer is continuously capturing instruction
1141 data that the CPU presents on its "debug bus", but in practice, the
1142 ROMified GDB stub only enables tracing when it continues or steps
1143 the program, and stops tracing when the program stops; so it
1144 actually works for GDB to read the buffer counter out of memory and
1145 then read each trace word. The counter records where the tracing
1146 stops, but there is no record of where it started, so we remember
1147 the PC when we resumed and then search backwards in the trace
1148 buffer for a word that includes that address. This is not perfect,
1149 because you will miss trace data if the resumption PC is the target
1150 of a branch. (The value of the buffer counter is semi-random, any
1151 trace data from a previous program stop is gone.) */
1152
1153 /* The address of the last word recorded in the trace buffer. */
1154
1155 #define DBBC_ADDR (0xd80000)
1156
1157 /* The base of the trace buffer, at least for the "Board_0". */
1158
1159 #define TRACE_BUFFER_BASE (0xf40000)
1160
1161 static void trace_command (char *, int);
1162
1163 static void untrace_command (char *, int);
1164
1165 static void trace_info (char *, int);
1166
1167 static void tdisassemble_command (char *, int);
1168
1169 static void display_trace (int, int);
1170
1171 /* True when instruction traces are being collected. */
1172
1173 static int tracing;
1174
1175 /* Remembered PC. */
1176
1177 static CORE_ADDR last_pc;
1178
1179 /* True when trace output should be displayed whenever program stops. */
1180
1181 static int trace_display;
1182
1183 /* True when trace listing should include source lines. */
1184
1185 static int default_trace_show_source = 1;
1186
1187 struct trace_buffer
1188 {
1189 int size;
1190 short *counts;
1191 CORE_ADDR *addrs;
1192 }
1193 trace_data;
1194
1195 static void
1196 trace_command (char *args, int from_tty)
1197 {
1198 /* Clear the host-side trace buffer, allocating space if needed. */
1199 trace_data.size = 0;
1200 if (trace_data.counts == NULL)
1201 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1202 if (trace_data.addrs == NULL)
1203 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1204
1205 tracing = 1;
1206
1207 printf_filtered ("Tracing is now on.\n");
1208 }
1209
1210 static void
1211 untrace_command (char *args, int from_tty)
1212 {
1213 tracing = 0;
1214
1215 printf_filtered ("Tracing is now off.\n");
1216 }
1217
1218 static void
1219 trace_info (char *args, int from_tty)
1220 {
1221 int i;
1222
1223 if (trace_data.size)
1224 {
1225 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1226
1227 for (i = 0; i < trace_data.size; ++i)
1228 {
1229 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1230 i,
1231 trace_data.counts[i],
1232 (trace_data.counts[i] == 1 ? "" : "s"),
1233 paddr_nz (trace_data.addrs[i]));
1234 }
1235 }
1236 else
1237 printf_filtered ("No entries in trace buffer.\n");
1238
1239 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1240 }
1241
1242 /* Print the instruction at address MEMADDR in debugged memory,
1243 on STREAM. Returns length of the instruction, in bytes. */
1244
1245 static int
1246 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1247 {
1248 /* If there's no disassembler, something is very wrong. */
1249 if (tm_print_insn == NULL)
1250 internal_error (__FILE__, __LINE__,
1251 "print_insn: no disassembler");
1252
1253 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1254 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1255 else
1256 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1257 return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info);
1258 }
1259
1260 static void
1261 d10v_eva_prepare_to_trace (void)
1262 {
1263 if (!tracing)
1264 return;
1265
1266 last_pc = read_register (PC_REGNUM);
1267 }
1268
1269 /* Collect trace data from the target board and format it into a form
1270 more useful for display. */
1271
1272 static void
1273 d10v_eva_get_trace_data (void)
1274 {
1275 int count, i, j, oldsize;
1276 int trace_addr, trace_seg, trace_cnt, next_cnt;
1277 unsigned int last_trace, trace_word, next_word;
1278 unsigned int *tmpspace;
1279
1280 if (!tracing)
1281 return;
1282
1283 tmpspace = xmalloc (65536 * sizeof (unsigned int));
1284
1285 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1286
1287 /* Collect buffer contents from the target, stopping when we reach
1288 the word recorded when execution resumed. */
1289
1290 count = 0;
1291 while (last_trace > 0)
1292 {
1293 QUIT;
1294 trace_word =
1295 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1296 trace_addr = trace_word & 0xffff;
1297 last_trace -= 4;
1298 /* Ignore an apparently nonsensical entry. */
1299 if (trace_addr == 0xffd5)
1300 continue;
1301 tmpspace[count++] = trace_word;
1302 if (trace_addr == last_pc)
1303 break;
1304 if (count > 65535)
1305 break;
1306 }
1307
1308 /* Move the data to the host-side trace buffer, adjusting counts to
1309 include the last instruction executed and transforming the address
1310 into something that GDB likes. */
1311
1312 for (i = 0; i < count; ++i)
1313 {
1314 trace_word = tmpspace[i];
1315 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1316 trace_addr = trace_word & 0xffff;
1317 next_cnt = (next_word >> 24) & 0xff;
1318 j = trace_data.size + count - i - 1;
1319 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1320 trace_data.counts[j] = next_cnt + 1;
1321 }
1322
1323 oldsize = trace_data.size;
1324 trace_data.size += count;
1325
1326 xfree (tmpspace);
1327
1328 if (trace_display)
1329 display_trace (oldsize, trace_data.size);
1330 }
1331
1332 static void
1333 tdisassemble_command (char *arg, int from_tty)
1334 {
1335 int i, count;
1336 CORE_ADDR low, high;
1337 char *space_index;
1338
1339 if (!arg)
1340 {
1341 low = 0;
1342 high = trace_data.size;
1343 }
1344 else if (!(space_index = (char *) strchr (arg, ' ')))
1345 {
1346 low = parse_and_eval_address (arg);
1347 high = low + 5;
1348 }
1349 else
1350 {
1351 /* Two arguments. */
1352 *space_index = '\0';
1353 low = parse_and_eval_address (arg);
1354 high = parse_and_eval_address (space_index + 1);
1355 if (high < low)
1356 high = low;
1357 }
1358
1359 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
1360
1361 display_trace (low, high);
1362
1363 printf_filtered ("End of trace dump.\n");
1364 gdb_flush (gdb_stdout);
1365 }
1366
1367 static void
1368 display_trace (int low, int high)
1369 {
1370 int i, count, trace_show_source, first, suppress;
1371 CORE_ADDR next_address;
1372
1373 trace_show_source = default_trace_show_source;
1374 if (!have_full_symbols () && !have_partial_symbols ())
1375 {
1376 trace_show_source = 0;
1377 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1378 printf_filtered ("Trace will not display any source.\n");
1379 }
1380
1381 first = 1;
1382 suppress = 0;
1383 for (i = low; i < high; ++i)
1384 {
1385 next_address = trace_data.addrs[i];
1386 count = trace_data.counts[i];
1387 while (count-- > 0)
1388 {
1389 QUIT;
1390 if (trace_show_source)
1391 {
1392 struct symtab_and_line sal, sal_prev;
1393
1394 sal_prev = find_pc_line (next_address - 4, 0);
1395 sal = find_pc_line (next_address, 0);
1396
1397 if (sal.symtab)
1398 {
1399 if (first || sal.line != sal_prev.line)
1400 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1401 suppress = 0;
1402 }
1403 else
1404 {
1405 if (!suppress)
1406 /* FIXME-32x64--assumes sal.pc fits in long. */
1407 printf_filtered ("No source file for address %s.\n",
1408 local_hex_string ((unsigned long) sal.pc));
1409 suppress = 1;
1410 }
1411 }
1412 first = 0;
1413 print_address (next_address, gdb_stdout);
1414 printf_filtered (":");
1415 printf_filtered ("\t");
1416 wrap_here (" ");
1417 next_address = next_address + print_insn (next_address, gdb_stdout);
1418 printf_filtered ("\n");
1419 gdb_flush (gdb_stdout);
1420 }
1421 }
1422 }
1423
1424
1425 static gdbarch_init_ftype d10v_gdbarch_init;
1426
1427 static struct gdbarch *
1428 d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1429 {
1430 static LONGEST d10v_call_dummy_words[] =
1431 {0};
1432 struct gdbarch *gdbarch;
1433 int d10v_num_regs;
1434 struct gdbarch_tdep *tdep;
1435 gdbarch_register_name_ftype *d10v_register_name;
1436 gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
1437
1438 /* Find a candidate among the list of pre-declared architectures. */
1439 arches = gdbarch_list_lookup_by_info (arches, &info);
1440 if (arches != NULL)
1441 return arches->gdbarch;
1442
1443 /* None found, create a new architecture from the information
1444 provided. */
1445 tdep = XMALLOC (struct gdbarch_tdep);
1446 gdbarch = gdbarch_alloc (&info, tdep);
1447
1448 switch (info.bfd_arch_info->mach)
1449 {
1450 case bfd_mach_d10v_ts2:
1451 d10v_num_regs = 37;
1452 d10v_register_name = d10v_ts2_register_name;
1453 d10v_register_sim_regno = d10v_ts2_register_sim_regno;
1454 tdep->a0_regnum = TS2_A0_REGNUM;
1455 tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
1456 tdep->dmap_register = d10v_ts2_dmap_register;
1457 tdep->imap_register = d10v_ts2_imap_register;
1458 break;
1459 default:
1460 case bfd_mach_d10v_ts3:
1461 d10v_num_regs = 42;
1462 d10v_register_name = d10v_ts3_register_name;
1463 d10v_register_sim_regno = d10v_ts3_register_sim_regno;
1464 tdep->a0_regnum = TS3_A0_REGNUM;
1465 tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
1466 tdep->dmap_register = d10v_ts3_dmap_register;
1467 tdep->imap_register = d10v_ts3_imap_register;
1468 break;
1469 }
1470
1471 set_gdbarch_read_pc (gdbarch, d10v_read_pc);
1472 set_gdbarch_write_pc (gdbarch, d10v_write_pc);
1473 set_gdbarch_read_fp (gdbarch, d10v_read_fp);
1474 set_gdbarch_read_sp (gdbarch, d10v_read_sp);
1475 set_gdbarch_write_sp (gdbarch, d10v_write_sp);
1476
1477 set_gdbarch_num_regs (gdbarch, d10v_num_regs);
1478 set_gdbarch_sp_regnum (gdbarch, 15);
1479 set_gdbarch_fp_regnum (gdbarch, 11);
1480 set_gdbarch_pc_regnum (gdbarch, 18);
1481 set_gdbarch_register_name (gdbarch, d10v_register_name);
1482 set_gdbarch_register_size (gdbarch, 2);
1483 set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
1484 set_gdbarch_register_byte (gdbarch, d10v_register_byte);
1485 set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
1486 set_gdbarch_max_register_raw_size (gdbarch, 8);
1487 set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size);
1488 set_gdbarch_max_register_virtual_size (gdbarch, 8);
1489 set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
1490
1491 set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1492 set_gdbarch_addr_bit (gdbarch, 32);
1493 set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer);
1494 set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address);
1495 set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address);
1496 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1497 set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1498 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1499 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1500 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1501 double'' is 64 bits. */
1502 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1503 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1504 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1505 switch (info.byte_order)
1506 {
1507 case BFD_ENDIAN_BIG:
1508 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
1509 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big);
1510 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
1511 break;
1512 case BFD_ENDIAN_LITTLE:
1513 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
1514 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
1515 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
1516 break;
1517 default:
1518 internal_error (__FILE__, __LINE__,
1519 "d10v_gdbarch_init: bad byte order for float format");
1520 }
1521
1522 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1523 set_gdbarch_call_dummy_length (gdbarch, 0);
1524 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1525 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1526 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
1527 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1528 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1529 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1530 set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
1531 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
1532 set_gdbarch_call_dummy_p (gdbarch, 1);
1533 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1534 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1535 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1536
1537 set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
1538 set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
1539 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1540 set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
1541
1542 set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
1543 set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
1544 set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
1545 set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
1546
1547 set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
1548 set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
1549
1550 set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
1551
1552 set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
1553 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1554 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1555 set_gdbarch_function_start_offset (gdbarch, 0);
1556 set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
1557
1558 set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
1559
1560 set_gdbarch_frame_args_skip (gdbarch, 0);
1561 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1562 set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
1563 set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
1564 set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
1565 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
1566 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
1567 set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
1568 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1569 set_gdbarch_stack_align (gdbarch, d10v_stack_align);
1570
1571 set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno);
1572 set_gdbarch_extra_stack_alignment_needed (gdbarch, 0);
1573
1574 return gdbarch;
1575 }
1576
1577
1578 extern void (*target_resume_hook) (void);
1579 extern void (*target_wait_loop_hook) (void);
1580
1581 void
1582 _initialize_d10v_tdep (void)
1583 {
1584 register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
1585
1586 tm_print_insn = print_insn_d10v;
1587
1588 target_resume_hook = d10v_eva_prepare_to_trace;
1589 target_wait_loop_hook = d10v_eva_get_trace_data;
1590
1591 add_com ("regs", class_vars, show_regs, "Print all registers");
1592
1593 add_com ("itrace", class_support, trace_command,
1594 "Enable tracing of instruction execution.");
1595
1596 add_com ("iuntrace", class_support, untrace_command,
1597 "Disable tracing of instruction execution.");
1598
1599 add_com ("itdisassemble", class_vars, tdisassemble_command,
1600 "Disassemble the trace buffer.\n\
1601 Two optional arguments specify a range of trace buffer entries\n\
1602 as reported by info trace (NOT addresses!).");
1603
1604 add_info ("itrace", trace_info,
1605 "Display info about the trace data buffer.");
1606
1607 add_show_from_set (add_set_cmd ("itracedisplay", no_class,
1608 var_integer, (char *) &trace_display,
1609 "Set automatic display of trace.\n", &setlist),
1610 &showlist);
1611 add_show_from_set (add_set_cmd ("itracesource", no_class,
1612 var_integer, (char *) &default_trace_show_source,
1613 "Set display of source code with trace.\n", &setlist),
1614 &showlist);
1615
1616 }
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