1 /* Target-dependent code for Mitsubishi D10V, for GDB.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Contributed by Martin Hunt, hunt@cygnus.com */
31 #include "gdb_string.h"
38 #include "arch-utils.h"
41 #include "floatformat.h"
45 #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
47 struct frame_extra_info
58 unsigned long (*dmap_register
) (int nr
);
59 unsigned long (*imap_register
) (int nr
);
62 /* These are the addresses the D10V-EVA board maps data and
63 instruction memory to. */
65 #define DMEM_START 0x2000000
66 #define IMEM_START 0x1000000
67 #define STACK_START 0x0007ffe
69 /* d10v register names. */
79 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
80 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
82 /* d10v calling convention. */
84 #define ARG1_REGNUM R0_REGNUM
86 #define RET1_REGNUM R0_REGNUM
90 extern void _initialize_d10v_tdep (void);
92 static void d10v_eva_prepare_to_trace (void);
94 static void d10v_eva_get_trace_data (void);
96 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
99 static void d10v_frame_init_saved_regs (struct frame_info
*);
101 static void do_d10v_pop_frame (struct frame_info
*fi
);
104 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
106 return ((chain
) != 0 && (frame
) != 0 && (frame
)->pc
> IMEM_START
);
110 d10v_stack_align (CORE_ADDR len
)
112 return (len
+ 1) & ~1;
115 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
116 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
117 and TYPE is the type (which is known to be struct, union or array).
119 The d10v returns anything less than 8 bytes in size in
123 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
125 return (TYPE_LENGTH (type
) > 8);
129 static unsigned char *
130 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
132 static unsigned char breakpoint
[] =
133 {0x2f, 0x90, 0x5e, 0x00};
134 *lenptr
= sizeof (breakpoint
);
138 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
139 when the reg_nr isn't valid. */
143 TS2_IMAP0_REGNUM
= 32,
144 TS2_DMAP_REGNUM
= 34,
145 TS2_NR_DMAP_REGS
= 1,
150 d10v_ts2_register_name (int reg_nr
)
152 static char *register_names
[] =
154 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
155 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
156 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
157 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
158 "imap0", "imap1", "dmap", "a0", "a1"
162 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
164 return register_names
[reg_nr
];
169 TS3_IMAP0_REGNUM
= 36,
170 TS3_DMAP0_REGNUM
= 38,
171 TS3_NR_DMAP_REGS
= 4,
176 d10v_ts3_register_name (int reg_nr
)
178 static char *register_names
[] =
180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
182 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
183 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
187 "dmap0", "dmap1", "dmap2", "dmap3"
191 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
193 return register_names
[reg_nr
];
196 /* Access the DMAP/IMAP registers in a target independent way.
198 Divide the D10V's 64k data space into four 16k segments:
199 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
202 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
203 0x7fff) always map to the on-chip data RAM, and the fourth always
204 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
205 unified memory or instruction memory, under the control of the
206 single DMAP register.
208 On the TS3, there are four DMAP registers, each of which controls
209 one of the segments. */
212 d10v_ts2_dmap_register (int reg_nr
)
220 return read_register (TS2_DMAP_REGNUM
);
227 d10v_ts3_dmap_register (int reg_nr
)
229 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
233 d10v_dmap_register (int reg_nr
)
235 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
239 d10v_ts2_imap_register (int reg_nr
)
241 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
245 d10v_ts3_imap_register (int reg_nr
)
247 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
251 d10v_imap_register (int reg_nr
)
253 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
256 /* MAP GDB's internal register numbering (determined by the layout fo
257 the REGISTER_BYTE array) onto the simulator's register
261 d10v_ts2_register_sim_regno (int nr
)
263 if (nr
>= TS2_IMAP0_REGNUM
264 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
265 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
266 if (nr
== TS2_DMAP_REGNUM
)
267 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
268 if (nr
>= TS2_A0_REGNUM
269 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
270 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
275 d10v_ts3_register_sim_regno (int nr
)
277 if (nr
>= TS3_IMAP0_REGNUM
278 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
279 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
280 if (nr
>= TS3_DMAP0_REGNUM
281 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
282 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
283 if (nr
>= TS3_A0_REGNUM
284 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
285 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
289 /* Index within `registers' of the first byte of the space for
293 d10v_register_byte (int reg_nr
)
295 if (reg_nr
< A0_REGNUM
)
297 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
298 return (A0_REGNUM
* 2
299 + (reg_nr
- A0_REGNUM
) * 8);
301 return (A0_REGNUM
* 2
303 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
306 /* Number of bytes of storage in the actual machine representation for
310 d10v_register_raw_size (int reg_nr
)
312 if (reg_nr
< A0_REGNUM
)
314 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
320 /* Number of bytes of storage in the program's representation
324 d10v_register_virtual_size (int reg_nr
)
326 return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr
));
329 /* Return the GDB type object for the "standard" data type
330 of data in register N. */
333 d10v_register_virtual_type (int reg_nr
)
335 if (reg_nr
>= A0_REGNUM
336 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
337 return builtin_type_int64
;
338 else if (reg_nr
== PC_REGNUM
339 || reg_nr
== SP_REGNUM
)
340 return builtin_type_int32
;
342 return builtin_type_int16
;
345 /* convert $pc and $sp to/from virtual addresses */
347 d10v_register_convertible (int nr
)
349 return ((nr
) == PC_REGNUM
|| (nr
) == SP_REGNUM
);
353 d10v_register_convert_to_virtual (int regnum
, struct type
*type
, char *from
,
356 ULONGEST x
= extract_unsigned_integer (from
, REGISTER_RAW_SIZE (regnum
));
357 if (regnum
== PC_REGNUM
)
358 x
= (x
<< 2) | IMEM_START
;
361 store_unsigned_integer (to
, TYPE_LENGTH (type
), x
);
365 d10v_register_convert_to_raw (struct type
*type
, int regnum
, char *from
,
368 ULONGEST x
= extract_unsigned_integer (from
, TYPE_LENGTH (type
));
370 if (regnum
== PC_REGNUM
)
372 store_unsigned_integer (to
, 2, x
);
377 d10v_make_daddr (CORE_ADDR x
)
379 return ((x
) | DMEM_START
);
383 d10v_make_iaddr (CORE_ADDR x
)
385 return (((x
) << 2) | IMEM_START
);
389 d10v_daddr_p (CORE_ADDR x
)
391 return (((x
) & 0x3000000) == DMEM_START
);
395 d10v_iaddr_p (CORE_ADDR x
)
397 return (((x
) & 0x3000000) == IMEM_START
);
402 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
404 return (((x
) >> 2) & 0xffff);
408 d10v_convert_daddr_to_raw (CORE_ADDR x
)
410 return ((x
) & 0xffff);
413 /* Store the address of the place in which to copy the structure the
414 subroutine will return. This is called from call_function.
416 We store structs through a pointer passed in the first Argument
420 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
422 write_register (ARG1_REGNUM
, (addr
));
425 /* Write into appropriate registers a function return value
426 of type TYPE, given in virtual format.
428 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
431 d10v_store_return_value (struct type
*type
, char *valbuf
)
433 write_register_bytes (REGISTER_BYTE (RET1_REGNUM
),
438 /* Extract from an array REGBUF containing the (raw) register state
439 the address in which a function should return its structure value,
440 as a CORE_ADDR (or an expression that can be used as one). */
443 d10v_extract_struct_value_address (char *regbuf
)
445 return (extract_address ((regbuf
) + REGISTER_BYTE (ARG1_REGNUM
),
446 REGISTER_RAW_SIZE (ARG1_REGNUM
))
451 d10v_frame_saved_pc (struct frame_info
*frame
)
453 return ((frame
)->extra_info
->return_pc
);
456 /* Immediately after a function call, return the saved pc. We can't
457 use frame->return_pc beause that is determined by reading R13 off
458 the stack and that may not be written yet. */
461 d10v_saved_pc_after_call (struct frame_info
*frame
)
463 return ((read_register (LR_REGNUM
) << 2)
467 /* Discard from the stack the innermost frame, restoring all saved
471 d10v_pop_frame (void)
473 generic_pop_current_frame (do_d10v_pop_frame
);
477 do_d10v_pop_frame (struct frame_info
*fi
)
484 /* fill out fsr with the address of where each */
485 /* register was stored in the frame */
486 d10v_frame_init_saved_regs (fi
);
488 /* now update the current registers with the old values */
489 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
491 if (fi
->saved_regs
[regnum
])
493 read_memory (fi
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
494 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
, REGISTER_RAW_SIZE (regnum
));
497 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
499 if (fi
->saved_regs
[regnum
])
501 write_register (regnum
, read_memory_unsigned_integer (fi
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
504 if (fi
->saved_regs
[PSW_REGNUM
])
506 write_register (PSW_REGNUM
, read_memory_unsigned_integer (fi
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
509 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
510 write_register (SP_REGNUM
, fp
+ fi
->extra_info
->size
);
511 target_store_registers (-1);
512 flush_cached_frames ();
516 check_prologue (unsigned short op
)
519 if ((op
& 0x7E1F) == 0x6C1F)
523 if ((op
& 0x7E3F) == 0x6E1F)
527 if ((op
& 0x7FE1) == 0x01E1)
539 if ((op
& 0x7E1F) == 0x681E)
543 if ((op
& 0x7E3F) == 0x3A1E)
550 d10v_skip_prologue (CORE_ADDR pc
)
553 unsigned short op1
, op2
;
554 CORE_ADDR func_addr
, func_end
;
555 struct symtab_and_line sal
;
557 /* If we have line debugging information, then the end of the */
558 /* prologue should the first assembly instruction of the first source line */
559 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
561 sal
= find_pc_line (func_addr
, 0);
562 if (sal
.end
&& sal
.end
< func_end
)
566 if (target_read_memory (pc
, (char *) &op
, 4))
567 return pc
; /* Can't access it -- assume no prologue. */
571 op
= (unsigned long) read_memory_integer (pc
, 4);
572 if ((op
& 0xC0000000) == 0xC0000000)
574 /* long instruction */
575 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
576 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
577 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
582 /* short instructions */
583 if ((op
& 0xC0000000) == 0x80000000)
585 op2
= (op
& 0x3FFF8000) >> 15;
590 op1
= (op
& 0x3FFF8000) >> 15;
593 if (check_prologue (op1
))
595 if (!check_prologue (op2
))
597 /* if the previous opcode was really part of the prologue */
598 /* and not just a NOP, then we want to break after both instructions */
612 /* Given a GDB frame, determine the address of the calling function's frame.
613 This will be used to create a new GDB frame struct, and then
614 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
618 d10v_frame_chain (struct frame_info
*fi
)
620 d10v_frame_init_saved_regs (fi
);
622 if (fi
->extra_info
->return_pc
== IMEM_START
623 || inside_entry_file (fi
->extra_info
->return_pc
))
624 return (CORE_ADDR
) 0;
626 if (!fi
->saved_regs
[FP_REGNUM
])
628 if (!fi
->saved_regs
[SP_REGNUM
]
629 || fi
->saved_regs
[SP_REGNUM
] == STACK_START
)
630 return (CORE_ADDR
) 0;
632 return fi
->saved_regs
[SP_REGNUM
];
635 if (!read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
636 REGISTER_RAW_SIZE (FP_REGNUM
)))
637 return (CORE_ADDR
) 0;
639 return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
640 REGISTER_RAW_SIZE (FP_REGNUM
)));
643 static int next_addr
, uses_frame
;
646 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
651 if ((op
& 0x7E1F) == 0x6C1F)
653 n
= (op
& 0x1E0) >> 5;
655 fi
->saved_regs
[n
] = next_addr
;
660 else if ((op
& 0x7E3F) == 0x6E1F)
662 n
= (op
& 0x1E0) >> 5;
664 fi
->saved_regs
[n
] = next_addr
;
665 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
670 if ((op
& 0x7FE1) == 0x01E1)
672 n
= (op
& 0x1E) >> 1;
691 if ((op
& 0x7E1F) == 0x681E)
693 n
= (op
& 0x1E0) >> 5;
694 fi
->saved_regs
[n
] = next_addr
;
699 if ((op
& 0x7E3F) == 0x3A1E)
701 n
= (op
& 0x1E0) >> 5;
702 fi
->saved_regs
[n
] = next_addr
;
703 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
710 /* Put here the code to store, into fi->saved_regs, the addresses of
711 the saved registers of frame described by FRAME_INFO. This
712 includes special registers such as pc and fp saved in special ways
713 in the stack frame. sp is even more special: the address we return
714 for it IS the sp for the next frame. */
717 d10v_frame_init_saved_regs (struct frame_info
*fi
)
721 unsigned short op1
, op2
;
725 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
728 pc
= get_pc_function_start (fi
->pc
);
733 op
= (unsigned long) read_memory_integer (pc
, 4);
734 if ((op
& 0xC0000000) == 0xC0000000)
736 /* long instruction */
737 if ((op
& 0x3FFF0000) == 0x01FF0000)
740 short n
= op
& 0xFFFF;
743 else if ((op
& 0x3F0F0000) == 0x340F0000)
745 /* st rn, @(offset,sp) */
746 short offset
= op
& 0xFFFF;
747 short n
= (op
>> 20) & 0xF;
748 fi
->saved_regs
[n
] = next_addr
+ offset
;
750 else if ((op
& 0x3F1F0000) == 0x350F0000)
752 /* st2w rn, @(offset,sp) */
753 short offset
= op
& 0xFFFF;
754 short n
= (op
>> 20) & 0xF;
755 fi
->saved_regs
[n
] = next_addr
+ offset
;
756 fi
->saved_regs
[n
+ 1] = next_addr
+ offset
+ 2;
763 /* short instructions */
764 if ((op
& 0xC0000000) == 0x80000000)
766 op2
= (op
& 0x3FFF8000) >> 15;
771 op1
= (op
& 0x3FFF8000) >> 15;
774 if (!prologue_find_regs (op1
, fi
, pc
) || !prologue_find_regs (op2
, fi
, pc
))
780 fi
->extra_info
->size
= -next_addr
;
783 fp
= D10V_MAKE_DADDR (read_register (SP_REGNUM
));
785 for (i
= 0; i
< NUM_REGS
- 1; i
++)
786 if (fi
->saved_regs
[i
])
788 fi
->saved_regs
[i
] = fp
- (next_addr
- fi
->saved_regs
[i
]);
791 if (fi
->saved_regs
[LR_REGNUM
])
793 CORE_ADDR return_pc
= read_memory_unsigned_integer (fi
->saved_regs
[LR_REGNUM
], REGISTER_RAW_SIZE (LR_REGNUM
));
794 fi
->extra_info
->return_pc
= D10V_MAKE_IADDR (return_pc
);
798 fi
->extra_info
->return_pc
= D10V_MAKE_IADDR (read_register (LR_REGNUM
));
801 /* th SP is not normally (ever?) saved, but check anyway */
802 if (!fi
->saved_regs
[SP_REGNUM
])
804 /* if the FP was saved, that means the current FP is valid, */
805 /* otherwise, it isn't being used, so we use the SP instead */
807 fi
->saved_regs
[SP_REGNUM
] = read_register (FP_REGNUM
) + fi
->extra_info
->size
;
810 fi
->saved_regs
[SP_REGNUM
] = fp
+ fi
->extra_info
->size
;
811 fi
->extra_info
->frameless
= 1;
812 fi
->saved_regs
[FP_REGNUM
] = 0;
818 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
820 fi
->extra_info
= (struct frame_extra_info
*)
821 frame_obstack_alloc (sizeof (struct frame_extra_info
));
822 frame_saved_regs_zalloc (fi
);
824 fi
->extra_info
->frameless
= 0;
825 fi
->extra_info
->size
= 0;
826 fi
->extra_info
->return_pc
= 0;
828 /* The call dummy doesn't save any registers on the stack, so we can
830 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
836 d10v_frame_init_saved_regs (fi
);
841 show_regs (char *args
, int from_tty
)
844 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
845 (long) read_register (PC_REGNUM
),
846 (long) D10V_MAKE_IADDR (read_register (PC_REGNUM
)),
847 (long) read_register (PSW_REGNUM
),
848 (long) read_register (24),
849 (long) read_register (25),
850 (long) read_register (23));
851 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
852 (long) read_register (0),
853 (long) read_register (1),
854 (long) read_register (2),
855 (long) read_register (3),
856 (long) read_register (4),
857 (long) read_register (5),
858 (long) read_register (6),
859 (long) read_register (7));
860 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
861 (long) read_register (8),
862 (long) read_register (9),
863 (long) read_register (10),
864 (long) read_register (11),
865 (long) read_register (12),
866 (long) read_register (13),
867 (long) read_register (14),
868 (long) read_register (15));
869 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
872 printf_filtered (" ");
873 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
875 if (NR_DMAP_REGS
== 1)
876 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
879 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
881 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
883 printf_filtered ("\n");
885 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
886 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
888 char num
[MAX_REGISTER_RAW_SIZE
];
890 printf_filtered (" ");
891 read_register_gen (a
, (char *) &num
);
892 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
894 printf_filtered ("%02x", (num
[i
] & 0xff));
897 printf_filtered ("\n");
901 d10v_read_pc (ptid_t ptid
)
907 save_ptid
= inferior_ptid
;
908 inferior_ptid
= ptid
;
909 pc
= (int) read_register (PC_REGNUM
);
910 inferior_ptid
= save_ptid
;
911 retval
= D10V_MAKE_IADDR (pc
);
916 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
920 save_ptid
= inferior_ptid
;
921 inferior_ptid
= ptid
;
922 write_register (PC_REGNUM
, D10V_CONVERT_IADDR_TO_RAW (val
));
923 inferior_ptid
= save_ptid
;
929 return (D10V_MAKE_DADDR (read_register (SP_REGNUM
)));
933 d10v_write_sp (CORE_ADDR val
)
935 write_register (SP_REGNUM
, D10V_CONVERT_DADDR_TO_RAW (val
));
939 d10v_write_fp (CORE_ADDR val
)
941 write_register (FP_REGNUM
, D10V_CONVERT_DADDR_TO_RAW (val
));
947 return (D10V_MAKE_DADDR (read_register (FP_REGNUM
)));
950 /* Function: push_return_address (pc)
951 Set up the return address for the inferior function call.
952 Needed for targets where we don't actually execute a JSR/BSR instruction */
955 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
957 write_register (LR_REGNUM
, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ()));
962 /* When arguments must be pushed onto the stack, they go on in reverse
963 order. The below implements a FILO (stack) to do this. */
968 struct stack_item
*prev
;
972 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
973 void *contents
, int len
);
974 static struct stack_item
*
975 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
977 struct stack_item
*si
;
978 si
= xmalloc (sizeof (struct stack_item
));
979 si
->data
= xmalloc (len
);
982 memcpy (si
->data
, contents
, len
);
986 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
987 static struct stack_item
*
988 pop_stack_item (struct stack_item
*si
)
990 struct stack_item
*dead
= si
;
999 d10v_push_arguments (int nargs
, value_ptr
*args
, CORE_ADDR sp
,
1000 int struct_return
, CORE_ADDR struct_addr
)
1003 int regnum
= ARG1_REGNUM
;
1004 struct stack_item
*si
= NULL
;
1006 /* Fill in registers and arg lists */
1007 for (i
= 0; i
< nargs
; i
++)
1009 value_ptr arg
= args
[i
];
1010 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1011 char *contents
= VALUE_CONTENTS (arg
);
1012 int len
= TYPE_LENGTH (type
);
1013 /* printf ("push: type=%d len=%d\n", type->code, len); */
1014 if (TYPE_CODE (type
) == TYPE_CODE_PTR
)
1016 /* pointers require special handling - first convert and
1018 long val
= extract_signed_integer (contents
, len
);
1020 if (TYPE_TARGET_TYPE (type
)
1021 && (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
))
1023 /* function pointer */
1024 val
= D10V_CONVERT_IADDR_TO_RAW (val
);
1026 else if (D10V_IADDR_P (val
))
1028 /* also function pointer! */
1029 val
= D10V_CONVERT_DADDR_TO_RAW (val
);
1036 if (regnum
<= ARGN_REGNUM
)
1037 write_register (regnum
++, val
& 0xffff);
1041 /* arg will go onto stack */
1042 store_address (ptr
, 2, val
& 0xffff);
1043 si
= push_stack_item (si
, ptr
, 2);
1048 int aligned_regnum
= (regnum
+ 1) & ~1;
1049 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1050 /* fits in a single register, do not align */
1052 long val
= extract_unsigned_integer (contents
, len
);
1053 write_register (regnum
++, val
);
1055 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1056 /* value fits in remaining registers, store keeping left
1060 regnum
= aligned_regnum
;
1061 for (b
= 0; b
< (len
& ~1); b
+= 2)
1063 long val
= extract_unsigned_integer (&contents
[b
], 2);
1064 write_register (regnum
++, val
);
1068 long val
= extract_unsigned_integer (&contents
[b
], 1);
1069 write_register (regnum
++, (val
<< 8));
1074 /* arg will go onto stack */
1075 regnum
= ARGN_REGNUM
+ 1;
1076 si
= push_stack_item (si
, contents
, len
);
1083 sp
= (sp
- si
->len
) & ~1;
1084 write_memory (sp
, si
->data
, si
->len
);
1085 si
= pop_stack_item (si
);
1092 /* Given a return value in `regbuf' with a type `valtype',
1093 extract and copy its value into `valbuf'. */
1096 d10v_extract_return_value (struct type
*type
, char regbuf
[REGISTER_BYTES
],
1100 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1101 if (TYPE_CODE (type
) == TYPE_CODE_PTR
1102 && TYPE_TARGET_TYPE (type
)
1103 && (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
))
1105 /* pointer to function */
1108 snum
= extract_address (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1109 store_address (valbuf
, 4, D10V_MAKE_IADDR (snum
));
1111 else if (TYPE_CODE (type
) == TYPE_CODE_PTR
)
1113 /* pointer to data */
1116 snum
= extract_address (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1117 store_address (valbuf
, 4, D10V_MAKE_DADDR (snum
));
1121 len
= TYPE_LENGTH (type
);
1124 unsigned short c
= extract_unsigned_integer (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1125 store_unsigned_integer (valbuf
, 1, c
);
1127 else if ((len
& 1) == 0)
1128 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
), len
);
1131 /* For return values of odd size, the first byte is in the
1132 least significant part of the first register. The
1133 remaining bytes in remaining registers. Interestingly,
1134 when such values are passed in, the last byte is in the
1135 most significant byte of that same register - wierd. */
1136 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
) + 1, len
);
1141 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1142 understands. Returns number of bytes that can be transfered
1143 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1144 (segmentation fault). Since the simulator knows all about how the
1145 VM system works, we just call that to do the translation. */
1148 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1149 CORE_ADDR
*targ_addr
, int *targ_len
)
1153 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1156 d10v_imap_register
);
1157 *targ_addr
= out_addr
;
1158 *targ_len
= out_len
;
1162 /* The following code implements access to, and display of, the D10V's
1163 instruction trace buffer. The buffer consists of 64K or more
1164 4-byte words of data, of which each words includes an 8-bit count,
1165 an 8-bit segment number, and a 16-bit instruction address.
1167 In theory, the trace buffer is continuously capturing instruction
1168 data that the CPU presents on its "debug bus", but in practice, the
1169 ROMified GDB stub only enables tracing when it continues or steps
1170 the program, and stops tracing when the program stops; so it
1171 actually works for GDB to read the buffer counter out of memory and
1172 then read each trace word. The counter records where the tracing
1173 stops, but there is no record of where it started, so we remember
1174 the PC when we resumed and then search backwards in the trace
1175 buffer for a word that includes that address. This is not perfect,
1176 because you will miss trace data if the resumption PC is the target
1177 of a branch. (The value of the buffer counter is semi-random, any
1178 trace data from a previous program stop is gone.) */
1180 /* The address of the last word recorded in the trace buffer. */
1182 #define DBBC_ADDR (0xd80000)
1184 /* The base of the trace buffer, at least for the "Board_0". */
1186 #define TRACE_BUFFER_BASE (0xf40000)
1188 static void trace_command (char *, int);
1190 static void untrace_command (char *, int);
1192 static void trace_info (char *, int);
1194 static void tdisassemble_command (char *, int);
1196 static void display_trace (int, int);
1198 /* True when instruction traces are being collected. */
1202 /* Remembered PC. */
1204 static CORE_ADDR last_pc
;
1206 /* True when trace output should be displayed whenever program stops. */
1208 static int trace_display
;
1210 /* True when trace listing should include source lines. */
1212 static int default_trace_show_source
= 1;
1223 trace_command (char *args
, int from_tty
)
1225 /* Clear the host-side trace buffer, allocating space if needed. */
1226 trace_data
.size
= 0;
1227 if (trace_data
.counts
== NULL
)
1228 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1229 if (trace_data
.addrs
== NULL
)
1230 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1234 printf_filtered ("Tracing is now on.\n");
1238 untrace_command (char *args
, int from_tty
)
1242 printf_filtered ("Tracing is now off.\n");
1246 trace_info (char *args
, int from_tty
)
1250 if (trace_data
.size
)
1252 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1254 for (i
= 0; i
< trace_data
.size
; ++i
)
1256 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1258 trace_data
.counts
[i
],
1259 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1260 paddr_nz (trace_data
.addrs
[i
]));
1264 printf_filtered ("No entries in trace buffer.\n");
1266 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1269 /* Print the instruction at address MEMADDR in debugged memory,
1270 on STREAM. Returns length of the instruction, in bytes. */
1273 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1275 /* If there's no disassembler, something is very wrong. */
1276 if (tm_print_insn
== NULL
)
1277 internal_error (__FILE__
, __LINE__
,
1278 "print_insn: no disassembler");
1280 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1281 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1283 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1284 return (*tm_print_insn
) (memaddr
, &tm_print_insn_info
);
1288 d10v_eva_prepare_to_trace (void)
1293 last_pc
= read_register (PC_REGNUM
);
1296 /* Collect trace data from the target board and format it into a form
1297 more useful for display. */
1300 d10v_eva_get_trace_data (void)
1302 int count
, i
, j
, oldsize
;
1303 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1304 unsigned int last_trace
, trace_word
, next_word
;
1305 unsigned int *tmpspace
;
1310 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1312 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1314 /* Collect buffer contents from the target, stopping when we reach
1315 the word recorded when execution resumed. */
1318 while (last_trace
> 0)
1322 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1323 trace_addr
= trace_word
& 0xffff;
1325 /* Ignore an apparently nonsensical entry. */
1326 if (trace_addr
== 0xffd5)
1328 tmpspace
[count
++] = trace_word
;
1329 if (trace_addr
== last_pc
)
1335 /* Move the data to the host-side trace buffer, adjusting counts to
1336 include the last instruction executed and transforming the address
1337 into something that GDB likes. */
1339 for (i
= 0; i
< count
; ++i
)
1341 trace_word
= tmpspace
[i
];
1342 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1343 trace_addr
= trace_word
& 0xffff;
1344 next_cnt
= (next_word
>> 24) & 0xff;
1345 j
= trace_data
.size
+ count
- i
- 1;
1346 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1347 trace_data
.counts
[j
] = next_cnt
+ 1;
1350 oldsize
= trace_data
.size
;
1351 trace_data
.size
+= count
;
1356 display_trace (oldsize
, trace_data
.size
);
1360 tdisassemble_command (char *arg
, int from_tty
)
1363 CORE_ADDR low
, high
;
1369 high
= trace_data
.size
;
1371 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1373 low
= parse_and_eval_address (arg
);
1378 /* Two arguments. */
1379 *space_index
= '\0';
1380 low
= parse_and_eval_address (arg
);
1381 high
= parse_and_eval_address (space_index
+ 1);
1386 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1388 display_trace (low
, high
);
1390 printf_filtered ("End of trace dump.\n");
1391 gdb_flush (gdb_stdout
);
1395 display_trace (int low
, int high
)
1397 int i
, count
, trace_show_source
, first
, suppress
;
1398 CORE_ADDR next_address
;
1400 trace_show_source
= default_trace_show_source
;
1401 if (!have_full_symbols () && !have_partial_symbols ())
1403 trace_show_source
= 0;
1404 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1405 printf_filtered ("Trace will not display any source.\n");
1410 for (i
= low
; i
< high
; ++i
)
1412 next_address
= trace_data
.addrs
[i
];
1413 count
= trace_data
.counts
[i
];
1417 if (trace_show_source
)
1419 struct symtab_and_line sal
, sal_prev
;
1421 sal_prev
= find_pc_line (next_address
- 4, 0);
1422 sal
= find_pc_line (next_address
, 0);
1426 if (first
|| sal
.line
!= sal_prev
.line
)
1427 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1433 /* FIXME-32x64--assumes sal.pc fits in long. */
1434 printf_filtered ("No source file for address %s.\n",
1435 local_hex_string ((unsigned long) sal
.pc
));
1440 print_address (next_address
, gdb_stdout
);
1441 printf_filtered (":");
1442 printf_filtered ("\t");
1444 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1445 printf_filtered ("\n");
1446 gdb_flush (gdb_stdout
);
1452 static gdbarch_init_ftype d10v_gdbarch_init
;
1454 static struct gdbarch
*
1455 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1457 static LONGEST d10v_call_dummy_words
[] =
1459 struct gdbarch
*gdbarch
;
1461 struct gdbarch_tdep
*tdep
;
1462 gdbarch_register_name_ftype
*d10v_register_name
;
1463 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1465 /* Find a candidate among the list of pre-declared architectures. */
1466 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1468 return arches
->gdbarch
;
1470 /* None found, create a new architecture from the information
1472 tdep
= XMALLOC (struct gdbarch_tdep
);
1473 gdbarch
= gdbarch_alloc (&info
, tdep
);
1475 switch (info
.bfd_arch_info
->mach
)
1477 case bfd_mach_d10v_ts2
:
1479 d10v_register_name
= d10v_ts2_register_name
;
1480 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1481 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1482 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1483 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1484 tdep
->imap_register
= d10v_ts2_imap_register
;
1487 case bfd_mach_d10v_ts3
:
1489 d10v_register_name
= d10v_ts3_register_name
;
1490 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1491 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1492 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1493 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1494 tdep
->imap_register
= d10v_ts3_imap_register
;
1498 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1499 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1500 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1501 set_gdbarch_write_fp (gdbarch
, d10v_write_fp
);
1502 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1503 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1505 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1506 set_gdbarch_sp_regnum (gdbarch
, 15);
1507 set_gdbarch_fp_regnum (gdbarch
, 11);
1508 set_gdbarch_pc_regnum (gdbarch
, 18);
1509 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1510 set_gdbarch_register_size (gdbarch
, 2);
1511 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1512 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1513 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1514 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1515 set_gdbarch_register_virtual_size (gdbarch
, d10v_register_virtual_size
);
1516 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1517 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1519 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1520 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1521 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1522 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1523 set_gdbarch_long_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1524 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1525 double'' is 64 bits. */
1526 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1527 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1528 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1529 switch (info
.byte_order
)
1532 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1533 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1534 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1537 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1538 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1539 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1542 internal_error (__FILE__
, __LINE__
,
1543 "d10v_gdbarch_init: bad byte order for float format");
1546 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
1547 set_gdbarch_call_dummy_length (gdbarch
, 0);
1548 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
1549 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1550 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1551 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1552 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1553 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
1554 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1555 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1556 set_gdbarch_call_dummy_p (gdbarch
, 1);
1557 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1558 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
1559 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1561 set_gdbarch_register_convertible (gdbarch
, d10v_register_convertible
);
1562 set_gdbarch_register_convert_to_virtual (gdbarch
, d10v_register_convert_to_virtual
);
1563 set_gdbarch_register_convert_to_raw (gdbarch
, d10v_register_convert_to_raw
);
1565 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1566 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1567 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1568 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1570 set_gdbarch_d10v_make_daddr (gdbarch
, d10v_make_daddr
);
1571 set_gdbarch_d10v_make_iaddr (gdbarch
, d10v_make_iaddr
);
1572 set_gdbarch_d10v_daddr_p (gdbarch
, d10v_daddr_p
);
1573 set_gdbarch_d10v_iaddr_p (gdbarch
, d10v_iaddr_p
);
1574 set_gdbarch_d10v_convert_daddr_to_raw (gdbarch
, d10v_convert_daddr_to_raw
);
1575 set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch
, d10v_convert_iaddr_to_raw
);
1577 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1578 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1579 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1580 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1582 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1583 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1585 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1587 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1588 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1589 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1590 set_gdbarch_function_start_offset (gdbarch
, 0);
1591 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1593 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1595 set_gdbarch_frame_args_skip (gdbarch
, 0);
1596 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1597 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1598 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1599 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1600 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
1601 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
1602 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1603 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1604 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1606 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1607 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1613 extern void (*target_resume_hook
) (void);
1614 extern void (*target_wait_loop_hook
) (void);
1617 _initialize_d10v_tdep (void)
1619 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1621 tm_print_insn
= print_insn_d10v
;
1623 target_resume_hook
= d10v_eva_prepare_to_trace
;
1624 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1626 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1628 add_com ("itrace", class_support
, trace_command
,
1629 "Enable tracing of instruction execution.");
1631 add_com ("iuntrace", class_support
, untrace_command
,
1632 "Disable tracing of instruction execution.");
1634 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1635 "Disassemble the trace buffer.\n\
1636 Two optional arguments specify a range of trace buffer entries\n\
1637 as reported by info trace (NOT addresses!).");
1639 add_info ("itrace", trace_info
,
1640 "Display info about the trace data buffer.");
1642 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1643 var_integer
, (char *) &trace_display
,
1644 "Set automatic display of trace.\n", &setlist
),
1646 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1647 var_integer
, (char *) &default_trace_show_source
,
1648 "Set display of source code with trace.\n", &setlist
),