1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
32 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "floatformat.h"
45 struct frame_extra_info
56 unsigned long (*dmap_register
) (int nr
);
57 unsigned long (*imap_register
) (int nr
);
60 /* These are the addresses the D10V-EVA board maps data and
61 instruction memory to. */
64 DMEM_START
= 0x2000000,
65 IMEM_START
= 0x1000000,
66 STACK_START
= 0x200bffe
69 /* d10v register names. */
84 /* d10v calling convention. */
85 ARG1_REGNUM
= R0_REGNUM
,
86 ARGN_REGNUM
= R3_REGNUM
,
87 RET1_REGNUM
= R0_REGNUM
,
90 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
91 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
95 extern void _initialize_d10v_tdep (void);
97 static void d10v_eva_prepare_to_trace (void);
99 static void d10v_eva_get_trace_data (void);
101 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
104 static void d10v_frame_init_saved_regs (struct frame_info
*);
106 static void do_d10v_pop_frame (struct frame_info
*fi
);
109 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
111 if (chain
!= 0 && frame
!= NULL
)
113 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
114 return 1; /* Path back from a call dummy must be valid. */
115 return ((frame
)->pc
> IMEM_START
116 && !inside_main_func (frame
->pc
));
122 d10v_stack_align (CORE_ADDR len
)
124 return (len
+ 1) & ~1;
127 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
128 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
129 and TYPE is the type (which is known to be struct, union or array).
131 The d10v returns anything less than 8 bytes in size in
135 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
139 /* The d10v only passes a struct in a register when that structure
140 has an alignment that matches the size of a register. */
141 /* If the structure doesn't fit in 4 registers, put it on the
143 if (TYPE_LENGTH (type
) > 8)
145 /* If the struct contains only one field, don't put it on the stack
146 - gcc can fit it in one or more registers. */
147 if (TYPE_NFIELDS (type
) == 1)
149 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
150 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
152 /* If the alignment changes, just assume it goes on the
154 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
157 /* If the alignment is suitable for the d10v's 16 bit registers,
158 don't put it on the stack. */
159 if (alignment
== 2 || alignment
== 4)
165 static const unsigned char *
166 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
168 static unsigned char breakpoint
[] =
169 {0x2f, 0x90, 0x5e, 0x00};
170 *lenptr
= sizeof (breakpoint
);
174 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
175 when the reg_nr isn't valid. */
179 TS2_IMAP0_REGNUM
= 32,
180 TS2_DMAP_REGNUM
= 34,
181 TS2_NR_DMAP_REGS
= 1,
186 d10v_ts2_register_name (int reg_nr
)
188 static char *register_names
[] =
190 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
191 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
192 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
193 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
194 "imap0", "imap1", "dmap", "a0", "a1"
198 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
200 return register_names
[reg_nr
];
205 TS3_IMAP0_REGNUM
= 36,
206 TS3_DMAP0_REGNUM
= 38,
207 TS3_NR_DMAP_REGS
= 4,
212 d10v_ts3_register_name (int reg_nr
)
214 static char *register_names
[] =
216 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
217 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
218 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
219 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
223 "dmap0", "dmap1", "dmap2", "dmap3"
227 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
229 return register_names
[reg_nr
];
232 /* Access the DMAP/IMAP registers in a target independent way.
234 Divide the D10V's 64k data space into four 16k segments:
235 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
238 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
239 0x7fff) always map to the on-chip data RAM, and the fourth always
240 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
241 unified memory or instruction memory, under the control of the
242 single DMAP register.
244 On the TS3, there are four DMAP registers, each of which controls
245 one of the segments. */
248 d10v_ts2_dmap_register (int reg_nr
)
256 return read_register (TS2_DMAP_REGNUM
);
263 d10v_ts3_dmap_register (int reg_nr
)
265 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
269 d10v_dmap_register (int reg_nr
)
271 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
275 d10v_ts2_imap_register (int reg_nr
)
277 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
281 d10v_ts3_imap_register (int reg_nr
)
283 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
287 d10v_imap_register (int reg_nr
)
289 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
292 /* MAP GDB's internal register numbering (determined by the layout fo
293 the REGISTER_BYTE array) onto the simulator's register
297 d10v_ts2_register_sim_regno (int nr
)
299 if (nr
>= TS2_IMAP0_REGNUM
300 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
301 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
302 if (nr
== TS2_DMAP_REGNUM
)
303 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
304 if (nr
>= TS2_A0_REGNUM
305 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
306 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
311 d10v_ts3_register_sim_regno (int nr
)
313 if (nr
>= TS3_IMAP0_REGNUM
314 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
315 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
316 if (nr
>= TS3_DMAP0_REGNUM
317 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
318 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
319 if (nr
>= TS3_A0_REGNUM
320 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
321 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
325 /* Index within `registers' of the first byte of the space for
329 d10v_register_byte (int reg_nr
)
331 if (reg_nr
< A0_REGNUM
)
333 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
334 return (A0_REGNUM
* 2
335 + (reg_nr
- A0_REGNUM
) * 8);
337 return (A0_REGNUM
* 2
339 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
342 /* Number of bytes of storage in the actual machine representation for
346 d10v_register_raw_size (int reg_nr
)
348 if (reg_nr
< A0_REGNUM
)
350 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
356 /* Return the GDB type object for the "standard" data type
357 of data in register N. */
360 d10v_register_virtual_type (int reg_nr
)
362 if (reg_nr
== PC_REGNUM
)
363 return builtin_type_void_func_ptr
;
364 else if (reg_nr
>= A0_REGNUM
365 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
366 return builtin_type_int64
;
368 return builtin_type_int16
;
372 d10v_daddr_p (CORE_ADDR x
)
374 return (((x
) & 0x3000000) == DMEM_START
);
378 d10v_iaddr_p (CORE_ADDR x
)
380 return (((x
) & 0x3000000) == IMEM_START
);
384 d10v_make_daddr (CORE_ADDR x
)
386 return ((x
) | DMEM_START
);
390 d10v_make_iaddr (CORE_ADDR x
)
392 if (d10v_iaddr_p (x
))
393 return x
; /* Idempotency -- x is already in the IMEM space. */
395 return (((x
) << 2) | IMEM_START
);
399 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
401 return (((x
) >> 2) & 0xffff);
405 d10v_convert_daddr_to_raw (CORE_ADDR x
)
407 return ((x
) & 0xffff);
411 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
413 /* Is it a code address? */
414 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
415 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
417 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
418 d10v_convert_iaddr_to_raw (addr
));
422 /* Strip off any upper segment bits. */
423 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
424 d10v_convert_daddr_to_raw (addr
));
429 d10v_pointer_to_address (struct type
*type
, void *buf
)
431 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
433 /* Is it a code address? */
434 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
435 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
436 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
437 return d10v_make_iaddr (addr
);
439 return d10v_make_daddr (addr
);
443 d10v_integer_to_address (struct type
*type
, void *buf
)
446 val
= unpack_long (type
, buf
);
447 if (TYPE_CODE (type
) == TYPE_CODE_INT
448 && TYPE_LENGTH (type
) <= TYPE_LENGTH (builtin_type_void_data_ptr
))
449 /* Convert small integers that would would be directly copied into
450 a pointer variable into an address pointing into data space. */
451 return d10v_make_daddr (val
& 0xffff);
453 /* The value is too large to fit in a pointer. Assume this was
454 intentional and that the user in fact specified a raw address. */
458 /* Store the address of the place in which to copy the structure the
459 subroutine will return. This is called from call_function.
461 We store structs through a pointer passed in the first Argument
465 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
467 write_register (ARG1_REGNUM
, (addr
));
470 /* Write into appropriate registers a function return value
471 of type TYPE, given in virtual format.
473 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
476 d10v_store_return_value (struct type
*type
, char *valbuf
)
478 write_register_bytes (REGISTER_BYTE (RET1_REGNUM
),
483 /* Extract from an array REGBUF containing the (raw) register state
484 the address in which a function should return its structure value,
485 as a CORE_ADDR (or an expression that can be used as one). */
488 d10v_extract_struct_value_address (char *regbuf
)
490 return (extract_address ((regbuf
) + REGISTER_BYTE (ARG1_REGNUM
),
491 REGISTER_RAW_SIZE (ARG1_REGNUM
))
496 d10v_frame_saved_pc (struct frame_info
*frame
)
498 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
499 return d10v_make_iaddr (generic_read_register_dummy (frame
->pc
,
503 return ((frame
)->extra_info
->return_pc
);
506 /* Immediately after a function call, return the saved pc. We can't
507 use frame->return_pc beause that is determined by reading R13 off
508 the stack and that may not be written yet. */
511 d10v_saved_pc_after_call (struct frame_info
*frame
)
513 return ((read_register (LR_REGNUM
) << 2)
517 /* Discard from the stack the innermost frame, restoring all saved
521 d10v_pop_frame (void)
523 generic_pop_current_frame (do_d10v_pop_frame
);
527 do_d10v_pop_frame (struct frame_info
*fi
)
534 /* fill out fsr with the address of where each */
535 /* register was stored in the frame */
536 d10v_frame_init_saved_regs (fi
);
538 /* now update the current registers with the old values */
539 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
541 if (fi
->saved_regs
[regnum
])
543 read_memory (fi
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
544 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
, REGISTER_RAW_SIZE (regnum
));
547 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
549 if (fi
->saved_regs
[regnum
])
551 write_register (regnum
, read_memory_unsigned_integer (fi
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
554 if (fi
->saved_regs
[PSW_REGNUM
])
556 write_register (PSW_REGNUM
, read_memory_unsigned_integer (fi
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
559 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
560 write_register (SP_REGNUM
, fp
+ fi
->extra_info
->size
);
561 target_store_registers (-1);
562 flush_cached_frames ();
566 check_prologue (unsigned short op
)
569 if ((op
& 0x7E1F) == 0x6C1F)
573 if ((op
& 0x7E3F) == 0x6E1F)
577 if ((op
& 0x7FE1) == 0x01E1)
589 if ((op
& 0x7E1F) == 0x681E)
593 if ((op
& 0x7E3F) == 0x3A1E)
600 d10v_skip_prologue (CORE_ADDR pc
)
603 unsigned short op1
, op2
;
604 CORE_ADDR func_addr
, func_end
;
605 struct symtab_and_line sal
;
607 /* If we have line debugging information, then the end of the */
608 /* prologue should the first assembly instruction of the first source line */
609 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
611 sal
= find_pc_line (func_addr
, 0);
612 if (sal
.end
&& sal
.end
< func_end
)
616 if (target_read_memory (pc
, (char *) &op
, 4))
617 return pc
; /* Can't access it -- assume no prologue. */
621 op
= (unsigned long) read_memory_integer (pc
, 4);
622 if ((op
& 0xC0000000) == 0xC0000000)
624 /* long instruction */
625 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
626 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
627 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
632 /* short instructions */
633 if ((op
& 0xC0000000) == 0x80000000)
635 op2
= (op
& 0x3FFF8000) >> 15;
640 op1
= (op
& 0x3FFF8000) >> 15;
643 if (check_prologue (op1
))
645 if (!check_prologue (op2
))
647 /* if the previous opcode was really part of the prologue */
648 /* and not just a NOP, then we want to break after both instructions */
662 /* Given a GDB frame, determine the address of the calling function's frame.
663 This will be used to create a new GDB frame struct, and then
664 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
668 d10v_frame_chain (struct frame_info
*fi
)
672 /* A generic call dummy's frame is the same as caller's. */
673 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
676 d10v_frame_init_saved_regs (fi
);
679 if (fi
->extra_info
->return_pc
== IMEM_START
680 || inside_entry_file (fi
->extra_info
->return_pc
))
682 /* This is meant to halt the backtrace at "_start".
683 Make sure we don't halt it at a generic dummy frame. */
684 if (!PC_IN_CALL_DUMMY (fi
->extra_info
->return_pc
, 0, 0))
685 return (CORE_ADDR
) 0;
688 if (!fi
->saved_regs
[FP_REGNUM
])
690 if (!fi
->saved_regs
[SP_REGNUM
]
691 || fi
->saved_regs
[SP_REGNUM
] == STACK_START
)
692 return (CORE_ADDR
) 0;
694 return fi
->saved_regs
[SP_REGNUM
];
697 addr
= read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
698 REGISTER_RAW_SIZE (FP_REGNUM
));
700 return (CORE_ADDR
) 0;
702 return d10v_make_daddr (addr
);
705 static int next_addr
, uses_frame
;
708 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
713 if ((op
& 0x7E1F) == 0x6C1F)
715 n
= (op
& 0x1E0) >> 5;
717 fi
->saved_regs
[n
] = next_addr
;
722 else if ((op
& 0x7E3F) == 0x6E1F)
724 n
= (op
& 0x1E0) >> 5;
726 fi
->saved_regs
[n
] = next_addr
;
727 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
732 if ((op
& 0x7FE1) == 0x01E1)
734 n
= (op
& 0x1E) >> 1;
753 if ((op
& 0x7E1F) == 0x681E)
755 n
= (op
& 0x1E0) >> 5;
756 fi
->saved_regs
[n
] = next_addr
;
761 if ((op
& 0x7E3F) == 0x3A1E)
763 n
= (op
& 0x1E0) >> 5;
764 fi
->saved_regs
[n
] = next_addr
;
765 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
772 /* Put here the code to store, into fi->saved_regs, the addresses of
773 the saved registers of frame described by FRAME_INFO. This
774 includes special registers such as pc and fp saved in special ways
775 in the stack frame. sp is even more special: the address we return
776 for it IS the sp for the next frame. */
779 d10v_frame_init_saved_regs (struct frame_info
*fi
)
783 unsigned short op1
, op2
;
787 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
790 pc
= get_pc_function_start (fi
->pc
);
795 op
= (unsigned long) read_memory_integer (pc
, 4);
796 if ((op
& 0xC0000000) == 0xC0000000)
798 /* long instruction */
799 if ((op
& 0x3FFF0000) == 0x01FF0000)
802 short n
= op
& 0xFFFF;
805 else if ((op
& 0x3F0F0000) == 0x340F0000)
807 /* st rn, @(offset,sp) */
808 short offset
= op
& 0xFFFF;
809 short n
= (op
>> 20) & 0xF;
810 fi
->saved_regs
[n
] = next_addr
+ offset
;
812 else if ((op
& 0x3F1F0000) == 0x350F0000)
814 /* st2w rn, @(offset,sp) */
815 short offset
= op
& 0xFFFF;
816 short n
= (op
>> 20) & 0xF;
817 fi
->saved_regs
[n
] = next_addr
+ offset
;
818 fi
->saved_regs
[n
+ 1] = next_addr
+ offset
+ 2;
825 /* short instructions */
826 if ((op
& 0xC0000000) == 0x80000000)
828 op2
= (op
& 0x3FFF8000) >> 15;
833 op1
= (op
& 0x3FFF8000) >> 15;
836 if (!prologue_find_regs (op1
, fi
, pc
)
837 || !prologue_find_regs (op2
, fi
, pc
))
843 fi
->extra_info
->size
= -next_addr
;
846 fp
= d10v_make_daddr (read_register (SP_REGNUM
));
848 for (i
= 0; i
< NUM_REGS
- 1; i
++)
849 if (fi
->saved_regs
[i
])
851 fi
->saved_regs
[i
] = fp
- (next_addr
- fi
->saved_regs
[i
]);
854 if (fi
->saved_regs
[LR_REGNUM
])
857 = read_memory_unsigned_integer (fi
->saved_regs
[LR_REGNUM
],
858 REGISTER_RAW_SIZE (LR_REGNUM
));
859 fi
->extra_info
->return_pc
= d10v_make_iaddr (return_pc
);
863 fi
->extra_info
->return_pc
= d10v_make_iaddr (read_register (LR_REGNUM
));
866 /* The SP is not normally (ever?) saved, but check anyway */
867 if (!fi
->saved_regs
[SP_REGNUM
])
869 /* if the FP was saved, that means the current FP is valid, */
870 /* otherwise, it isn't being used, so we use the SP instead */
872 fi
->saved_regs
[SP_REGNUM
]
873 = read_register (FP_REGNUM
) + fi
->extra_info
->size
;
876 fi
->saved_regs
[SP_REGNUM
] = fp
+ fi
->extra_info
->size
;
877 fi
->extra_info
->frameless
= 1;
878 fi
->saved_regs
[FP_REGNUM
] = 0;
884 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
886 fi
->extra_info
= (struct frame_extra_info
*)
887 frame_obstack_alloc (sizeof (struct frame_extra_info
));
888 frame_saved_regs_zalloc (fi
);
890 fi
->extra_info
->frameless
= 0;
891 fi
->extra_info
->size
= 0;
892 fi
->extra_info
->return_pc
= 0;
894 /* If fi->pc is zero, but this is not the outermost frame,
895 then let's snatch the return_pc from the callee, so that
896 PC_IN_CALL_DUMMY will work. */
897 if (fi
->pc
== 0 && fi
->level
!= 0 && fi
->next
!= NULL
)
898 fi
->pc
= d10v_frame_saved_pc (fi
->next
);
900 /* The call dummy doesn't save any registers on the stack, so we can
902 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
908 d10v_frame_init_saved_regs (fi
);
913 show_regs (char *args
, int from_tty
)
916 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
917 (long) read_register (PC_REGNUM
),
918 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
919 (long) read_register (PSW_REGNUM
),
920 (long) read_register (24),
921 (long) read_register (25),
922 (long) read_register (23));
923 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
924 (long) read_register (0),
925 (long) read_register (1),
926 (long) read_register (2),
927 (long) read_register (3),
928 (long) read_register (4),
929 (long) read_register (5),
930 (long) read_register (6),
931 (long) read_register (7));
932 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
933 (long) read_register (8),
934 (long) read_register (9),
935 (long) read_register (10),
936 (long) read_register (11),
937 (long) read_register (12),
938 (long) read_register (13),
939 (long) read_register (14),
940 (long) read_register (15));
941 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
944 printf_filtered (" ");
945 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
947 if (NR_DMAP_REGS
== 1)
948 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
951 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
953 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
955 printf_filtered ("\n");
957 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
958 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
960 char num
[MAX_REGISTER_RAW_SIZE
];
962 printf_filtered (" ");
963 read_register_gen (a
, (char *) &num
);
964 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
966 printf_filtered ("%02x", (num
[i
] & 0xff));
969 printf_filtered ("\n");
973 d10v_read_pc (ptid_t ptid
)
979 save_ptid
= inferior_ptid
;
980 inferior_ptid
= ptid
;
981 pc
= (int) read_register (PC_REGNUM
);
982 inferior_ptid
= save_ptid
;
983 retval
= d10v_make_iaddr (pc
);
988 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
992 save_ptid
= inferior_ptid
;
993 inferior_ptid
= ptid
;
994 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
995 inferior_ptid
= save_ptid
;
1001 return (d10v_make_daddr (read_register (SP_REGNUM
)));
1005 d10v_write_sp (CORE_ADDR val
)
1007 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
1013 return (d10v_make_daddr (read_register (FP_REGNUM
)));
1016 /* Function: push_return_address (pc)
1017 Set up the return address for the inferior function call.
1018 Needed for targets where we don't actually execute a JSR/BSR instruction */
1021 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1023 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
1028 /* When arguments must be pushed onto the stack, they go on in reverse
1029 order. The below implements a FILO (stack) to do this. */
1034 struct stack_item
*prev
;
1038 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
1039 void *contents
, int len
);
1040 static struct stack_item
*
1041 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1043 struct stack_item
*si
;
1044 si
= xmalloc (sizeof (struct stack_item
));
1045 si
->data
= xmalloc (len
);
1048 memcpy (si
->data
, contents
, len
);
1052 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1053 static struct stack_item
*
1054 pop_stack_item (struct stack_item
*si
)
1056 struct stack_item
*dead
= si
;
1065 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1066 int struct_return
, CORE_ADDR struct_addr
)
1069 int regnum
= ARG1_REGNUM
;
1070 struct stack_item
*si
= NULL
;
1072 /* Fill in registers and arg lists */
1073 for (i
= 0; i
< nargs
; i
++)
1075 struct value
*arg
= args
[i
];
1076 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1077 char *contents
= VALUE_CONTENTS (arg
);
1078 int len
= TYPE_LENGTH (type
);
1079 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1081 int aligned_regnum
= (regnum
+ 1) & ~1;
1082 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1083 /* fits in a single register, do not align */
1085 long val
= extract_unsigned_integer (contents
, len
);
1086 write_register (regnum
++, val
);
1088 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1089 /* value fits in remaining registers, store keeping left
1093 regnum
= aligned_regnum
;
1094 for (b
= 0; b
< (len
& ~1); b
+= 2)
1096 long val
= extract_unsigned_integer (&contents
[b
], 2);
1097 write_register (regnum
++, val
);
1101 long val
= extract_unsigned_integer (&contents
[b
], 1);
1102 write_register (regnum
++, (val
<< 8));
1107 /* arg will go onto stack */
1108 regnum
= ARGN_REGNUM
+ 1;
1109 si
= push_stack_item (si
, contents
, len
);
1116 sp
= (sp
- si
->len
) & ~1;
1117 write_memory (sp
, si
->data
, si
->len
);
1118 si
= pop_stack_item (si
);
1125 /* Given a return value in `regbuf' with a type `valtype',
1126 extract and copy its value into `valbuf'. */
1129 d10v_extract_return_value (struct type
*type
, char regbuf
[REGISTER_BYTES
],
1133 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1135 len
= TYPE_LENGTH (type
);
1138 unsigned short c
= extract_unsigned_integer (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1139 store_unsigned_integer (valbuf
, 1, c
);
1141 else if ((len
& 1) == 0)
1142 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
), len
);
1145 /* For return values of odd size, the first byte is in the
1146 least significant part of the first register. The
1147 remaining bytes in remaining registers. Interestingly,
1148 when such values are passed in, the last byte is in the
1149 most significant byte of that same register - wierd. */
1150 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
) + 1, len
);
1155 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1156 understands. Returns number of bytes that can be transfered
1157 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1158 (segmentation fault). Since the simulator knows all about how the
1159 VM system works, we just call that to do the translation. */
1162 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1163 CORE_ADDR
*targ_addr
, int *targ_len
)
1167 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1170 d10v_imap_register
);
1171 *targ_addr
= out_addr
;
1172 *targ_len
= out_len
;
1176 /* The following code implements access to, and display of, the D10V's
1177 instruction trace buffer. The buffer consists of 64K or more
1178 4-byte words of data, of which each words includes an 8-bit count,
1179 an 8-bit segment number, and a 16-bit instruction address.
1181 In theory, the trace buffer is continuously capturing instruction
1182 data that the CPU presents on its "debug bus", but in practice, the
1183 ROMified GDB stub only enables tracing when it continues or steps
1184 the program, and stops tracing when the program stops; so it
1185 actually works for GDB to read the buffer counter out of memory and
1186 then read each trace word. The counter records where the tracing
1187 stops, but there is no record of where it started, so we remember
1188 the PC when we resumed and then search backwards in the trace
1189 buffer for a word that includes that address. This is not perfect,
1190 because you will miss trace data if the resumption PC is the target
1191 of a branch. (The value of the buffer counter is semi-random, any
1192 trace data from a previous program stop is gone.) */
1194 /* The address of the last word recorded in the trace buffer. */
1196 #define DBBC_ADDR (0xd80000)
1198 /* The base of the trace buffer, at least for the "Board_0". */
1200 #define TRACE_BUFFER_BASE (0xf40000)
1202 static void trace_command (char *, int);
1204 static void untrace_command (char *, int);
1206 static void trace_info (char *, int);
1208 static void tdisassemble_command (char *, int);
1210 static void display_trace (int, int);
1212 /* True when instruction traces are being collected. */
1216 /* Remembered PC. */
1218 static CORE_ADDR last_pc
;
1220 /* True when trace output should be displayed whenever program stops. */
1222 static int trace_display
;
1224 /* True when trace listing should include source lines. */
1226 static int default_trace_show_source
= 1;
1237 trace_command (char *args
, int from_tty
)
1239 /* Clear the host-side trace buffer, allocating space if needed. */
1240 trace_data
.size
= 0;
1241 if (trace_data
.counts
== NULL
)
1242 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1243 if (trace_data
.addrs
== NULL
)
1244 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1248 printf_filtered ("Tracing is now on.\n");
1252 untrace_command (char *args
, int from_tty
)
1256 printf_filtered ("Tracing is now off.\n");
1260 trace_info (char *args
, int from_tty
)
1264 if (trace_data
.size
)
1266 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1268 for (i
= 0; i
< trace_data
.size
; ++i
)
1270 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1272 trace_data
.counts
[i
],
1273 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1274 paddr_nz (trace_data
.addrs
[i
]));
1278 printf_filtered ("No entries in trace buffer.\n");
1280 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1283 /* Print the instruction at address MEMADDR in debugged memory,
1284 on STREAM. Returns length of the instruction, in bytes. */
1287 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1289 /* If there's no disassembler, something is very wrong. */
1290 if (tm_print_insn
== NULL
)
1291 internal_error (__FILE__
, __LINE__
,
1292 "print_insn: no disassembler");
1294 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1295 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1297 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1298 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1302 d10v_eva_prepare_to_trace (void)
1307 last_pc
= read_register (PC_REGNUM
);
1310 /* Collect trace data from the target board and format it into a form
1311 more useful for display. */
1314 d10v_eva_get_trace_data (void)
1316 int count
, i
, j
, oldsize
;
1317 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1318 unsigned int last_trace
, trace_word
, next_word
;
1319 unsigned int *tmpspace
;
1324 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1326 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1328 /* Collect buffer contents from the target, stopping when we reach
1329 the word recorded when execution resumed. */
1332 while (last_trace
> 0)
1336 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1337 trace_addr
= trace_word
& 0xffff;
1339 /* Ignore an apparently nonsensical entry. */
1340 if (trace_addr
== 0xffd5)
1342 tmpspace
[count
++] = trace_word
;
1343 if (trace_addr
== last_pc
)
1349 /* Move the data to the host-side trace buffer, adjusting counts to
1350 include the last instruction executed and transforming the address
1351 into something that GDB likes. */
1353 for (i
= 0; i
< count
; ++i
)
1355 trace_word
= tmpspace
[i
];
1356 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1357 trace_addr
= trace_word
& 0xffff;
1358 next_cnt
= (next_word
>> 24) & 0xff;
1359 j
= trace_data
.size
+ count
- i
- 1;
1360 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1361 trace_data
.counts
[j
] = next_cnt
+ 1;
1364 oldsize
= trace_data
.size
;
1365 trace_data
.size
+= count
;
1370 display_trace (oldsize
, trace_data
.size
);
1374 tdisassemble_command (char *arg
, int from_tty
)
1377 CORE_ADDR low
, high
;
1383 high
= trace_data
.size
;
1385 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1387 low
= parse_and_eval_address (arg
);
1392 /* Two arguments. */
1393 *space_index
= '\0';
1394 low
= parse_and_eval_address (arg
);
1395 high
= parse_and_eval_address (space_index
+ 1);
1400 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1402 display_trace (low
, high
);
1404 printf_filtered ("End of trace dump.\n");
1405 gdb_flush (gdb_stdout
);
1409 display_trace (int low
, int high
)
1411 int i
, count
, trace_show_source
, first
, suppress
;
1412 CORE_ADDR next_address
;
1414 trace_show_source
= default_trace_show_source
;
1415 if (!have_full_symbols () && !have_partial_symbols ())
1417 trace_show_source
= 0;
1418 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1419 printf_filtered ("Trace will not display any source.\n");
1424 for (i
= low
; i
< high
; ++i
)
1426 next_address
= trace_data
.addrs
[i
];
1427 count
= trace_data
.counts
[i
];
1431 if (trace_show_source
)
1433 struct symtab_and_line sal
, sal_prev
;
1435 sal_prev
= find_pc_line (next_address
- 4, 0);
1436 sal
= find_pc_line (next_address
, 0);
1440 if (first
|| sal
.line
!= sal_prev
.line
)
1441 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1447 /* FIXME-32x64--assumes sal.pc fits in long. */
1448 printf_filtered ("No source file for address %s.\n",
1449 local_hex_string ((unsigned long) sal
.pc
));
1454 print_address (next_address
, gdb_stdout
);
1455 printf_filtered (":");
1456 printf_filtered ("\t");
1458 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1459 printf_filtered ("\n");
1460 gdb_flush (gdb_stdout
);
1466 static gdbarch_init_ftype d10v_gdbarch_init
;
1468 static struct gdbarch
*
1469 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1471 static LONGEST d10v_call_dummy_words
[] =
1473 struct gdbarch
*gdbarch
;
1475 struct gdbarch_tdep
*tdep
;
1476 gdbarch_register_name_ftype
*d10v_register_name
;
1477 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1479 /* Find a candidate among the list of pre-declared architectures. */
1480 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1482 return arches
->gdbarch
;
1484 /* None found, create a new architecture from the information
1486 tdep
= XMALLOC (struct gdbarch_tdep
);
1487 gdbarch
= gdbarch_alloc (&info
, tdep
);
1489 switch (info
.bfd_arch_info
->mach
)
1491 case bfd_mach_d10v_ts2
:
1493 d10v_register_name
= d10v_ts2_register_name
;
1494 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1495 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1496 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1497 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1498 tdep
->imap_register
= d10v_ts2_imap_register
;
1501 case bfd_mach_d10v_ts3
:
1503 d10v_register_name
= d10v_ts3_register_name
;
1504 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1505 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1506 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1507 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1508 tdep
->imap_register
= d10v_ts3_imap_register
;
1512 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1513 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1514 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1515 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1516 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1518 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1519 set_gdbarch_sp_regnum (gdbarch
, 15);
1520 set_gdbarch_fp_regnum (gdbarch
, 11);
1521 set_gdbarch_pc_regnum (gdbarch
, 18);
1522 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1523 set_gdbarch_register_size (gdbarch
, 2);
1524 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1525 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1526 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1527 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1528 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1529 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1530 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1532 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1533 set_gdbarch_addr_bit (gdbarch
, 32);
1534 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1535 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1536 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1537 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1538 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1539 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1540 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1541 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1542 double'' is 64 bits. */
1543 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1544 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1545 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1546 switch (info
.byte_order
)
1548 case BFD_ENDIAN_BIG
:
1549 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1550 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1551 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1553 case BFD_ENDIAN_LITTLE
:
1554 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1555 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1556 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1559 internal_error (__FILE__
, __LINE__
,
1560 "d10v_gdbarch_init: bad byte order for float format");
1563 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
1564 set_gdbarch_call_dummy_length (gdbarch
, 0);
1565 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
1566 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1567 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1568 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1569 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1570 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
1571 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1572 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1573 set_gdbarch_call_dummy_p (gdbarch
, 1);
1574 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1575 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
1576 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1578 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1579 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1580 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1581 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1583 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1584 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1585 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1586 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1588 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1589 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1591 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1593 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1594 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1595 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1596 set_gdbarch_function_start_offset (gdbarch
, 0);
1597 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1599 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1601 set_gdbarch_frame_args_skip (gdbarch
, 0);
1602 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1603 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1604 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1605 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1606 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
1607 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
1608 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1609 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1610 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1612 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1613 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1619 extern void (*target_resume_hook
) (void);
1620 extern void (*target_wait_loop_hook
) (void);
1623 _initialize_d10v_tdep (void)
1625 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1627 tm_print_insn
= print_insn_d10v
;
1629 target_resume_hook
= d10v_eva_prepare_to_trace
;
1630 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1632 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1634 add_com ("itrace", class_support
, trace_command
,
1635 "Enable tracing of instruction execution.");
1637 add_com ("iuntrace", class_support
, untrace_command
,
1638 "Disable tracing of instruction execution.");
1640 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1641 "Disassemble the trace buffer.\n\
1642 Two optional arguments specify a range of trace buffer entries\n\
1643 as reported by info trace (NOT addresses!).");
1645 add_info ("itrace", trace_info
,
1646 "Display info about the trace data buffer.");
1648 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1649 var_integer
, (char *) &trace_display
,
1650 "Set automatic display of trace.\n", &setlist
),
1652 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1653 var_integer
, (char *) &default_trace_show_source
,
1654 "Set display of source code with trace.\n", &setlist
),