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Add __FILE__ and __LINE__ parameter to internal_error() /
[deliverable/binutils-gdb.git] / gdb / d30v-tdep.c
1 /* Target-dependent code for Mitsubishi D30V, for GDB.
2 Copyright (C) 1996, 1997, 2000, 2001 Free Software Foundation, Inc.
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21 /* Contributed by Martin Hunt, hunt@cygnus.com */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "obstack.h"
26 #include "symtab.h"
27 #include "gdbtypes.h"
28 #include "gdbcmd.h"
29 #include "gdbcore.h"
30 #include "gdb_string.h"
31 #include "value.h"
32 #include "inferior.h"
33 #include "dis-asm.h"
34 #include "symfile.h"
35 #include "objfiles.h"
36
37 #include "language.h" /* For local_hex_string() */
38
39 void d30v_frame_find_saved_regs (struct frame_info *fi,
40 struct frame_saved_regs *fsr);
41 void d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
42 struct frame_saved_regs *fsr);
43 static void d30v_pop_dummy_frame (struct frame_info *fi);
44 static void d30v_print_flags (void);
45 static void print_flags_command (char *, int);
46
47 /* the following defines assume:
48 fp is r61, lr is r62, sp is r63, and ?? is r22
49 if that changes, they will need to be updated */
50
51 #define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */
52
53 #define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */
54 #define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */
55 #define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */
56 #define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */
57
58 #define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */
59 #define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */
60 #define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */
61 #define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */
62
63 #define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */
64 #define OP_NOP 0x00f00000 /* nop */
65
66 #define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */
67 #define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */
68 #define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */
69 #define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */
70 #define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */
71 #define OP_OR_SP_R0_IMM 0x03abf000 /* or sp,r0,imm */
72
73 /* no mask */
74 #define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */
75 #define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */
76 #define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */
77 #define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */
78 #define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */
79
80 #define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */
81 #define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */
82 #define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */
83 #define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */
84 #define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */
85
86 #define OP_MASK_FM_BIT 0x80000000
87 #define OP_MASK_CC_BITS 0x70000000
88 #define OP_MASK_SUB_INST 0x0fffffff
89
90 #define EXTRACT_RA(op) (((op) >> 12) & 0x3f)
91 #define EXTRACT_RB(op) (((op) >> 6) & 0x3f)
92 #define EXTRACT_RC(op) (((op) & 0x3f)
93 #define EXTRACT_UIMM6(op) ((op) & 0x3f)
94 #define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26)
95 #define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff))
96 #define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr))
97
98
99 int
100 d30v_frame_chain_valid (CORE_ADDR chain, struct frame_info *fi)
101 {
102 #if 0
103 return ((chain) != 0 && (fi) != 0 && (fi)->return_pc != 0);
104 #else
105 return ((chain) != 0 && (fi) != 0 && (fi)->frame <= chain);
106 #endif
107 }
108
109 /* Discard from the stack the innermost frame, restoring all saved
110 registers. */
111
112 void
113 d30v_pop_frame (void)
114 {
115 struct frame_info *frame = get_current_frame ();
116 CORE_ADDR fp;
117 int regnum;
118 struct frame_saved_regs fsr;
119 char raw_buffer[8];
120
121 fp = FRAME_FP (frame);
122 if (frame->dummy)
123 {
124 d30v_pop_dummy_frame (frame);
125 return;
126 }
127
128 /* fill out fsr with the address of where each */
129 /* register was stored in the frame */
130 get_frame_saved_regs (frame, &fsr);
131
132 /* now update the current registers with the old values */
133 for (regnum = A0_REGNUM; regnum < A0_REGNUM + 2; regnum++)
134 {
135 if (fsr.regs[regnum])
136 {
137 read_memory (fsr.regs[regnum], raw_buffer, 8);
138 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8);
139 }
140 }
141 for (regnum = 0; regnum < SP_REGNUM; regnum++)
142 {
143 if (fsr.regs[regnum])
144 {
145 write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4));
146 }
147 }
148 if (fsr.regs[PSW_REGNUM])
149 {
150 write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4));
151 }
152
153 write_register (PC_REGNUM, read_register (LR_REGNUM));
154 write_register (SP_REGNUM, fp + frame->size);
155 target_store_registers (-1);
156 flush_cached_frames ();
157 }
158
159 static int
160 check_prologue (unsigned long op)
161 {
162 /* add sp,sp,imm -- observed */
163 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
164 return 1;
165
166 /* add r22,sp,imm -- observed */
167 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
168 return 1;
169
170 /* or fp,r0,sp -- observed */
171 if (op == OP_OR_FP_R0_SP)
172 return 1;
173
174 /* nop */
175 if ((op & OP_MASK_OPCODE) == OP_NOP)
176 return 1;
177
178 /* stw Ra,@(sp,r0) */
179 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0)
180 return 1;
181
182 /* stw Ra,@(sp,0x0) */
183 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)
184 return 1;
185
186 /* st2w Ra,@(sp,r0) */
187 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0)
188 return 1;
189
190 /* st2w Ra,@(sp,0x0) */
191 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)
192 return 1;
193
194 /* stw fp, @(r22+,r0) -- observed */
195 if (op == OP_STW_FP_R22P_R0)
196 return 1;
197
198 /* stw r62, @(r22+,r0) -- observed */
199 if (op == OP_STW_LR_R22P_R0)
200 return 1;
201
202 /* stw Ra, @(fp,r0) -- observed */
203 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
204 return 1; /* first arg */
205
206 /* stw Ra, @(fp,imm) -- observed */
207 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
208 return 1; /* second and subsequent args */
209
210 /* stw fp,@(sp,imm) -- observed */
211 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
212 return 1;
213
214 /* st2w Ra,@(r22+,r0) */
215 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
216 return 1;
217
218 /* stw Ra, @(sp-) */
219 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
220 return 1;
221
222 /* st2w Ra, @(sp-) */
223 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
224 return 1;
225
226 /* sub.? sp,sp,imm */
227 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
228 return 1;
229
230 return 0;
231 }
232
233 CORE_ADDR
234 d30v_skip_prologue (CORE_ADDR pc)
235 {
236 unsigned long op[2];
237 unsigned long opl, opr; /* left / right sub operations */
238 unsigned long fm0, fm1; /* left / right mode bits */
239 unsigned long cc0, cc1;
240 unsigned long op1, op2;
241 CORE_ADDR func_addr, func_end;
242 struct symtab_and_line sal;
243
244 /* If we have line debugging information, then the end of the */
245 /* prologue should the first assembly instruction of the first source line */
246 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
247 {
248 sal = find_pc_line (func_addr, 0);
249 if (sal.end && sal.end < func_end)
250 return sal.end;
251 }
252
253 if (target_read_memory (pc, (char *) &op[0], 8))
254 return pc; /* Can't access it -- assume no prologue. */
255
256 while (1)
257 {
258 opl = (unsigned long) read_memory_integer (pc, 4);
259 opr = (unsigned long) read_memory_integer (pc + 4, 4);
260
261 fm0 = (opl & OP_MASK_FM_BIT);
262 fm1 = (opr & OP_MASK_FM_BIT);
263
264 cc0 = (opl & OP_MASK_CC_BITS);
265 cc1 = (opr & OP_MASK_CC_BITS);
266
267 opl = (opl & OP_MASK_SUB_INST);
268 opr = (opr & OP_MASK_SUB_INST);
269
270 if (fm0 && fm1)
271 {
272 /* long instruction (opl contains the opcode) */
273 if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */
274 ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */
275 ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */
276 ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */
277 break;
278 }
279 else
280 {
281 /* short instructions */
282 if (fm0 && !fm1)
283 {
284 op1 = opr;
285 op2 = opl;
286 }
287 else
288 {
289 op1 = opl;
290 op2 = opr;
291 }
292 if (check_prologue (op1))
293 {
294 if (!check_prologue (op2))
295 {
296 /* if the previous opcode was really part of the prologue */
297 /* and not just a NOP, then we want to break after both instructions */
298 if ((op1 & OP_MASK_OPCODE) != OP_NOP)
299 pc += 8;
300 break;
301 }
302 }
303 else
304 break;
305 }
306 pc += 8;
307 }
308 return pc;
309 }
310
311 static int end_of_stack;
312
313 /* Given a GDB frame, determine the address of the calling function's frame.
314 This will be used to create a new GDB frame struct, and then
315 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
316 */
317
318 CORE_ADDR
319 d30v_frame_chain (struct frame_info *frame)
320 {
321 struct frame_saved_regs fsr;
322
323 d30v_frame_find_saved_regs (frame, &fsr);
324
325 if (end_of_stack)
326 return (CORE_ADDR) 0;
327
328 if (frame->return_pc == IMEM_START)
329 return (CORE_ADDR) 0;
330
331 if (!fsr.regs[FP_REGNUM])
332 {
333 if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START)
334 return (CORE_ADDR) 0;
335
336 return fsr.regs[SP_REGNUM];
337 }
338
339 if (!read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4))
340 return (CORE_ADDR) 0;
341
342 return read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4);
343 }
344
345 static int next_addr, uses_frame;
346 static int frame_size;
347
348 static int
349 prologue_find_regs (unsigned long op, struct frame_saved_regs *fsr,
350 CORE_ADDR addr)
351 {
352 int n;
353 int offset;
354
355 /* add sp,sp,imm -- observed */
356 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
357 {
358 offset = EXTRACT_IMM6 (op);
359 /*next_addr += offset; */
360 frame_size += -offset;
361 return 1;
362 }
363
364 /* add r22,sp,imm -- observed */
365 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
366 {
367 offset = EXTRACT_IMM6 (op);
368 next_addr = (offset - frame_size);
369 return 1;
370 }
371
372 /* stw Ra, @(fp, offset) -- observed */
373 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
374 {
375 n = EXTRACT_RA (op);
376 offset = EXTRACT_IMM6 (op);
377 fsr->regs[n] = (offset - frame_size);
378 return 1;
379 }
380
381 /* stw Ra, @(fp, r0) -- observed */
382 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
383 {
384 n = EXTRACT_RA (op);
385 fsr->regs[n] = (-frame_size);
386 return 1;
387 }
388
389 /* or fp,0,sp -- observed */
390 if ((op == OP_OR_FP_R0_SP) ||
391 (op == OP_OR_FP_SP_R0) ||
392 (op == OP_OR_FP_IMM0_SP))
393 {
394 uses_frame = 1;
395 return 1;
396 }
397
398 /* nop */
399 if ((op & OP_MASK_OPCODE) == OP_NOP)
400 return 1;
401
402 /* stw Ra,@(r22+,r0) -- observed */
403 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0)
404 {
405 n = EXTRACT_RA (op);
406 fsr->regs[n] = next_addr;
407 next_addr += 4;
408 return 1;
409 }
410 #if 0 /* subsumed in pattern above */
411 /* stw fp,@(r22+,r0) -- observed */
412 if (op == OP_STW_FP_R22P_R0)
413 {
414 fsr->regs[FP_REGNUM] = next_addr; /* XXX */
415 next_addr += 4;
416 return 1;
417 }
418
419 /* stw r62,@(r22+,r0) -- observed */
420 if (op == OP_STW_LR_R22P_R0)
421 {
422 fsr->regs[LR_REGNUM] = next_addr;
423 next_addr += 4;
424 return 1;
425 }
426 #endif
427 /* st2w Ra,@(r22+,r0) -- observed */
428 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
429 {
430 n = EXTRACT_RA (op);
431 fsr->regs[n] = next_addr;
432 fsr->regs[n + 1] = next_addr + 4;
433 next_addr += 8;
434 return 1;
435 }
436
437 /* stw rn, @(sp-) */
438 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
439 {
440 n = EXTRACT_RA (op);
441 fsr->regs[n] = next_addr;
442 next_addr -= 4;
443 return 1;
444 }
445
446 /* st2w Ra, @(sp-) */
447 else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
448 {
449 n = EXTRACT_RA (op);
450 fsr->regs[n] = next_addr;
451 fsr->regs[n + 1] = next_addr + 4;
452 next_addr -= 8;
453 return 1;
454 }
455
456 /* sub sp,sp,imm */
457 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
458 {
459 offset = EXTRACT_IMM6 (op);
460 frame_size += -offset;
461 return 1;
462 }
463
464 /* st rn, @(sp,0) -- observed */
465 if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) ||
466 ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0))
467 {
468 n = EXTRACT_RA (op);
469 fsr->regs[n] = (-frame_size);
470 return 1;
471 }
472
473 /* st2w rn, @(sp,0) */
474 if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) ||
475 ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0))
476 {
477 n = EXTRACT_RA (op);
478 fsr->regs[n] = (-frame_size);
479 fsr->regs[n + 1] = (-frame_size) + 4;
480 return 1;
481 }
482
483 /* stw fp,@(sp,imm) -- observed */
484 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
485 {
486 offset = EXTRACT_IMM6 (op);
487 fsr->regs[FP_REGNUM] = (offset - frame_size);
488 return 1;
489 }
490 return 0;
491 }
492
493 /* Put here the code to store, into a struct frame_saved_regs, the
494 addresses of the saved registers of frame described by FRAME_INFO.
495 This includes special registers such as pc and fp saved in special
496 ways in the stack frame. sp is even more special: the address we
497 return for it IS the sp for the next frame. */
498 void
499 d30v_frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr)
500 {
501 CORE_ADDR fp, pc;
502 unsigned long opl, opr;
503 unsigned long op1, op2;
504 unsigned long fm0, fm1;
505 int i;
506
507 fp = fi->frame;
508 memset (fsr, 0, sizeof (*fsr));
509 next_addr = 0;
510 frame_size = 0;
511 end_of_stack = 0;
512
513 uses_frame = 0;
514
515 d30v_frame_find_saved_regs_offsets (fi, fsr);
516
517 fi->size = frame_size;
518
519 if (!fp)
520 fp = read_register (SP_REGNUM);
521
522 for (i = 0; i < NUM_REGS - 1; i++)
523 if (fsr->regs[i])
524 {
525 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
526 }
527
528 if (fsr->regs[LR_REGNUM])
529 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
530 else
531 fi->return_pc = read_register (LR_REGNUM);
532
533 /* the SP is not normally (ever?) saved, but check anyway */
534 if (!fsr->regs[SP_REGNUM])
535 {
536 /* if the FP was saved, that means the current FP is valid, */
537 /* otherwise, it isn't being used, so we use the SP instead */
538 if (uses_frame)
539 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
540 else
541 {
542 fsr->regs[SP_REGNUM] = fp + fi->size;
543 fi->frameless = 1;
544 fsr->regs[FP_REGNUM] = 0;
545 }
546 }
547 }
548
549 void
550 d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
551 struct frame_saved_regs *fsr)
552 {
553 CORE_ADDR fp, pc;
554 unsigned long opl, opr;
555 unsigned long op1, op2;
556 unsigned long fm0, fm1;
557 int i;
558
559 fp = fi->frame;
560 memset (fsr, 0, sizeof (*fsr));
561 next_addr = 0;
562 frame_size = 0;
563 end_of_stack = 0;
564
565 pc = get_pc_function_start (fi->pc);
566
567 uses_frame = 0;
568 while (pc < fi->pc)
569 {
570 opl = (unsigned long) read_memory_integer (pc, 4);
571 opr = (unsigned long) read_memory_integer (pc + 4, 4);
572
573 fm0 = (opl & OP_MASK_FM_BIT);
574 fm1 = (opr & OP_MASK_FM_BIT);
575
576 opl = (opl & OP_MASK_SUB_INST);
577 opr = (opr & OP_MASK_SUB_INST);
578
579 if (fm0 && fm1)
580 {
581 /* long instruction */
582 if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
583 {
584 /* add sp,sp,n */
585 long offset = EXTRACT_IMM32 (opl, opr);
586 frame_size += -offset;
587 }
588 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
589 {
590 /* add r22,sp,offset */
591 long offset = EXTRACT_IMM32 (opl, opr);
592 next_addr = (offset - frame_size);
593 }
594 else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM)
595 {
596 /* st Ra, @(sp,imm) */
597 long offset = EXTRACT_IMM32 (opl, opr);
598 short n = EXTRACT_RA (opl);
599 fsr->regs[n] = (offset - frame_size);
600 }
601 else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM)
602 {
603 /* st2w Ra, @(sp,offset) */
604 long offset = EXTRACT_IMM32 (opl, opr);
605 short n = EXTRACT_RA (opl);
606 fsr->regs[n] = (offset - frame_size);
607 fsr->regs[n + 1] = (offset - frame_size) + 4;
608 }
609 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_OR_SP_R0_IMM)
610 {
611 end_of_stack = 1;
612 }
613 else
614 break;
615 }
616 else
617 {
618 /* short instructions */
619 if (fm0 && !fm1)
620 {
621 op2 = opl;
622 op1 = opr;
623 }
624 else
625 {
626 op1 = opl;
627 op2 = opr;
628 }
629 if (!prologue_find_regs (op1, fsr, pc) || !prologue_find_regs (op2, fsr, pc))
630 break;
631 }
632 pc += 8;
633 }
634
635 #if 0
636 fi->size = frame_size;
637
638 if (!fp)
639 fp = read_register (SP_REGNUM);
640
641 for (i = 0; i < NUM_REGS - 1; i++)
642 if (fsr->regs[i])
643 {
644 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
645 }
646
647 if (fsr->regs[LR_REGNUM])
648 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
649 else
650 fi->return_pc = read_register (LR_REGNUM);
651
652 /* the SP is not normally (ever?) saved, but check anyway */
653 if (!fsr->regs[SP_REGNUM])
654 {
655 /* if the FP was saved, that means the current FP is valid, */
656 /* otherwise, it isn't being used, so we use the SP instead */
657 if (uses_frame)
658 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
659 else
660 {
661 fsr->regs[SP_REGNUM] = fp + fi->size;
662 fi->frameless = 1;
663 fsr->regs[FP_REGNUM] = 0;
664 }
665 }
666 #endif
667 }
668
669 void
670 d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
671 {
672 struct frame_saved_regs dummy;
673
674 if (fi->next && (fi->pc == 0))
675 fi->pc = fi->next->return_pc;
676
677 d30v_frame_find_saved_regs_offsets (fi, &dummy);
678
679 if (uses_frame == 0)
680 fi->frameless = 1;
681 else
682 fi->frameless = 0;
683
684 if ((fi->next == 0) && (uses_frame == 0))
685 /* innermost frame and it's "frameless",
686 so the fi->frame field is wrong, fix it! */
687 fi->frame = read_sp ();
688
689 if (dummy.regs[LR_REGNUM])
690 {
691 /* it was saved, grab it! */
692 dummy.regs[LR_REGNUM] += (fi->frame + frame_size);
693 fi->return_pc = read_memory_unsigned_integer (dummy.regs[LR_REGNUM], 4);
694 }
695 else
696 fi->return_pc = read_register (LR_REGNUM);
697 }
698
699 void
700 d30v_init_frame_pc (int fromleaf, struct frame_info *prev)
701 {
702 /* default value, put here so we can breakpoint on it and
703 see if the default value is really the right thing to use */
704 prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
705 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
706 }
707
708 static void d30v_print_register (int regnum, int tabular);
709
710 static void
711 d30v_print_register (int regnum, int tabular)
712 {
713 if (regnum < A0_REGNUM)
714 {
715 if (tabular)
716 printf_filtered ("%08lx", (long) read_register (regnum));
717 else
718 printf_filtered ("0x%lx %ld",
719 (long) read_register (regnum),
720 (long) read_register (regnum));
721 }
722 else
723 {
724 char regbuf[MAX_REGISTER_RAW_SIZE];
725
726 read_relative_register_raw_bytes (regnum, regbuf);
727
728 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
729 gdb_stdout, 'x', 1, 0, Val_pretty_default);
730
731 if (!tabular)
732 {
733 printf_filtered (" ");
734 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
735 gdb_stdout, 'd', 1, 0, Val_pretty_default);
736 }
737 }
738 }
739
740 static void
741 d30v_print_flags (void)
742 {
743 long psw = read_register (PSW_REGNUM);
744 printf_filtered ("flags #1");
745 printf_filtered (" (sm) %d", (psw & PSW_SM) != 0);
746 printf_filtered (" (ea) %d", (psw & PSW_EA) != 0);
747 printf_filtered (" (db) %d", (psw & PSW_DB) != 0);
748 printf_filtered (" (ds) %d", (psw & PSW_DS) != 0);
749 printf_filtered (" (ie) %d", (psw & PSW_IE) != 0);
750 printf_filtered (" (rp) %d", (psw & PSW_RP) != 0);
751 printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0);
752
753 printf_filtered ("flags #2");
754 printf_filtered (" (f0) %d", (psw & PSW_F0) != 0);
755 printf_filtered (" (f1) %d", (psw & PSW_F1) != 0);
756 printf_filtered (" (f2) %d", (psw & PSW_F2) != 0);
757 printf_filtered (" (f3) %d", (psw & PSW_F3) != 0);
758 printf_filtered (" (s) %d", (psw & PSW_S) != 0);
759 printf_filtered (" (v) %d", (psw & PSW_V) != 0);
760 printf_filtered (" (va) %d", (psw & PSW_VA) != 0);
761 printf_filtered (" (c) %d\n", (psw & PSW_C) != 0);
762 }
763
764 static void
765 print_flags_command (char *args, int from_tty)
766 {
767 d30v_print_flags ();
768 }
769
770 void
771 d30v_do_registers_info (int regnum, int fpregs)
772 {
773 long long num1, num2;
774 long psw;
775
776 if (regnum != -1)
777 {
778 if (REGISTER_NAME (0) == NULL || REGISTER_NAME (0)[0] == '\000')
779 return;
780
781 printf_filtered ("%s ", REGISTER_NAME (regnum));
782 d30v_print_register (regnum, 0);
783
784 printf_filtered ("\n");
785 return;
786 }
787
788 /* Have to print all the registers. Format them nicely. */
789
790 printf_filtered ("PC=");
791 print_address (read_pc (), gdb_stdout);
792
793 printf_filtered (" PSW=");
794 d30v_print_register (PSW_REGNUM, 1);
795
796 printf_filtered (" BPC=");
797 print_address (read_register (BPC_REGNUM), gdb_stdout);
798
799 printf_filtered (" BPSW=");
800 d30v_print_register (BPSW_REGNUM, 1);
801 printf_filtered ("\n");
802
803 printf_filtered ("DPC=");
804 print_address (read_register (DPC_REGNUM), gdb_stdout);
805
806 printf_filtered (" DPSW=");
807 d30v_print_register (DPSW_REGNUM, 1);
808
809 printf_filtered (" IBA=");
810 print_address (read_register (IBA_REGNUM), gdb_stdout);
811 printf_filtered ("\n");
812
813 printf_filtered ("RPT_C=");
814 d30v_print_register (RPT_C_REGNUM, 1);
815
816 printf_filtered (" RPT_S=");
817 print_address (read_register (RPT_S_REGNUM), gdb_stdout);
818
819 printf_filtered (" RPT_E=");
820 print_address (read_register (RPT_E_REGNUM), gdb_stdout);
821 printf_filtered ("\n");
822
823 printf_filtered ("MOD_S=");
824 print_address (read_register (MOD_S_REGNUM), gdb_stdout);
825
826 printf_filtered (" MOD_E=");
827 print_address (read_register (MOD_E_REGNUM), gdb_stdout);
828 printf_filtered ("\n");
829
830 printf_filtered ("EIT_VB=");
831 print_address (read_register (EIT_VB_REGNUM), gdb_stdout);
832
833 printf_filtered (" INT_S=");
834 d30v_print_register (INT_S_REGNUM, 1);
835
836 printf_filtered (" INT_M=");
837 d30v_print_register (INT_M_REGNUM, 1);
838 printf_filtered ("\n");
839
840 d30v_print_flags ();
841 for (regnum = 0; regnum <= 63;)
842 {
843 int i;
844
845 printf_filtered ("R%d-R%d ", regnum, regnum + 7);
846 if (regnum < 10)
847 printf_filtered (" ");
848 if (regnum + 7 < 10)
849 printf_filtered (" ");
850
851 for (i = 0; i < 8; i++)
852 {
853 printf_filtered (" ");
854 d30v_print_register (regnum++, 1);
855 }
856
857 printf_filtered ("\n");
858 }
859
860 printf_filtered ("A0-A1 ");
861
862 d30v_print_register (A0_REGNUM, 1);
863 printf_filtered (" ");
864 d30v_print_register (A1_REGNUM, 1);
865 printf_filtered ("\n");
866 }
867
868 CORE_ADDR
869 d30v_fix_call_dummy (char *dummyname, CORE_ADDR start_sp, CORE_ADDR fun,
870 int nargs, value_ptr *args, struct type *type, int gcc_p)
871 {
872 int regnum;
873 CORE_ADDR sp;
874 char buffer[MAX_REGISTER_RAW_SIZE];
875 struct frame_info *frame = get_current_frame ();
876 frame->dummy = start_sp;
877 /*start_sp |= DMEM_START; */
878
879 sp = start_sp;
880 for (regnum = 0; regnum < NUM_REGS; regnum++)
881 {
882 sp -= REGISTER_RAW_SIZE (regnum);
883 store_address (buffer, REGISTER_RAW_SIZE (regnum), read_register (regnum));
884 write_memory (sp, buffer, REGISTER_RAW_SIZE (regnum));
885 }
886 write_register (SP_REGNUM, (LONGEST) sp);
887 /* now we need to load LR with the return address */
888 write_register (LR_REGNUM, (LONGEST) d30v_call_dummy_address ());
889 return sp;
890 }
891
892 static void
893 d30v_pop_dummy_frame (struct frame_info *fi)
894 {
895 CORE_ADDR sp = fi->dummy;
896 int regnum;
897
898 for (regnum = 0; regnum < NUM_REGS; regnum++)
899 {
900 sp -= REGISTER_RAW_SIZE (regnum);
901 write_register (regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE (regnum)));
902 }
903 flush_cached_frames (); /* needed? */
904 }
905
906
907 CORE_ADDR
908 d30v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp,
909 int struct_return, CORE_ADDR struct_addr)
910 {
911 int i, len, index = 0, regnum = 2;
912 char buffer[4], *contents;
913 LONGEST val;
914 CORE_ADDR ptrs[10];
915
916 #if 0
917 /* Pass 1. Put all large args on stack */
918 for (i = 0; i < nargs; i++)
919 {
920 value_ptr arg = args[i];
921 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
922 len = TYPE_LENGTH (arg_type);
923 contents = VALUE_CONTENTS (arg);
924 val = extract_signed_integer (contents, len);
925 if (len > 4)
926 {
927 /* put on stack and pass pointers */
928 sp -= len;
929 write_memory (sp, contents, len);
930 ptrs[index++] = sp;
931 }
932 }
933 #endif
934 index = 0;
935
936 for (i = 0; i < nargs; i++)
937 {
938 value_ptr arg = args[i];
939 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
940 len = TYPE_LENGTH (arg_type);
941 contents = VALUE_CONTENTS (arg);
942 if (len > 4)
943 {
944 /* we need multiple registers */
945 int ndx;
946
947 for (ndx = 0; len > 0; ndx += 8, len -= 8)
948 {
949 if (regnum & 1)
950 regnum++; /* all args > 4 bytes start in even register */
951
952 if (regnum < 18)
953 {
954 val = extract_signed_integer (&contents[ndx], 4);
955 write_register (regnum++, val);
956
957 if (len >= 8)
958 val = extract_signed_integer (&contents[ndx + 4], 4);
959 else
960 val = extract_signed_integer (&contents[ndx + 4], len - 4);
961 write_register (regnum++, val);
962 }
963 else
964 {
965 /* no more registers available. put it on the stack */
966
967 /* all args > 4 bytes are padded to a multiple of 8 bytes
968 and start on an 8 byte boundary */
969 if (sp & 7)
970 sp -= (sp & 7); /* align it */
971
972 sp -= ((len + 7) & ~7); /* allocate space */
973 write_memory (sp, &contents[ndx], len);
974 break;
975 }
976 }
977 }
978 else
979 {
980 if (regnum < 18)
981 {
982 val = extract_signed_integer (contents, len);
983 write_register (regnum++, val);
984 }
985 else
986 {
987 /* all args are padded to a multiple of 4 bytes (at least) */
988 sp -= ((len + 3) & ~3);
989 write_memory (sp, contents, len);
990 }
991 }
992 }
993 if (sp & 7)
994 /* stack pointer is not on an 8 byte boundary -- align it */
995 sp -= (sp & 7);
996 return sp;
997 }
998
999
1000 /* pick an out-of-the-way place to set the return value */
1001 /* for an inferior function call. The link register is set to this */
1002 /* value and a momentary breakpoint is set there. When the breakpoint */
1003 /* is hit, the dummy frame is popped and the previous environment is */
1004 /* restored. */
1005
1006 CORE_ADDR
1007 d30v_call_dummy_address (void)
1008 {
1009 CORE_ADDR entry;
1010 struct minimal_symbol *sym;
1011
1012 entry = entry_point_address ();
1013
1014 if (entry != 0)
1015 return entry;
1016
1017 sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile);
1018
1019 if (!sym || MSYMBOL_TYPE (sym) != mst_text)
1020 return 0;
1021 else
1022 return SYMBOL_VALUE_ADDRESS (sym);
1023 }
1024
1025 /* Given a return value in `regbuf' with a type `valtype',
1026 extract and copy its value into `valbuf'. */
1027
1028 void
1029 d30v_extract_return_value (struct type *valtype, char regbuf[REGISTER_BYTES],
1030 char *valbuf)
1031 {
1032 memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype));
1033 }
1034
1035 /* The following code implements access to, and display of, the D30V's
1036 instruction trace buffer. The buffer consists of 64K or more
1037 4-byte words of data, of which each words includes an 8-bit count,
1038 an 8-bit segment number, and a 16-bit instruction address.
1039
1040 In theory, the trace buffer is continuously capturing instruction
1041 data that the CPU presents on its "debug bus", but in practice, the
1042 ROMified GDB stub only enables tracing when it continues or steps
1043 the program, and stops tracing when the program stops; so it
1044 actually works for GDB to read the buffer counter out of memory and
1045 then read each trace word. The counter records where the tracing
1046 stops, but there is no record of where it started, so we remember
1047 the PC when we resumed and then search backwards in the trace
1048 buffer for a word that includes that address. This is not perfect,
1049 because you will miss trace data if the resumption PC is the target
1050 of a branch. (The value of the buffer counter is semi-random, any
1051 trace data from a previous program stop is gone.) */
1052
1053 /* The address of the last word recorded in the trace buffer. */
1054
1055 #define DBBC_ADDR (0xd80000)
1056
1057 /* The base of the trace buffer, at least for the "Board_0". */
1058
1059 #define TRACE_BUFFER_BASE (0xf40000)
1060
1061 static void trace_command (char *, int);
1062
1063 static void untrace_command (char *, int);
1064
1065 static void trace_info (char *, int);
1066
1067 static void tdisassemble_command (char *, int);
1068
1069 static void display_trace (int, int);
1070
1071 /* True when instruction traces are being collected. */
1072
1073 static int tracing;
1074
1075 /* Remembered PC. */
1076
1077 static CORE_ADDR last_pc;
1078
1079 /* True when trace output should be displayed whenever program stops. */
1080
1081 static int trace_display;
1082
1083 /* True when trace listing should include source lines. */
1084
1085 static int default_trace_show_source = 1;
1086
1087 struct trace_buffer
1088 {
1089 int size;
1090 short *counts;
1091 CORE_ADDR *addrs;
1092 }
1093 trace_data;
1094
1095 static void
1096 trace_command (char *args, int from_tty)
1097 {
1098 /* Clear the host-side trace buffer, allocating space if needed. */
1099 trace_data.size = 0;
1100 if (trace_data.counts == NULL)
1101 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1102 if (trace_data.addrs == NULL)
1103 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1104
1105 tracing = 1;
1106
1107 printf_filtered ("Tracing is now on.\n");
1108 }
1109
1110 static void
1111 untrace_command (char *args, int from_tty)
1112 {
1113 tracing = 0;
1114
1115 printf_filtered ("Tracing is now off.\n");
1116 }
1117
1118 static void
1119 trace_info (char *args, int from_tty)
1120 {
1121 int i;
1122
1123 if (trace_data.size)
1124 {
1125 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1126
1127 for (i = 0; i < trace_data.size; ++i)
1128 {
1129 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1130 i, trace_data.counts[i],
1131 (trace_data.counts[i] == 1 ? "" : "s"),
1132 paddr_nz (trace_data.addrs[i]));
1133 }
1134 }
1135 else
1136 printf_filtered ("No entries in trace buffer.\n");
1137
1138 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1139 }
1140
1141 /* Print the instruction at address MEMADDR in debugged memory,
1142 on STREAM. Returns length of the instruction, in bytes. */
1143
1144 static int
1145 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1146 {
1147 /* If there's no disassembler, something is very wrong. */
1148 if (tm_print_insn == NULL)
1149 internal_error (__FILE__, __LINE__,
1150 "print_insn: no disassembler");
1151
1152 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1153 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1154 else
1155 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1156 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1157 }
1158
1159 void
1160 d30v_eva_prepare_to_trace (void)
1161 {
1162 if (!tracing)
1163 return;
1164
1165 last_pc = read_register (PC_REGNUM);
1166 }
1167
1168 /* Collect trace data from the target board and format it into a form
1169 more useful for display. */
1170
1171 void
1172 d30v_eva_get_trace_data (void)
1173 {
1174 int count, i, j, oldsize;
1175 int trace_addr, trace_seg, trace_cnt, next_cnt;
1176 unsigned int last_trace, trace_word, next_word;
1177 unsigned int *tmpspace;
1178
1179 if (!tracing)
1180 return;
1181
1182 tmpspace = xmalloc (65536 * sizeof (unsigned int));
1183
1184 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1185
1186 /* Collect buffer contents from the target, stopping when we reach
1187 the word recorded when execution resumed. */
1188
1189 count = 0;
1190 while (last_trace > 0)
1191 {
1192 QUIT;
1193 trace_word =
1194 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1195 trace_addr = trace_word & 0xffff;
1196 last_trace -= 4;
1197 /* Ignore an apparently nonsensical entry. */
1198 if (trace_addr == 0xffd5)
1199 continue;
1200 tmpspace[count++] = trace_word;
1201 if (trace_addr == last_pc)
1202 break;
1203 if (count > 65535)
1204 break;
1205 }
1206
1207 /* Move the data to the host-side trace buffer, adjusting counts to
1208 include the last instruction executed and transforming the address
1209 into something that GDB likes. */
1210
1211 for (i = 0; i < count; ++i)
1212 {
1213 trace_word = tmpspace[i];
1214 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1215 trace_addr = trace_word & 0xffff;
1216 next_cnt = (next_word >> 24) & 0xff;
1217 j = trace_data.size + count - i - 1;
1218 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1219 trace_data.counts[j] = next_cnt + 1;
1220 }
1221
1222 oldsize = trace_data.size;
1223 trace_data.size += count;
1224
1225 xfree (tmpspace);
1226
1227 if (trace_display)
1228 display_trace (oldsize, trace_data.size);
1229 }
1230
1231 static void
1232 tdisassemble_command (char *arg, int from_tty)
1233 {
1234 int i, count;
1235 CORE_ADDR low, high;
1236 char *space_index;
1237
1238 if (!arg)
1239 {
1240 low = 0;
1241 high = trace_data.size;
1242 }
1243 else if (!(space_index = (char *) strchr (arg, ' ')))
1244 {
1245 low = parse_and_eval_address (arg);
1246 high = low + 5;
1247 }
1248 else
1249 {
1250 /* Two arguments. */
1251 *space_index = '\0';
1252 low = parse_and_eval_address (arg);
1253 high = parse_and_eval_address (space_index + 1);
1254 if (high < low)
1255 high = low;
1256 }
1257
1258 printf_filtered ("Dump of trace from %s to %s:\n",
1259 paddr_u (low),
1260 paddr_u (high));
1261
1262 display_trace (low, high);
1263
1264 printf_filtered ("End of trace dump.\n");
1265 gdb_flush (gdb_stdout);
1266 }
1267
1268 static void
1269 display_trace (int low, int high)
1270 {
1271 int i, count, trace_show_source, first, suppress;
1272 CORE_ADDR next_address;
1273
1274 trace_show_source = default_trace_show_source;
1275 if (!have_full_symbols () && !have_partial_symbols ())
1276 {
1277 trace_show_source = 0;
1278 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1279 printf_filtered ("Trace will not display any source.\n");
1280 }
1281
1282 first = 1;
1283 suppress = 0;
1284 for (i = low; i < high; ++i)
1285 {
1286 next_address = trace_data.addrs[i];
1287 count = trace_data.counts[i];
1288 while (count-- > 0)
1289 {
1290 QUIT;
1291 if (trace_show_source)
1292 {
1293 struct symtab_and_line sal, sal_prev;
1294
1295 sal_prev = find_pc_line (next_address - 4, 0);
1296 sal = find_pc_line (next_address, 0);
1297
1298 if (sal.symtab)
1299 {
1300 if (first || sal.line != sal_prev.line)
1301 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1302 suppress = 0;
1303 }
1304 else
1305 {
1306 if (!suppress)
1307 /* FIXME-32x64--assumes sal.pc fits in long. */
1308 printf_filtered ("No source file for address %s.\n",
1309 local_hex_string ((unsigned long) sal.pc));
1310 suppress = 1;
1311 }
1312 }
1313 first = 0;
1314 print_address (next_address, gdb_stdout);
1315 printf_filtered (":");
1316 printf_filtered ("\t");
1317 wrap_here (" ");
1318 next_address = next_address + print_insn (next_address, gdb_stdout);
1319 printf_filtered ("\n");
1320 gdb_flush (gdb_stdout);
1321 }
1322 }
1323 }
1324
1325 extern void (*target_resume_hook) (void);
1326 extern void (*target_wait_loop_hook) (void);
1327
1328 void
1329 _initialize_d30v_tdep (void)
1330 {
1331 tm_print_insn = print_insn_d30v;
1332
1333 target_resume_hook = d30v_eva_prepare_to_trace;
1334 target_wait_loop_hook = d30v_eva_get_trace_data;
1335
1336 add_info ("flags", print_flags_command, "Print d30v flags.");
1337
1338 add_com ("trace", class_support, trace_command,
1339 "Enable tracing of instruction execution.");
1340
1341 add_com ("untrace", class_support, untrace_command,
1342 "Disable tracing of instruction execution.");
1343
1344 add_com ("tdisassemble", class_vars, tdisassemble_command,
1345 "Disassemble the trace buffer.\n\
1346 Two optional arguments specify a range of trace buffer entries\n\
1347 as reported by info trace (NOT addresses!).");
1348
1349 add_info ("trace", trace_info,
1350 "Display info about the trace data buffer.");
1351
1352 add_show_from_set (add_set_cmd ("tracedisplay", no_class,
1353 var_integer, (char *) &trace_display,
1354 "Set automatic display of trace.\n", &setlist),
1355 &showlist);
1356 add_show_from_set (add_set_cmd ("tracesource", no_class,
1357 var_integer, (char *) &default_trace_show_source,
1358 "Set display of source code with trace.\n", &setlist),
1359 &showlist);
1360
1361 }
GDB Binutils - Deliverables
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