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Create new file regcache.h. Update all uses.
[deliverable/binutils-gdb.git] / gdb / d30v-tdep.c
1 /* Target-dependent code for Mitsubishi D30V, for GDB.
2 Copyright (C) 1996, 1997, 2000, 2001 Free Software Foundation, Inc.
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21 /* Contributed by Martin Hunt, hunt@cygnus.com */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "obstack.h"
26 #include "symtab.h"
27 #include "gdbtypes.h"
28 #include "gdbcmd.h"
29 #include "gdbcore.h"
30 #include "gdb_string.h"
31 #include "value.h"
32 #include "inferior.h"
33 #include "dis-asm.h"
34 #include "symfile.h"
35 #include "objfiles.h"
36 #include "regcache.h"
37
38 #include "language.h" /* For local_hex_string() */
39
40 void d30v_frame_find_saved_regs (struct frame_info *fi,
41 struct frame_saved_regs *fsr);
42 void d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
43 struct frame_saved_regs *fsr);
44 static void d30v_pop_dummy_frame (struct frame_info *fi);
45 static void d30v_print_flags (void);
46 static void print_flags_command (char *, int);
47
48 /* the following defines assume:
49 fp is r61, lr is r62, sp is r63, and ?? is r22
50 if that changes, they will need to be updated */
51
52 #define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */
53
54 #define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */
55 #define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */
56 #define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */
57 #define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */
58
59 #define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */
60 #define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */
61 #define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */
62 #define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */
63
64 #define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */
65 #define OP_NOP 0x00f00000 /* nop */
66
67 #define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */
68 #define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */
69 #define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */
70 #define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */
71 #define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */
72 #define OP_OR_SP_R0_IMM 0x03abf000 /* or sp,r0,imm */
73
74 /* no mask */
75 #define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */
76 #define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */
77 #define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */
78 #define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */
79 #define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */
80
81 #define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */
82 #define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */
83 #define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */
84 #define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */
85 #define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */
86
87 #define OP_MASK_FM_BIT 0x80000000
88 #define OP_MASK_CC_BITS 0x70000000
89 #define OP_MASK_SUB_INST 0x0fffffff
90
91 #define EXTRACT_RA(op) (((op) >> 12) & 0x3f)
92 #define EXTRACT_RB(op) (((op) >> 6) & 0x3f)
93 #define EXTRACT_RC(op) (((op) & 0x3f)
94 #define EXTRACT_UIMM6(op) ((op) & 0x3f)
95 #define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26)
96 #define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff))
97 #define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr))
98
99
100 int
101 d30v_frame_chain_valid (CORE_ADDR chain, struct frame_info *fi)
102 {
103 #if 0
104 return ((chain) != 0 && (fi) != 0 && (fi)->return_pc != 0);
105 #else
106 return ((chain) != 0 && (fi) != 0 && (fi)->frame <= chain);
107 #endif
108 }
109
110 /* Discard from the stack the innermost frame, restoring all saved
111 registers. */
112
113 void
114 d30v_pop_frame (void)
115 {
116 struct frame_info *frame = get_current_frame ();
117 CORE_ADDR fp;
118 int regnum;
119 struct frame_saved_regs fsr;
120 char raw_buffer[8];
121
122 fp = FRAME_FP (frame);
123 if (frame->dummy)
124 {
125 d30v_pop_dummy_frame (frame);
126 return;
127 }
128
129 /* fill out fsr with the address of where each */
130 /* register was stored in the frame */
131 get_frame_saved_regs (frame, &fsr);
132
133 /* now update the current registers with the old values */
134 for (regnum = A0_REGNUM; regnum < A0_REGNUM + 2; regnum++)
135 {
136 if (fsr.regs[regnum])
137 {
138 read_memory (fsr.regs[regnum], raw_buffer, 8);
139 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8);
140 }
141 }
142 for (regnum = 0; regnum < SP_REGNUM; regnum++)
143 {
144 if (fsr.regs[regnum])
145 {
146 write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4));
147 }
148 }
149 if (fsr.regs[PSW_REGNUM])
150 {
151 write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4));
152 }
153
154 write_register (PC_REGNUM, read_register (LR_REGNUM));
155 write_register (SP_REGNUM, fp + frame->size);
156 target_store_registers (-1);
157 flush_cached_frames ();
158 }
159
160 static int
161 check_prologue (unsigned long op)
162 {
163 /* add sp,sp,imm -- observed */
164 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
165 return 1;
166
167 /* add r22,sp,imm -- observed */
168 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
169 return 1;
170
171 /* or fp,r0,sp -- observed */
172 if (op == OP_OR_FP_R0_SP)
173 return 1;
174
175 /* nop */
176 if ((op & OP_MASK_OPCODE) == OP_NOP)
177 return 1;
178
179 /* stw Ra,@(sp,r0) */
180 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0)
181 return 1;
182
183 /* stw Ra,@(sp,0x0) */
184 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)
185 return 1;
186
187 /* st2w Ra,@(sp,r0) */
188 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0)
189 return 1;
190
191 /* st2w Ra,@(sp,0x0) */
192 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)
193 return 1;
194
195 /* stw fp, @(r22+,r0) -- observed */
196 if (op == OP_STW_FP_R22P_R0)
197 return 1;
198
199 /* stw r62, @(r22+,r0) -- observed */
200 if (op == OP_STW_LR_R22P_R0)
201 return 1;
202
203 /* stw Ra, @(fp,r0) -- observed */
204 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
205 return 1; /* first arg */
206
207 /* stw Ra, @(fp,imm) -- observed */
208 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
209 return 1; /* second and subsequent args */
210
211 /* stw fp,@(sp,imm) -- observed */
212 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
213 return 1;
214
215 /* st2w Ra,@(r22+,r0) */
216 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
217 return 1;
218
219 /* stw Ra, @(sp-) */
220 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
221 return 1;
222
223 /* st2w Ra, @(sp-) */
224 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
225 return 1;
226
227 /* sub.? sp,sp,imm */
228 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
229 return 1;
230
231 return 0;
232 }
233
234 CORE_ADDR
235 d30v_skip_prologue (CORE_ADDR pc)
236 {
237 unsigned long op[2];
238 unsigned long opl, opr; /* left / right sub operations */
239 unsigned long fm0, fm1; /* left / right mode bits */
240 unsigned long cc0, cc1;
241 unsigned long op1, op2;
242 CORE_ADDR func_addr, func_end;
243 struct symtab_and_line sal;
244
245 /* If we have line debugging information, then the end of the */
246 /* prologue should the first assembly instruction of the first source line */
247 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
248 {
249 sal = find_pc_line (func_addr, 0);
250 if (sal.end && sal.end < func_end)
251 return sal.end;
252 }
253
254 if (target_read_memory (pc, (char *) &op[0], 8))
255 return pc; /* Can't access it -- assume no prologue. */
256
257 while (1)
258 {
259 opl = (unsigned long) read_memory_integer (pc, 4);
260 opr = (unsigned long) read_memory_integer (pc + 4, 4);
261
262 fm0 = (opl & OP_MASK_FM_BIT);
263 fm1 = (opr & OP_MASK_FM_BIT);
264
265 cc0 = (opl & OP_MASK_CC_BITS);
266 cc1 = (opr & OP_MASK_CC_BITS);
267
268 opl = (opl & OP_MASK_SUB_INST);
269 opr = (opr & OP_MASK_SUB_INST);
270
271 if (fm0 && fm1)
272 {
273 /* long instruction (opl contains the opcode) */
274 if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */
275 ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */
276 ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */
277 ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */
278 break;
279 }
280 else
281 {
282 /* short instructions */
283 if (fm0 && !fm1)
284 {
285 op1 = opr;
286 op2 = opl;
287 }
288 else
289 {
290 op1 = opl;
291 op2 = opr;
292 }
293 if (check_prologue (op1))
294 {
295 if (!check_prologue (op2))
296 {
297 /* if the previous opcode was really part of the prologue */
298 /* and not just a NOP, then we want to break after both instructions */
299 if ((op1 & OP_MASK_OPCODE) != OP_NOP)
300 pc += 8;
301 break;
302 }
303 }
304 else
305 break;
306 }
307 pc += 8;
308 }
309 return pc;
310 }
311
312 static int end_of_stack;
313
314 /* Given a GDB frame, determine the address of the calling function's frame.
315 This will be used to create a new GDB frame struct, and then
316 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
317 */
318
319 CORE_ADDR
320 d30v_frame_chain (struct frame_info *frame)
321 {
322 struct frame_saved_regs fsr;
323
324 d30v_frame_find_saved_regs (frame, &fsr);
325
326 if (end_of_stack)
327 return (CORE_ADDR) 0;
328
329 if (frame->return_pc == IMEM_START)
330 return (CORE_ADDR) 0;
331
332 if (!fsr.regs[FP_REGNUM])
333 {
334 if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START)
335 return (CORE_ADDR) 0;
336
337 return fsr.regs[SP_REGNUM];
338 }
339
340 if (!read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4))
341 return (CORE_ADDR) 0;
342
343 return read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4);
344 }
345
346 static int next_addr, uses_frame;
347 static int frame_size;
348
349 static int
350 prologue_find_regs (unsigned long op, struct frame_saved_regs *fsr,
351 CORE_ADDR addr)
352 {
353 int n;
354 int offset;
355
356 /* add sp,sp,imm -- observed */
357 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
358 {
359 offset = EXTRACT_IMM6 (op);
360 /*next_addr += offset; */
361 frame_size += -offset;
362 return 1;
363 }
364
365 /* add r22,sp,imm -- observed */
366 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
367 {
368 offset = EXTRACT_IMM6 (op);
369 next_addr = (offset - frame_size);
370 return 1;
371 }
372
373 /* stw Ra, @(fp, offset) -- observed */
374 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
375 {
376 n = EXTRACT_RA (op);
377 offset = EXTRACT_IMM6 (op);
378 fsr->regs[n] = (offset - frame_size);
379 return 1;
380 }
381
382 /* stw Ra, @(fp, r0) -- observed */
383 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
384 {
385 n = EXTRACT_RA (op);
386 fsr->regs[n] = (-frame_size);
387 return 1;
388 }
389
390 /* or fp,0,sp -- observed */
391 if ((op == OP_OR_FP_R0_SP) ||
392 (op == OP_OR_FP_SP_R0) ||
393 (op == OP_OR_FP_IMM0_SP))
394 {
395 uses_frame = 1;
396 return 1;
397 }
398
399 /* nop */
400 if ((op & OP_MASK_OPCODE) == OP_NOP)
401 return 1;
402
403 /* stw Ra,@(r22+,r0) -- observed */
404 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0)
405 {
406 n = EXTRACT_RA (op);
407 fsr->regs[n] = next_addr;
408 next_addr += 4;
409 return 1;
410 }
411 #if 0 /* subsumed in pattern above */
412 /* stw fp,@(r22+,r0) -- observed */
413 if (op == OP_STW_FP_R22P_R0)
414 {
415 fsr->regs[FP_REGNUM] = next_addr; /* XXX */
416 next_addr += 4;
417 return 1;
418 }
419
420 /* stw r62,@(r22+,r0) -- observed */
421 if (op == OP_STW_LR_R22P_R0)
422 {
423 fsr->regs[LR_REGNUM] = next_addr;
424 next_addr += 4;
425 return 1;
426 }
427 #endif
428 /* st2w Ra,@(r22+,r0) -- observed */
429 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
430 {
431 n = EXTRACT_RA (op);
432 fsr->regs[n] = next_addr;
433 fsr->regs[n + 1] = next_addr + 4;
434 next_addr += 8;
435 return 1;
436 }
437
438 /* stw rn, @(sp-) */
439 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
440 {
441 n = EXTRACT_RA (op);
442 fsr->regs[n] = next_addr;
443 next_addr -= 4;
444 return 1;
445 }
446
447 /* st2w Ra, @(sp-) */
448 else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
449 {
450 n = EXTRACT_RA (op);
451 fsr->regs[n] = next_addr;
452 fsr->regs[n + 1] = next_addr + 4;
453 next_addr -= 8;
454 return 1;
455 }
456
457 /* sub sp,sp,imm */
458 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
459 {
460 offset = EXTRACT_IMM6 (op);
461 frame_size += -offset;
462 return 1;
463 }
464
465 /* st rn, @(sp,0) -- observed */
466 if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) ||
467 ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0))
468 {
469 n = EXTRACT_RA (op);
470 fsr->regs[n] = (-frame_size);
471 return 1;
472 }
473
474 /* st2w rn, @(sp,0) */
475 if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) ||
476 ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0))
477 {
478 n = EXTRACT_RA (op);
479 fsr->regs[n] = (-frame_size);
480 fsr->regs[n + 1] = (-frame_size) + 4;
481 return 1;
482 }
483
484 /* stw fp,@(sp,imm) -- observed */
485 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
486 {
487 offset = EXTRACT_IMM6 (op);
488 fsr->regs[FP_REGNUM] = (offset - frame_size);
489 return 1;
490 }
491 return 0;
492 }
493
494 /* Put here the code to store, into a struct frame_saved_regs, the
495 addresses of the saved registers of frame described by FRAME_INFO.
496 This includes special registers such as pc and fp saved in special
497 ways in the stack frame. sp is even more special: the address we
498 return for it IS the sp for the next frame. */
499 void
500 d30v_frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr)
501 {
502 CORE_ADDR fp, pc;
503 unsigned long opl, opr;
504 unsigned long op1, op2;
505 unsigned long fm0, fm1;
506 int i;
507
508 fp = fi->frame;
509 memset (fsr, 0, sizeof (*fsr));
510 next_addr = 0;
511 frame_size = 0;
512 end_of_stack = 0;
513
514 uses_frame = 0;
515
516 d30v_frame_find_saved_regs_offsets (fi, fsr);
517
518 fi->size = frame_size;
519
520 if (!fp)
521 fp = read_register (SP_REGNUM);
522
523 for (i = 0; i < NUM_REGS - 1; i++)
524 if (fsr->regs[i])
525 {
526 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
527 }
528
529 if (fsr->regs[LR_REGNUM])
530 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
531 else
532 fi->return_pc = read_register (LR_REGNUM);
533
534 /* the SP is not normally (ever?) saved, but check anyway */
535 if (!fsr->regs[SP_REGNUM])
536 {
537 /* if the FP was saved, that means the current FP is valid, */
538 /* otherwise, it isn't being used, so we use the SP instead */
539 if (uses_frame)
540 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
541 else
542 {
543 fsr->regs[SP_REGNUM] = fp + fi->size;
544 fi->frameless = 1;
545 fsr->regs[FP_REGNUM] = 0;
546 }
547 }
548 }
549
550 void
551 d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
552 struct frame_saved_regs *fsr)
553 {
554 CORE_ADDR fp, pc;
555 unsigned long opl, opr;
556 unsigned long op1, op2;
557 unsigned long fm0, fm1;
558 int i;
559
560 fp = fi->frame;
561 memset (fsr, 0, sizeof (*fsr));
562 next_addr = 0;
563 frame_size = 0;
564 end_of_stack = 0;
565
566 pc = get_pc_function_start (fi->pc);
567
568 uses_frame = 0;
569 while (pc < fi->pc)
570 {
571 opl = (unsigned long) read_memory_integer (pc, 4);
572 opr = (unsigned long) read_memory_integer (pc + 4, 4);
573
574 fm0 = (opl & OP_MASK_FM_BIT);
575 fm1 = (opr & OP_MASK_FM_BIT);
576
577 opl = (opl & OP_MASK_SUB_INST);
578 opr = (opr & OP_MASK_SUB_INST);
579
580 if (fm0 && fm1)
581 {
582 /* long instruction */
583 if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
584 {
585 /* add sp,sp,n */
586 long offset = EXTRACT_IMM32 (opl, opr);
587 frame_size += -offset;
588 }
589 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
590 {
591 /* add r22,sp,offset */
592 long offset = EXTRACT_IMM32 (opl, opr);
593 next_addr = (offset - frame_size);
594 }
595 else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM)
596 {
597 /* st Ra, @(sp,imm) */
598 long offset = EXTRACT_IMM32 (opl, opr);
599 short n = EXTRACT_RA (opl);
600 fsr->regs[n] = (offset - frame_size);
601 }
602 else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM)
603 {
604 /* st2w Ra, @(sp,offset) */
605 long offset = EXTRACT_IMM32 (opl, opr);
606 short n = EXTRACT_RA (opl);
607 fsr->regs[n] = (offset - frame_size);
608 fsr->regs[n + 1] = (offset - frame_size) + 4;
609 }
610 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_OR_SP_R0_IMM)
611 {
612 end_of_stack = 1;
613 }
614 else
615 break;
616 }
617 else
618 {
619 /* short instructions */
620 if (fm0 && !fm1)
621 {
622 op2 = opl;
623 op1 = opr;
624 }
625 else
626 {
627 op1 = opl;
628 op2 = opr;
629 }
630 if (!prologue_find_regs (op1, fsr, pc) || !prologue_find_regs (op2, fsr, pc))
631 break;
632 }
633 pc += 8;
634 }
635
636 #if 0
637 fi->size = frame_size;
638
639 if (!fp)
640 fp = read_register (SP_REGNUM);
641
642 for (i = 0; i < NUM_REGS - 1; i++)
643 if (fsr->regs[i])
644 {
645 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
646 }
647
648 if (fsr->regs[LR_REGNUM])
649 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
650 else
651 fi->return_pc = read_register (LR_REGNUM);
652
653 /* the SP is not normally (ever?) saved, but check anyway */
654 if (!fsr->regs[SP_REGNUM])
655 {
656 /* if the FP was saved, that means the current FP is valid, */
657 /* otherwise, it isn't being used, so we use the SP instead */
658 if (uses_frame)
659 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
660 else
661 {
662 fsr->regs[SP_REGNUM] = fp + fi->size;
663 fi->frameless = 1;
664 fsr->regs[FP_REGNUM] = 0;
665 }
666 }
667 #endif
668 }
669
670 void
671 d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
672 {
673 struct frame_saved_regs dummy;
674
675 if (fi->next && (fi->pc == 0))
676 fi->pc = fi->next->return_pc;
677
678 d30v_frame_find_saved_regs_offsets (fi, &dummy);
679
680 if (uses_frame == 0)
681 fi->frameless = 1;
682 else
683 fi->frameless = 0;
684
685 if ((fi->next == 0) && (uses_frame == 0))
686 /* innermost frame and it's "frameless",
687 so the fi->frame field is wrong, fix it! */
688 fi->frame = read_sp ();
689
690 if (dummy.regs[LR_REGNUM])
691 {
692 /* it was saved, grab it! */
693 dummy.regs[LR_REGNUM] += (fi->frame + frame_size);
694 fi->return_pc = read_memory_unsigned_integer (dummy.regs[LR_REGNUM], 4);
695 }
696 else
697 fi->return_pc = read_register (LR_REGNUM);
698 }
699
700 void
701 d30v_init_frame_pc (int fromleaf, struct frame_info *prev)
702 {
703 /* default value, put here so we can breakpoint on it and
704 see if the default value is really the right thing to use */
705 prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
706 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
707 }
708
709 static void d30v_print_register (int regnum, int tabular);
710
711 static void
712 d30v_print_register (int regnum, int tabular)
713 {
714 if (regnum < A0_REGNUM)
715 {
716 if (tabular)
717 printf_filtered ("%08lx", (long) read_register (regnum));
718 else
719 printf_filtered ("0x%lx %ld",
720 (long) read_register (regnum),
721 (long) read_register (regnum));
722 }
723 else
724 {
725 char regbuf[MAX_REGISTER_RAW_SIZE];
726
727 read_relative_register_raw_bytes (regnum, regbuf);
728
729 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
730 gdb_stdout, 'x', 1, 0, Val_pretty_default);
731
732 if (!tabular)
733 {
734 printf_filtered (" ");
735 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
736 gdb_stdout, 'd', 1, 0, Val_pretty_default);
737 }
738 }
739 }
740
741 static void
742 d30v_print_flags (void)
743 {
744 long psw = read_register (PSW_REGNUM);
745 printf_filtered ("flags #1");
746 printf_filtered (" (sm) %d", (psw & PSW_SM) != 0);
747 printf_filtered (" (ea) %d", (psw & PSW_EA) != 0);
748 printf_filtered (" (db) %d", (psw & PSW_DB) != 0);
749 printf_filtered (" (ds) %d", (psw & PSW_DS) != 0);
750 printf_filtered (" (ie) %d", (psw & PSW_IE) != 0);
751 printf_filtered (" (rp) %d", (psw & PSW_RP) != 0);
752 printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0);
753
754 printf_filtered ("flags #2");
755 printf_filtered (" (f0) %d", (psw & PSW_F0) != 0);
756 printf_filtered (" (f1) %d", (psw & PSW_F1) != 0);
757 printf_filtered (" (f2) %d", (psw & PSW_F2) != 0);
758 printf_filtered (" (f3) %d", (psw & PSW_F3) != 0);
759 printf_filtered (" (s) %d", (psw & PSW_S) != 0);
760 printf_filtered (" (v) %d", (psw & PSW_V) != 0);
761 printf_filtered (" (va) %d", (psw & PSW_VA) != 0);
762 printf_filtered (" (c) %d\n", (psw & PSW_C) != 0);
763 }
764
765 static void
766 print_flags_command (char *args, int from_tty)
767 {
768 d30v_print_flags ();
769 }
770
771 void
772 d30v_do_registers_info (int regnum, int fpregs)
773 {
774 long long num1, num2;
775 long psw;
776
777 if (regnum != -1)
778 {
779 if (REGISTER_NAME (0) == NULL || REGISTER_NAME (0)[0] == '\000')
780 return;
781
782 printf_filtered ("%s ", REGISTER_NAME (regnum));
783 d30v_print_register (regnum, 0);
784
785 printf_filtered ("\n");
786 return;
787 }
788
789 /* Have to print all the registers. Format them nicely. */
790
791 printf_filtered ("PC=");
792 print_address (read_pc (), gdb_stdout);
793
794 printf_filtered (" PSW=");
795 d30v_print_register (PSW_REGNUM, 1);
796
797 printf_filtered (" BPC=");
798 print_address (read_register (BPC_REGNUM), gdb_stdout);
799
800 printf_filtered (" BPSW=");
801 d30v_print_register (BPSW_REGNUM, 1);
802 printf_filtered ("\n");
803
804 printf_filtered ("DPC=");
805 print_address (read_register (DPC_REGNUM), gdb_stdout);
806
807 printf_filtered (" DPSW=");
808 d30v_print_register (DPSW_REGNUM, 1);
809
810 printf_filtered (" IBA=");
811 print_address (read_register (IBA_REGNUM), gdb_stdout);
812 printf_filtered ("\n");
813
814 printf_filtered ("RPT_C=");
815 d30v_print_register (RPT_C_REGNUM, 1);
816
817 printf_filtered (" RPT_S=");
818 print_address (read_register (RPT_S_REGNUM), gdb_stdout);
819
820 printf_filtered (" RPT_E=");
821 print_address (read_register (RPT_E_REGNUM), gdb_stdout);
822 printf_filtered ("\n");
823
824 printf_filtered ("MOD_S=");
825 print_address (read_register (MOD_S_REGNUM), gdb_stdout);
826
827 printf_filtered (" MOD_E=");
828 print_address (read_register (MOD_E_REGNUM), gdb_stdout);
829 printf_filtered ("\n");
830
831 printf_filtered ("EIT_VB=");
832 print_address (read_register (EIT_VB_REGNUM), gdb_stdout);
833
834 printf_filtered (" INT_S=");
835 d30v_print_register (INT_S_REGNUM, 1);
836
837 printf_filtered (" INT_M=");
838 d30v_print_register (INT_M_REGNUM, 1);
839 printf_filtered ("\n");
840
841 d30v_print_flags ();
842 for (regnum = 0; regnum <= 63;)
843 {
844 int i;
845
846 printf_filtered ("R%d-R%d ", regnum, regnum + 7);
847 if (regnum < 10)
848 printf_filtered (" ");
849 if (regnum + 7 < 10)
850 printf_filtered (" ");
851
852 for (i = 0; i < 8; i++)
853 {
854 printf_filtered (" ");
855 d30v_print_register (regnum++, 1);
856 }
857
858 printf_filtered ("\n");
859 }
860
861 printf_filtered ("A0-A1 ");
862
863 d30v_print_register (A0_REGNUM, 1);
864 printf_filtered (" ");
865 d30v_print_register (A1_REGNUM, 1);
866 printf_filtered ("\n");
867 }
868
869 CORE_ADDR
870 d30v_fix_call_dummy (char *dummyname, CORE_ADDR start_sp, CORE_ADDR fun,
871 int nargs, value_ptr *args, struct type *type, int gcc_p)
872 {
873 int regnum;
874 CORE_ADDR sp;
875 char buffer[MAX_REGISTER_RAW_SIZE];
876 struct frame_info *frame = get_current_frame ();
877 frame->dummy = start_sp;
878 /*start_sp |= DMEM_START; */
879
880 sp = start_sp;
881 for (regnum = 0; regnum < NUM_REGS; regnum++)
882 {
883 sp -= REGISTER_RAW_SIZE (regnum);
884 store_address (buffer, REGISTER_RAW_SIZE (regnum), read_register (regnum));
885 write_memory (sp, buffer, REGISTER_RAW_SIZE (regnum));
886 }
887 write_register (SP_REGNUM, (LONGEST) sp);
888 /* now we need to load LR with the return address */
889 write_register (LR_REGNUM, (LONGEST) d30v_call_dummy_address ());
890 return sp;
891 }
892
893 static void
894 d30v_pop_dummy_frame (struct frame_info *fi)
895 {
896 CORE_ADDR sp = fi->dummy;
897 int regnum;
898
899 for (regnum = 0; regnum < NUM_REGS; regnum++)
900 {
901 sp -= REGISTER_RAW_SIZE (regnum);
902 write_register (regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE (regnum)));
903 }
904 flush_cached_frames (); /* needed? */
905 }
906
907
908 CORE_ADDR
909 d30v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp,
910 int struct_return, CORE_ADDR struct_addr)
911 {
912 int i, len, index = 0, regnum = 2;
913 char buffer[4], *contents;
914 LONGEST val;
915 CORE_ADDR ptrs[10];
916
917 #if 0
918 /* Pass 1. Put all large args on stack */
919 for (i = 0; i < nargs; i++)
920 {
921 value_ptr arg = args[i];
922 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
923 len = TYPE_LENGTH (arg_type);
924 contents = VALUE_CONTENTS (arg);
925 val = extract_signed_integer (contents, len);
926 if (len > 4)
927 {
928 /* put on stack and pass pointers */
929 sp -= len;
930 write_memory (sp, contents, len);
931 ptrs[index++] = sp;
932 }
933 }
934 #endif
935 index = 0;
936
937 for (i = 0; i < nargs; i++)
938 {
939 value_ptr arg = args[i];
940 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
941 len = TYPE_LENGTH (arg_type);
942 contents = VALUE_CONTENTS (arg);
943 if (len > 4)
944 {
945 /* we need multiple registers */
946 int ndx;
947
948 for (ndx = 0; len > 0; ndx += 8, len -= 8)
949 {
950 if (regnum & 1)
951 regnum++; /* all args > 4 bytes start in even register */
952
953 if (regnum < 18)
954 {
955 val = extract_signed_integer (&contents[ndx], 4);
956 write_register (regnum++, val);
957
958 if (len >= 8)
959 val = extract_signed_integer (&contents[ndx + 4], 4);
960 else
961 val = extract_signed_integer (&contents[ndx + 4], len - 4);
962 write_register (regnum++, val);
963 }
964 else
965 {
966 /* no more registers available. put it on the stack */
967
968 /* all args > 4 bytes are padded to a multiple of 8 bytes
969 and start on an 8 byte boundary */
970 if (sp & 7)
971 sp -= (sp & 7); /* align it */
972
973 sp -= ((len + 7) & ~7); /* allocate space */
974 write_memory (sp, &contents[ndx], len);
975 break;
976 }
977 }
978 }
979 else
980 {
981 if (regnum < 18)
982 {
983 val = extract_signed_integer (contents, len);
984 write_register (regnum++, val);
985 }
986 else
987 {
988 /* all args are padded to a multiple of 4 bytes (at least) */
989 sp -= ((len + 3) & ~3);
990 write_memory (sp, contents, len);
991 }
992 }
993 }
994 if (sp & 7)
995 /* stack pointer is not on an 8 byte boundary -- align it */
996 sp -= (sp & 7);
997 return sp;
998 }
999
1000
1001 /* pick an out-of-the-way place to set the return value */
1002 /* for an inferior function call. The link register is set to this */
1003 /* value and a momentary breakpoint is set there. When the breakpoint */
1004 /* is hit, the dummy frame is popped and the previous environment is */
1005 /* restored. */
1006
1007 CORE_ADDR
1008 d30v_call_dummy_address (void)
1009 {
1010 CORE_ADDR entry;
1011 struct minimal_symbol *sym;
1012
1013 entry = entry_point_address ();
1014
1015 if (entry != 0)
1016 return entry;
1017
1018 sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile);
1019
1020 if (!sym || MSYMBOL_TYPE (sym) != mst_text)
1021 return 0;
1022 else
1023 return SYMBOL_VALUE_ADDRESS (sym);
1024 }
1025
1026 /* Given a return value in `regbuf' with a type `valtype',
1027 extract and copy its value into `valbuf'. */
1028
1029 void
1030 d30v_extract_return_value (struct type *valtype, char regbuf[REGISTER_BYTES],
1031 char *valbuf)
1032 {
1033 memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype));
1034 }
1035
1036 /* The following code implements access to, and display of, the D30V's
1037 instruction trace buffer. The buffer consists of 64K or more
1038 4-byte words of data, of which each words includes an 8-bit count,
1039 an 8-bit segment number, and a 16-bit instruction address.
1040
1041 In theory, the trace buffer is continuously capturing instruction
1042 data that the CPU presents on its "debug bus", but in practice, the
1043 ROMified GDB stub only enables tracing when it continues or steps
1044 the program, and stops tracing when the program stops; so it
1045 actually works for GDB to read the buffer counter out of memory and
1046 then read each trace word. The counter records where the tracing
1047 stops, but there is no record of where it started, so we remember
1048 the PC when we resumed and then search backwards in the trace
1049 buffer for a word that includes that address. This is not perfect,
1050 because you will miss trace data if the resumption PC is the target
1051 of a branch. (The value of the buffer counter is semi-random, any
1052 trace data from a previous program stop is gone.) */
1053
1054 /* The address of the last word recorded in the trace buffer. */
1055
1056 #define DBBC_ADDR (0xd80000)
1057
1058 /* The base of the trace buffer, at least for the "Board_0". */
1059
1060 #define TRACE_BUFFER_BASE (0xf40000)
1061
1062 static void trace_command (char *, int);
1063
1064 static void untrace_command (char *, int);
1065
1066 static void trace_info (char *, int);
1067
1068 static void tdisassemble_command (char *, int);
1069
1070 static void display_trace (int, int);
1071
1072 /* True when instruction traces are being collected. */
1073
1074 static int tracing;
1075
1076 /* Remembered PC. */
1077
1078 static CORE_ADDR last_pc;
1079
1080 /* True when trace output should be displayed whenever program stops. */
1081
1082 static int trace_display;
1083
1084 /* True when trace listing should include source lines. */
1085
1086 static int default_trace_show_source = 1;
1087
1088 struct trace_buffer
1089 {
1090 int size;
1091 short *counts;
1092 CORE_ADDR *addrs;
1093 }
1094 trace_data;
1095
1096 static void
1097 trace_command (char *args, int from_tty)
1098 {
1099 /* Clear the host-side trace buffer, allocating space if needed. */
1100 trace_data.size = 0;
1101 if (trace_data.counts == NULL)
1102 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1103 if (trace_data.addrs == NULL)
1104 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1105
1106 tracing = 1;
1107
1108 printf_filtered ("Tracing is now on.\n");
1109 }
1110
1111 static void
1112 untrace_command (char *args, int from_tty)
1113 {
1114 tracing = 0;
1115
1116 printf_filtered ("Tracing is now off.\n");
1117 }
1118
1119 static void
1120 trace_info (char *args, int from_tty)
1121 {
1122 int i;
1123
1124 if (trace_data.size)
1125 {
1126 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1127
1128 for (i = 0; i < trace_data.size; ++i)
1129 {
1130 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1131 i, trace_data.counts[i],
1132 (trace_data.counts[i] == 1 ? "" : "s"),
1133 paddr_nz (trace_data.addrs[i]));
1134 }
1135 }
1136 else
1137 printf_filtered ("No entries in trace buffer.\n");
1138
1139 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1140 }
1141
1142 /* Print the instruction at address MEMADDR in debugged memory,
1143 on STREAM. Returns length of the instruction, in bytes. */
1144
1145 static int
1146 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1147 {
1148 /* If there's no disassembler, something is very wrong. */
1149 if (tm_print_insn == NULL)
1150 internal_error (__FILE__, __LINE__,
1151 "print_insn: no disassembler");
1152
1153 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1154 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1155 else
1156 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1157 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1158 }
1159
1160 void
1161 d30v_eva_prepare_to_trace (void)
1162 {
1163 if (!tracing)
1164 return;
1165
1166 last_pc = read_register (PC_REGNUM);
1167 }
1168
1169 /* Collect trace data from the target board and format it into a form
1170 more useful for display. */
1171
1172 void
1173 d30v_eva_get_trace_data (void)
1174 {
1175 int count, i, j, oldsize;
1176 int trace_addr, trace_seg, trace_cnt, next_cnt;
1177 unsigned int last_trace, trace_word, next_word;
1178 unsigned int *tmpspace;
1179
1180 if (!tracing)
1181 return;
1182
1183 tmpspace = xmalloc (65536 * sizeof (unsigned int));
1184
1185 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1186
1187 /* Collect buffer contents from the target, stopping when we reach
1188 the word recorded when execution resumed. */
1189
1190 count = 0;
1191 while (last_trace > 0)
1192 {
1193 QUIT;
1194 trace_word =
1195 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1196 trace_addr = trace_word & 0xffff;
1197 last_trace -= 4;
1198 /* Ignore an apparently nonsensical entry. */
1199 if (trace_addr == 0xffd5)
1200 continue;
1201 tmpspace[count++] = trace_word;
1202 if (trace_addr == last_pc)
1203 break;
1204 if (count > 65535)
1205 break;
1206 }
1207
1208 /* Move the data to the host-side trace buffer, adjusting counts to
1209 include the last instruction executed and transforming the address
1210 into something that GDB likes. */
1211
1212 for (i = 0; i < count; ++i)
1213 {
1214 trace_word = tmpspace[i];
1215 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1216 trace_addr = trace_word & 0xffff;
1217 next_cnt = (next_word >> 24) & 0xff;
1218 j = trace_data.size + count - i - 1;
1219 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1220 trace_data.counts[j] = next_cnt + 1;
1221 }
1222
1223 oldsize = trace_data.size;
1224 trace_data.size += count;
1225
1226 xfree (tmpspace);
1227
1228 if (trace_display)
1229 display_trace (oldsize, trace_data.size);
1230 }
1231
1232 static void
1233 tdisassemble_command (char *arg, int from_tty)
1234 {
1235 int i, count;
1236 CORE_ADDR low, high;
1237 char *space_index;
1238
1239 if (!arg)
1240 {
1241 low = 0;
1242 high = trace_data.size;
1243 }
1244 else if (!(space_index = (char *) strchr (arg, ' ')))
1245 {
1246 low = parse_and_eval_address (arg);
1247 high = low + 5;
1248 }
1249 else
1250 {
1251 /* Two arguments. */
1252 *space_index = '\0';
1253 low = parse_and_eval_address (arg);
1254 high = parse_and_eval_address (space_index + 1);
1255 if (high < low)
1256 high = low;
1257 }
1258
1259 printf_filtered ("Dump of trace from %s to %s:\n",
1260 paddr_u (low),
1261 paddr_u (high));
1262
1263 display_trace (low, high);
1264
1265 printf_filtered ("End of trace dump.\n");
1266 gdb_flush (gdb_stdout);
1267 }
1268
1269 static void
1270 display_trace (int low, int high)
1271 {
1272 int i, count, trace_show_source, first, suppress;
1273 CORE_ADDR next_address;
1274
1275 trace_show_source = default_trace_show_source;
1276 if (!have_full_symbols () && !have_partial_symbols ())
1277 {
1278 trace_show_source = 0;
1279 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1280 printf_filtered ("Trace will not display any source.\n");
1281 }
1282
1283 first = 1;
1284 suppress = 0;
1285 for (i = low; i < high; ++i)
1286 {
1287 next_address = trace_data.addrs[i];
1288 count = trace_data.counts[i];
1289 while (count-- > 0)
1290 {
1291 QUIT;
1292 if (trace_show_source)
1293 {
1294 struct symtab_and_line sal, sal_prev;
1295
1296 sal_prev = find_pc_line (next_address - 4, 0);
1297 sal = find_pc_line (next_address, 0);
1298
1299 if (sal.symtab)
1300 {
1301 if (first || sal.line != sal_prev.line)
1302 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1303 suppress = 0;
1304 }
1305 else
1306 {
1307 if (!suppress)
1308 /* FIXME-32x64--assumes sal.pc fits in long. */
1309 printf_filtered ("No source file for address %s.\n",
1310 local_hex_string ((unsigned long) sal.pc));
1311 suppress = 1;
1312 }
1313 }
1314 first = 0;
1315 print_address (next_address, gdb_stdout);
1316 printf_filtered (":");
1317 printf_filtered ("\t");
1318 wrap_here (" ");
1319 next_address = next_address + print_insn (next_address, gdb_stdout);
1320 printf_filtered ("\n");
1321 gdb_flush (gdb_stdout);
1322 }
1323 }
1324 }
1325
1326 extern void (*target_resume_hook) (void);
1327 extern void (*target_wait_loop_hook) (void);
1328
1329 void
1330 _initialize_d30v_tdep (void)
1331 {
1332 tm_print_insn = print_insn_d30v;
1333
1334 target_resume_hook = d30v_eva_prepare_to_trace;
1335 target_wait_loop_hook = d30v_eva_get_trace_data;
1336
1337 add_info ("flags", print_flags_command, "Print d30v flags.");
1338
1339 add_com ("trace", class_support, trace_command,
1340 "Enable tracing of instruction execution.");
1341
1342 add_com ("untrace", class_support, untrace_command,
1343 "Disable tracing of instruction execution.");
1344
1345 add_com ("tdisassemble", class_vars, tdisassemble_command,
1346 "Disassemble the trace buffer.\n\
1347 Two optional arguments specify a range of trace buffer entries\n\
1348 as reported by info trace (NOT addresses!).");
1349
1350 add_info ("trace", trace_info,
1351 "Display info about the trace data buffer.");
1352
1353 add_show_from_set (add_set_cmd ("tracedisplay", no_class,
1354 var_integer, (char *) &trace_display,
1355 "Set automatic display of trace.\n", &setlist),
1356 &showlist);
1357 add_show_from_set (add_set_cmd ("tracesource", no_class,
1358 var_integer, (char *) &default_trace_show_source,
1359 "Set display of source code with trace.\n", &setlist),
1360 &showlist);
1361
1362 }
GDB Binutils - Deliverables
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