1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "gdb_string.h"
25 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
32 #include "gdb_assert.h"
33 #include "sim-regno.h"
34 #include "gdb/sim-frv.h"
35 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
44 extern void _initialize_frv_tdep (void);
46 struct frv_unwind_cache
/* was struct frame_extra_info */
48 /* The previous frame's inner-most stack address. Used as this
49 frame ID's stack_addr. */
52 /* The frame's base, optionally used by the high-level debug info. */
55 /* Table indicating the location of each and every register. */
56 struct trad_frame_saved_reg
*saved_regs
;
59 /* A structure describing a particular variant of the FRV.
60 We allocate and initialize one of these structures when we create
61 the gdbarch object for a variant.
63 At the moment, all the FR variants we support differ only in which
64 registers are present; the portable code of GDB knows that
65 registers whose names are the empty string don't exist, so the
66 `register_names' array captures all the per-variant information we
69 in the future, if we need to have per-variant maps for raw size,
70 virtual type, etc., we should replace register_names with an array
71 of structures, each of which gives all the necessary info for one
72 register. Don't stick parallel arrays in here --- that's so
76 /* Which ABI is in use? */
79 /* How many general-purpose registers does this variant have? */
82 /* How many floating-point registers does this variant have? */
85 /* How many hardware watchpoints can it support? */
86 int num_hw_watchpoints
;
88 /* How many hardware breakpoints can it support? */
89 int num_hw_breakpoints
;
92 char **register_names
;
95 /* Return the FR-V ABI associated with GDBARCH. */
97 frv_abi (struct gdbarch
*gdbarch
)
99 return gdbarch_tdep (gdbarch
)->frv_abi
;
102 /* Fetch the interpreter and executable loadmap addresses (for shared
103 library support) for the FDPIC ABI. Return 0 if successful, -1 if
104 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
106 frv_fdpic_loadmap_addresses (struct gdbarch
*gdbarch
, CORE_ADDR
*interp_addr
,
107 CORE_ADDR
*exec_addr
)
109 if (frv_abi (gdbarch
) != FRV_ABI_FDPIC
)
113 struct regcache
*regcache
= get_current_regcache ();
115 if (interp_addr
!= NULL
)
118 regcache_cooked_read_unsigned (regcache
,
119 fdpic_loadmap_interp_regnum
, &val
);
122 if (exec_addr
!= NULL
)
125 regcache_cooked_read_unsigned (regcache
,
126 fdpic_loadmap_exec_regnum
, &val
);
133 /* Allocate a new variant structure, and set up default values for all
135 static struct gdbarch_tdep
*
138 struct gdbarch_tdep
*var
;
142 var
= xmalloc (sizeof (*var
));
143 memset (var
, 0, sizeof (*var
));
145 var
->frv_abi
= FRV_ABI_EABI
;
148 var
->num_hw_watchpoints
= 0;
149 var
->num_hw_breakpoints
= 0;
151 /* By default, don't supply any general-purpose or floating-point
154 = (char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
156 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
157 var
->register_names
[r
] = "";
159 /* Do, however, supply default names for the known special-purpose
162 var
->register_names
[pc_regnum
] = "pc";
163 var
->register_names
[lr_regnum
] = "lr";
164 var
->register_names
[lcr_regnum
] = "lcr";
166 var
->register_names
[psr_regnum
] = "psr";
167 var
->register_names
[ccr_regnum
] = "ccr";
168 var
->register_names
[cccr_regnum
] = "cccr";
169 var
->register_names
[tbr_regnum
] = "tbr";
171 /* Debug registers. */
172 var
->register_names
[brr_regnum
] = "brr";
173 var
->register_names
[dbar0_regnum
] = "dbar0";
174 var
->register_names
[dbar1_regnum
] = "dbar1";
175 var
->register_names
[dbar2_regnum
] = "dbar2";
176 var
->register_names
[dbar3_regnum
] = "dbar3";
178 /* iacc0 (Only found on MB93405.) */
179 var
->register_names
[iacc0h_regnum
] = "iacc0h";
180 var
->register_names
[iacc0l_regnum
] = "iacc0l";
181 var
->register_names
[iacc0_regnum
] = "iacc0";
183 /* fsr0 (Found on FR555 and FR501.) */
184 var
->register_names
[fsr0_regnum
] = "fsr0";
186 /* acc0 - acc7. The architecture provides for the possibility of many
187 more (up to 64 total), but we don't want to make that big of a hole
188 in the G packet. If we need more in the future, we'll add them
190 for (r
= acc0_regnum
; r
<= acc7_regnum
; r
++)
193 buf
= xstrprintf ("acc%d", r
- acc0_regnum
);
194 var
->register_names
[r
] = buf
;
197 /* accg0 - accg7: These are one byte registers. The remote protocol
198 provides the raw values packed four into a slot. accg0123 and
199 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
200 We don't provide names for accg0123 and accg4567 since the user will
201 likely not want to see these raw values. */
203 for (r
= accg0_regnum
; r
<= accg7_regnum
; r
++)
206 buf
= xstrprintf ("accg%d", r
- accg0_regnum
);
207 var
->register_names
[r
] = buf
;
212 var
->register_names
[msr0_regnum
] = "msr0";
213 var
->register_names
[msr1_regnum
] = "msr1";
215 /* gner and fner registers. */
216 var
->register_names
[gner0_regnum
] = "gner0";
217 var
->register_names
[gner1_regnum
] = "gner1";
218 var
->register_names
[fner0_regnum
] = "fner0";
219 var
->register_names
[fner1_regnum
] = "fner1";
225 /* Indicate that the variant VAR has NUM_GPRS general-purpose
226 registers, and fill in the names array appropriately. */
228 set_variant_num_gprs (struct gdbarch_tdep
*var
, int num_gprs
)
232 var
->num_gprs
= num_gprs
;
234 for (r
= 0; r
< num_gprs
; ++r
)
238 sprintf (buf
, "gr%d", r
);
239 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
244 /* Indicate that the variant VAR has NUM_FPRS floating-point
245 registers, and fill in the names array appropriately. */
247 set_variant_num_fprs (struct gdbarch_tdep
*var
, int num_fprs
)
251 var
->num_fprs
= num_fprs
;
253 for (r
= 0; r
< num_fprs
; ++r
)
257 sprintf (buf
, "fr%d", r
);
258 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
263 set_variant_abi_fdpic (struct gdbarch_tdep
*var
)
265 var
->frv_abi
= FRV_ABI_FDPIC
;
266 var
->register_names
[fdpic_loadmap_exec_regnum
] = xstrdup ("loadmap_exec");
267 var
->register_names
[fdpic_loadmap_interp_regnum
]
268 = xstrdup ("loadmap_interp");
272 set_variant_scratch_registers (struct gdbarch_tdep
*var
)
274 var
->register_names
[scr0_regnum
] = xstrdup ("scr0");
275 var
->register_names
[scr1_regnum
] = xstrdup ("scr1");
276 var
->register_names
[scr2_regnum
] = xstrdup ("scr2");
277 var
->register_names
[scr3_regnum
] = xstrdup ("scr3");
281 frv_register_name (struct gdbarch
*gdbarch
, int reg
)
285 if (reg
>= frv_num_regs
+ frv_num_pseudo_regs
)
288 return gdbarch_tdep (gdbarch
)->register_names
[reg
];
293 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
295 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
296 return builtin_type (gdbarch
)->builtin_float
;
297 else if (reg
== iacc0_regnum
)
298 return builtin_type (gdbarch
)->builtin_int64
;
300 return builtin_type (gdbarch
)->builtin_int32
;
303 static enum register_status
304 frv_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
305 int reg
, gdb_byte
*buffer
)
307 enum register_status status
;
309 if (reg
== iacc0_regnum
)
311 status
= regcache_raw_read (regcache
, iacc0h_regnum
, buffer
);
312 if (status
== REG_VALID
)
313 status
= regcache_raw_read (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
315 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
317 /* The accg raw registers have four values in each slot with the
318 lowest register number occupying the first byte. */
320 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
321 int byte_num
= (reg
- accg0_regnum
) % 4;
324 status
= regcache_raw_read (regcache
, raw_regnum
, buf
);
325 if (status
== REG_VALID
)
327 memset (buffer
, 0, 4);
328 /* FR-V is big endian, so put the requested byte in the
329 first byte of the buffer allocated to hold the
331 buffer
[0] = buf
[byte_num
];
335 gdb_assert_not_reached ("invalid pseudo register number");
341 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
342 int reg
, const gdb_byte
*buffer
)
344 if (reg
== iacc0_regnum
)
346 regcache_raw_write (regcache
, iacc0h_regnum
, buffer
);
347 regcache_raw_write (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
349 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
351 /* The accg raw registers have four values in each slot with the
352 lowest register number occupying the first byte. */
354 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
355 int byte_num
= (reg
- accg0_regnum
) % 4;
358 regcache_raw_read (regcache
, raw_regnum
, buf
);
359 buf
[byte_num
] = ((bfd_byte
*) buffer
)[0];
360 regcache_raw_write (regcache
, raw_regnum
, buf
);
365 frv_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
367 static const int spr_map
[] =
369 H_SPR_PSR
, /* psr_regnum */
370 H_SPR_CCR
, /* ccr_regnum */
371 H_SPR_CCCR
, /* cccr_regnum */
372 -1, /* fdpic_loadmap_exec_regnum */
373 -1, /* fdpic_loadmap_interp_regnum */
375 H_SPR_TBR
, /* tbr_regnum */
376 H_SPR_BRR
, /* brr_regnum */
377 H_SPR_DBAR0
, /* dbar0_regnum */
378 H_SPR_DBAR1
, /* dbar1_regnum */
379 H_SPR_DBAR2
, /* dbar2_regnum */
380 H_SPR_DBAR3
, /* dbar3_regnum */
381 H_SPR_SCR0
, /* scr0_regnum */
382 H_SPR_SCR1
, /* scr1_regnum */
383 H_SPR_SCR2
, /* scr2_regnum */
384 H_SPR_SCR3
, /* scr3_regnum */
385 H_SPR_LR
, /* lr_regnum */
386 H_SPR_LCR
, /* lcr_regnum */
387 H_SPR_IACC0H
, /* iacc0h_regnum */
388 H_SPR_IACC0L
, /* iacc0l_regnum */
389 H_SPR_FSR0
, /* fsr0_regnum */
390 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
391 -1, /* acc0_regnum */
392 -1, /* acc1_regnum */
393 -1, /* acc2_regnum */
394 -1, /* acc3_regnum */
395 -1, /* acc4_regnum */
396 -1, /* acc5_regnum */
397 -1, /* acc6_regnum */
398 -1, /* acc7_regnum */
399 -1, /* acc0123_regnum */
400 -1, /* acc4567_regnum */
401 H_SPR_MSR0
, /* msr0_regnum */
402 H_SPR_MSR1
, /* msr1_regnum */
403 H_SPR_GNER0
, /* gner0_regnum */
404 H_SPR_GNER1
, /* gner1_regnum */
405 H_SPR_FNER0
, /* fner0_regnum */
406 H_SPR_FNER1
, /* fner1_regnum */
409 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
411 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
412 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
413 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
414 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
415 else if (pc_regnum
== reg
)
416 return SIM_FRV_PC_REGNUM
;
417 else if (reg
>= first_spr_regnum
418 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
420 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
422 if (spr_reg_offset
< 0)
423 return SIM_REGNO_DOES_NOT_EXIST
;
425 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
428 internal_error (__FILE__
, __LINE__
, _("Bad register number %d"), reg
);
431 static const unsigned char *
432 frv_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenp
)
434 static unsigned char breakpoint
[] = {0xc0, 0x70, 0x00, 0x01};
435 *lenp
= sizeof (breakpoint
);
439 /* Define the maximum number of instructions which may be packed into a
440 bundle (VLIW instruction). */
441 static const int max_instrs_per_bundle
= 8;
443 /* Define the size (in bytes) of an FR-V instruction. */
444 static const int frv_instr_size
= 4;
446 /* Adjust a breakpoint's address to account for the FR-V architecture's
447 constraint that a break instruction must not appear as any but the
448 first instruction in the bundle. */
450 frv_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
452 int count
= max_instrs_per_bundle
;
453 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
454 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
456 /* Find the end of the previous packing sequence. This will be indicated
457 by either attempting to access some inaccessible memory or by finding
458 an instruction word whose packing bit is set to one. */
459 while (count
-- > 0 && addr
>= func_start
)
461 char instr
[frv_instr_size
];
464 status
= target_read_memory (addr
, instr
, sizeof instr
);
469 /* This is a big endian architecture, so byte zero will have most
470 significant byte. The most significant bit of this byte is the
475 addr
-= frv_instr_size
;
479 bpaddr
= addr
+ frv_instr_size
;
485 /* Return true if REG is a caller-saves ("scratch") register,
488 is_caller_saves_reg (int reg
)
490 return ((4 <= reg
&& reg
<= 7)
491 || (14 <= reg
&& reg
<= 15)
492 || (32 <= reg
&& reg
<= 47));
496 /* Return true if REG is a callee-saves register, false otherwise. */
498 is_callee_saves_reg (int reg
)
500 return ((16 <= reg
&& reg
<= 31)
501 || (48 <= reg
&& reg
<= 63));
505 /* Return true if REG is an argument register, false otherwise. */
507 is_argument_reg (int reg
)
509 return (8 <= reg
&& reg
<= 13);
512 /* Scan an FR-V prologue, starting at PC, until frame->PC.
513 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
514 We assume FRAME's saved_regs array has already been allocated and cleared.
515 Return the first PC value after the prologue.
517 Note that, for unoptimized code, we almost don't need this function
518 at all; all arguments and locals live on the stack, so we just need
519 the FP to find everything. The catch: structures passed by value
520 have their addresses living in registers; they're never spilled to
521 the stack. So if you ever want to be able to get to these
522 arguments in any frame but the top, you'll need to do this serious
523 prologue analysis. */
525 frv_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
526 struct frame_info
*this_frame
,
527 struct frv_unwind_cache
*info
)
529 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
531 /* When writing out instruction bitpatterns, we use the following
532 letters to label instruction fields:
533 P - The parallel bit. We don't use this.
534 J - The register number of GRj in the instruction description.
535 K - The register number of GRk in the instruction description.
536 I - The register number of GRi.
537 S - a signed imediate offset.
538 U - an unsigned immediate offset.
540 The dots below the numbers indicate where hex digit boundaries
541 fall, to make it easier to check the numbers. */
543 /* Non-zero iff we've seen the instruction that initializes the
544 frame pointer for this function's frame. */
547 /* If fp_set is non_zero, then this is the distance from
548 the stack pointer to frame pointer: fp = sp + fp_offset. */
551 /* Total size of frame prior to any alloca operations. */
554 /* Flag indicating if lr has been saved on the stack. */
555 int lr_saved_on_stack
= 0;
557 /* The number of the general-purpose register we saved the return
558 address ("link register") in, or -1 if we haven't moved it yet. */
559 int lr_save_reg
= -1;
561 /* Offset (from sp) at which lr has been saved on the stack. */
563 int lr_sp_offset
= 0;
565 /* If gr_saved[i] is non-zero, then we've noticed that general
566 register i has been saved at gr_sp_offset[i] from the stack
569 int gr_sp_offset
[64];
571 /* The address of the most recently scanned prologue instruction. */
572 CORE_ADDR last_prologue_pc
;
574 /* The address of the next instruction. */
577 /* The upper bound to of the pc values to scan. */
580 memset (gr_saved
, 0, sizeof (gr_saved
));
582 last_prologue_pc
= pc
;
584 /* Try to compute an upper limit (on how far to scan) based on the
586 lim_pc
= skip_prologue_using_sal (gdbarch
, pc
);
587 /* If there's no line number info, lim_pc will be 0. In that case,
588 set the limit to be 100 instructions away from pc. Hopefully, this
589 will be far enough away to account for the entire prologue. Don't
590 worry about overshooting the end of the function. The scan loop
591 below contains some checks to avoid scanning unreasonably far. */
595 /* If we have a frame, we don't want to scan past the frame's pc. This
596 will catch those cases where the pc is in the prologue. */
599 CORE_ADDR frame_pc
= get_frame_pc (this_frame
);
600 if (frame_pc
< lim_pc
)
604 /* Scan the prologue. */
607 char buf
[frv_instr_size
];
610 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
612 op
= extract_signed_integer (buf
, sizeof buf
, byte_order
);
616 /* The tests in this chain of ifs should be in order of
617 decreasing selectivity, so that more particular patterns get
618 to fire before less particular patterns. */
620 /* Some sort of control transfer instruction: stop scanning prologue.
621 Integer Conditional Branch:
622 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
623 Floating-point / media Conditional Branch:
624 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
625 LCR Conditional Branch to LR
626 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
627 Integer conditional Branches to LR
628 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
629 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
630 Floating-point/Media Branches to LR
631 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
632 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
634 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
635 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
637 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
639 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
640 Integer Conditional Trap
641 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
642 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
643 Floating-point /media Conditional Trap
644 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
645 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
647 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
649 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
650 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
651 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
652 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
653 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
655 /* Stop scanning; not in prologue any longer. */
659 /* Loading something from memory into fp probably means that
660 we're in the epilogue. Stop scanning the prologue.
662 X 000010 0000010 XXXXXX 000100 XXXXXX
664 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
665 else if ((op
& 0x7ffc0fc0) == 0x04080100
666 || (op
& 0x7ffc0000) == 0x04c80000)
671 /* Setting the FP from the SP:
673 P 000010 0100010 000001 000000000000 = 0x04881000
674 0 111111 1111111 111111 111111111111 = 0x7fffffff
676 We treat this as part of the prologue. */
677 else if ((op
& 0x7fffffff) == 0x04881000)
681 last_prologue_pc
= next_pc
;
684 /* Move the link register to the scratch register grJ, before saving:
686 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
687 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
689 We treat this as part of the prologue. */
690 else if ((op
& 0x7fffffc0) == 0x080d01c0)
692 int gr_j
= op
& 0x3f;
694 /* If we're moving it to a scratch register, that's fine. */
695 if (is_caller_saves_reg (gr_j
))
698 last_prologue_pc
= next_pc
;
702 /* To save multiple callee-saves registers on the stack, at
706 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
707 0 000000 1111111 111111 111111 111111 = 0x01ffffff
710 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
711 0 000000 1111111 111111 111111 111111 = 0x01ffffff
713 We treat this as part of the prologue, and record the register's
714 saved address in the frame structure. */
715 else if ((op
& 0x01ffffff) == 0x000c10c0
716 || (op
& 0x01ffffff) == 0x000c1100)
718 int gr_k
= ((op
>> 25) & 0x3f);
719 int ope
= ((op
>> 6) & 0x3f);
723 /* Is it an std or an stq? */
729 /* Is it really a callee-saves register? */
730 if (is_callee_saves_reg (gr_k
))
732 for (i
= 0; i
< count
; i
++)
734 gr_saved
[gr_k
+ i
] = 1;
735 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
737 last_prologue_pc
= next_pc
;
741 /* Adjusting the stack pointer. (The stack pointer is GR1.)
743 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
744 0 111111 1111111 111111 000000000000 = 0x7ffff000
746 We treat this as part of the prologue. */
747 else if ((op
& 0x7ffff000) == 0x02401000)
751 /* Sign-extend the twelve-bit field.
752 (Isn't there a better way to do this?) */
753 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
756 last_prologue_pc
= pc
;
760 /* If the prologue is being adjusted again, we've
761 likely gone too far; i.e. we're probably in the
767 /* Setting the FP to a constant distance from the SP:
769 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
770 0 111111 1111111 111111 000000000000 = 0x7ffff000
772 We treat this as part of the prologue. */
773 else if ((op
& 0x7ffff000) == 0x04401000)
775 /* Sign-extend the twelve-bit field.
776 (Isn't there a better way to do this?) */
777 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
780 last_prologue_pc
= pc
;
783 /* To spill an argument register to a scratch register:
785 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
786 0 000000 1111111 000000 111111111111 = 0x01fc0fff
788 For the time being, we treat this as a prologue instruction,
789 assuming that GRi is an argument register. This one's kind
790 of suspicious, because it seems like it could be part of a
791 legitimate body instruction. But we only come here when the
792 source info wasn't helpful, so we have to do the best we can.
793 Hopefully once GCC and GDB agree on how to emit line number
794 info for prologues, then this code will never come into play. */
795 else if ((op
& 0x01fc0fff) == 0x00880000)
797 int gr_i
= ((op
>> 12) & 0x3f);
799 /* Make sure that the source is an arg register; if it is, we'll
800 treat it as a prologue instruction. */
801 if (is_argument_reg (gr_i
))
802 last_prologue_pc
= next_pc
;
805 /* To spill 16-bit values to the stack:
807 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
808 0 000000 1111111 111111 000000000000 = 0x01fff000
810 And for 8-bit values, we use STB instructions.
812 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
813 0 000000 1111111 111111 000000000000 = 0x01fff000
815 We check that GRk is really an argument register, and treat
816 all such as part of the prologue. */
817 else if ( (op
& 0x01fff000) == 0x01442000
818 || (op
& 0x01fff000) == 0x01402000)
820 int gr_k
= ((op
>> 25) & 0x3f);
822 /* Make sure that GRk is really an argument register; treat
823 it as a prologue instruction if so. */
824 if (is_argument_reg (gr_k
))
825 last_prologue_pc
= next_pc
;
828 /* To save multiple callee-saves register on the stack, at a
832 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
833 0 000000 1111111 111111 000000000000 = 0x01fff000
836 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
837 0 000000 1111111 111111 000000000000 = 0x01fff000
839 We treat this as part of the prologue, and record the register's
840 saved address in the frame structure. */
841 else if ((op
& 0x01fff000) == 0x014c1000
842 || (op
& 0x01fff000) == 0x01501000)
844 int gr_k
= ((op
>> 25) & 0x3f);
848 /* Is it a stdi or a stqi? */
849 if ((op
& 0x01fff000) == 0x014c1000)
854 /* Is it really a callee-saves register? */
855 if (is_callee_saves_reg (gr_k
))
857 /* Sign-extend the twelve-bit field.
858 (Isn't there a better way to do this?) */
859 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
861 for (i
= 0; i
< count
; i
++)
863 gr_saved
[gr_k
+ i
] = 1;
864 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
866 last_prologue_pc
= next_pc
;
870 /* Storing any kind of integer register at any constant offset
871 from any other register.
874 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
875 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
878 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
879 0 000000 1111111 000000 000000000000 = 0x01fc0000
881 These could be almost anything, but a lot of prologue
882 instructions fall into this pattern, so let's decode the
883 instruction once, and then work at a higher level. */
884 else if (((op
& 0x01fc0fff) == 0x000c0080)
885 || ((op
& 0x01fc0000) == 0x01480000))
887 int gr_k
= ((op
>> 25) & 0x3f);
888 int gr_i
= ((op
>> 12) & 0x3f);
891 /* Are we storing with gr0 as an offset, or using an
893 if ((op
& 0x01fc0fff) == 0x000c0080)
896 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
898 /* If the address isn't relative to the SP or FP, it's not a
899 prologue instruction. */
900 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
902 /* Do nothing; not a prologue instruction. */
905 /* Saving the old FP in the new frame (relative to the SP). */
906 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
908 gr_saved
[fp_regnum
] = 1;
909 gr_sp_offset
[fp_regnum
] = offset
;
910 last_prologue_pc
= next_pc
;
913 /* Saving callee-saves register(s) on the stack, relative to
915 else if (gr_i
== sp_regnum
916 && is_callee_saves_reg (gr_k
))
919 if (gr_i
== sp_regnum
)
920 gr_sp_offset
[gr_k
] = offset
;
922 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
923 last_prologue_pc
= next_pc
;
926 /* Saving the scratch register holding the return address. */
927 else if (lr_save_reg
!= -1
928 && gr_k
== lr_save_reg
)
930 lr_saved_on_stack
= 1;
931 if (gr_i
== sp_regnum
)
932 lr_sp_offset
= offset
;
934 lr_sp_offset
= offset
+ fp_offset
;
935 last_prologue_pc
= next_pc
;
938 /* Spilling int-sized arguments to the stack. */
939 else if (is_argument_reg (gr_k
))
940 last_prologue_pc
= next_pc
;
945 if (this_frame
&& info
)
950 /* If we know the relationship between the stack and frame
951 pointers, record the addresses of the registers we noticed.
952 Note that we have to do this as a separate step at the end,
953 because instructions may save relative to the SP, but we need
954 their addresses relative to the FP. */
956 this_base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
958 this_base
= get_frame_register_unsigned (this_frame
, sp_regnum
);
960 for (i
= 0; i
< 64; i
++)
962 info
->saved_regs
[i
].addr
= this_base
- fp_offset
+ gr_sp_offset
[i
];
964 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
965 info
->base
= this_base
;
967 /* If LR was saved on the stack, record its location. */
968 if (lr_saved_on_stack
)
969 info
->saved_regs
[lr_regnum
].addr
970 = this_base
- fp_offset
+ lr_sp_offset
;
972 /* The call instruction moves the caller's PC in the callee's LR.
973 Since this is an unwind, do the reverse. Copy the location of LR
974 into PC (the address / regnum) so that a request for PC will be
975 converted into a request for the LR. */
976 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
978 /* Save the previous frame's computed SP value. */
979 trad_frame_set_value (info
->saved_regs
, sp_regnum
, info
->prev_sp
);
982 return last_prologue_pc
;
987 frv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
989 CORE_ADDR func_addr
, func_end
, new_pc
;
993 /* If the line table has entry for a line *within* the function
994 (i.e., not in the prologue, and not past the end), then that's
996 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
998 struct symtab_and_line sal
;
1000 sal
= find_pc_line (func_addr
, 0);
1002 if (sal
.line
!= 0 && sal
.end
< func_end
)
1008 /* The FR-V prologue is at least five instructions long (twenty bytes).
1009 If we didn't find a real source location past that, then
1010 do a full analysis of the prologue. */
1011 if (new_pc
< pc
+ 20)
1012 new_pc
= frv_analyze_prologue (gdbarch
, pc
, 0, 0);
1018 /* Examine the instruction pointed to by PC. If it corresponds to
1019 a call to __main, return the address of the next instruction.
1020 Otherwise, return PC. */
1023 frv_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1025 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1028 CORE_ADDR orig_pc
= pc
;
1030 if (target_read_memory (pc
, buf
, 4))
1032 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1034 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1035 to the call instruction.
1037 Skip over this instruction if present. It won't be present in
1038 non-PIC code, and even in PIC code, it might not be present.
1039 (This is due to the fact that GR15, the FDPIC register, already
1040 contains the correct value.)
1042 The general form of the LDI is given first, followed by the
1043 specific instruction with the GRi and GRk filled in as FP and
1046 ldi @(GRi, d12), GRk
1047 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1048 0 000000 1111111 000000 000000000000 = 0x01fc0000
1050 ldi @(FP, d12), GR15
1051 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1052 0 001111 1111111 000010 000000000000 = 0x7ffff000
1055 if ((op
& 0x7ffff000) == 0x1ec82000)
1058 if (target_read_memory (pc
, buf
, 4))
1060 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1063 /* The format of an FRV CALL instruction is as follows:
1066 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1067 0 000000 1111111 000000000000000000 = 0x01fc0000
1070 where label24 is constructed by concatenating the H bits with the
1071 L bits. The call target is PC + (4 * sign_ext(label24)). */
1073 if ((op
& 0x01fc0000) == 0x003c0000)
1076 CORE_ADDR call_dest
;
1077 struct minimal_symbol
*s
;
1079 displ
= ((op
& 0xfe000000) >> 7) | (op
& 0x0003ffff);
1080 if ((displ
& 0x00800000) != 0)
1081 displ
|= ~((LONGEST
) 0x00ffffff);
1083 call_dest
= pc
+ 4 * displ
;
1084 s
= lookup_minimal_symbol_by_pc (call_dest
);
1087 && SYMBOL_LINKAGE_NAME (s
) != NULL
1088 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1098 static struct frv_unwind_cache
*
1099 frv_frame_unwind_cache (struct frame_info
*this_frame
,
1100 void **this_prologue_cache
)
1102 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1105 struct frv_unwind_cache
*info
;
1107 if ((*this_prologue_cache
))
1108 return (*this_prologue_cache
);
1110 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
1111 (*this_prologue_cache
) = info
;
1112 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1114 /* Prologue analysis does the rest... */
1115 frv_analyze_prologue (gdbarch
,
1116 get_frame_func (this_frame
), this_frame
, info
);
1122 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1125 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1126 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1127 int len
= TYPE_LENGTH (type
);
1132 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1133 store_unsigned_integer (valbuf
, len
, byte_order
, gpr8_val
);
1139 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1140 store_unsigned_integer (valbuf
, 4, byte_order
, regval
);
1141 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1142 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, byte_order
, regval
);
1145 internal_error (__FILE__
, __LINE__
,
1146 _("Illegal return value length: %d"), len
);
1150 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1152 /* Require dword alignment. */
1153 return align_down (sp
, 8);
1157 find_func_descr (struct gdbarch
*gdbarch
, CORE_ADDR entry_point
)
1159 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1162 CORE_ADDR start_addr
;
1164 /* If we can't find the function in the symbol table, then we assume
1165 that the function address is already in descriptor form. */
1166 if (!find_pc_partial_function (entry_point
, NULL
, &start_addr
, NULL
)
1167 || entry_point
!= start_addr
)
1170 descr
= frv_fdpic_find_canonical_descriptor (entry_point
);
1175 /* Construct a non-canonical descriptor from space allocated on
1178 descr
= value_as_long (value_allocate_space_in_inferior (8));
1179 store_unsigned_integer (valbuf
, 4, byte_order
, entry_point
);
1180 write_memory (descr
, valbuf
, 4);
1181 store_unsigned_integer (valbuf
, 4, byte_order
,
1182 frv_fdpic_find_global_pointer (entry_point
));
1183 write_memory (descr
+ 4, valbuf
, 4);
1188 frv_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1189 struct target_ops
*targ
)
1191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1192 CORE_ADDR entry_point
;
1193 CORE_ADDR got_address
;
1195 entry_point
= get_target_memory_unsigned (targ
, addr
, 4, byte_order
);
1196 got_address
= get_target_memory_unsigned (targ
, addr
+ 4, 4, byte_order
);
1198 if (got_address
== frv_fdpic_find_global_pointer (entry_point
))
1205 frv_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1206 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1207 int nargs
, struct value
**args
, CORE_ADDR sp
,
1208 int struct_return
, CORE_ADDR struct_addr
)
1210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1216 struct type
*arg_type
;
1218 enum type_code typecode
;
1222 enum frv_abi abi
= frv_abi (gdbarch
);
1223 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1226 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1227 nargs
, (int) sp
, struct_return
, struct_addr
);
1231 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1232 stack_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
1234 stack_space
-= (6 * 4);
1235 if (stack_space
> 0)
1238 /* Make sure stack is dword aligned. */
1239 sp
= align_down (sp
, 8);
1246 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1249 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1252 arg_type
= check_typedef (value_type (arg
));
1253 len
= TYPE_LENGTH (arg_type
);
1254 typecode
= TYPE_CODE (arg_type
);
1256 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1258 store_unsigned_integer (valbuf
, 4, byte_order
,
1259 value_address (arg
));
1260 typecode
= TYPE_CODE_PTR
;
1264 else if (abi
== FRV_ABI_FDPIC
1266 && typecode
== TYPE_CODE_PTR
1267 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
1269 /* The FDPIC ABI requires function descriptors to be passed instead
1271 CORE_ADDR addr
= extract_unsigned_integer
1272 (value_contents (arg
), 4, byte_order
);
1273 addr
= find_func_descr (gdbarch
, addr
);
1274 store_unsigned_integer (valbuf
, 4, byte_order
, addr
);
1275 typecode
= TYPE_CODE_PTR
;
1281 val
= (char *) value_contents (arg
);
1286 int partial_len
= (len
< 4 ? len
: 4);
1290 regval
= extract_unsigned_integer (val
, partial_len
, byte_order
);
1292 printf(" Argnum %d data %x -> reg %d\n",
1293 argnum
, (int) regval
, argreg
);
1295 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1301 printf(" Argnum %d data %x -> offset %d (%x)\n",
1302 argnum
, *((int *)val
), stack_offset
,
1303 (int) (sp
+ stack_offset
));
1305 write_memory (sp
+ stack_offset
, val
, partial_len
);
1306 stack_offset
+= align_up (partial_len
, 4);
1313 /* Set the return address. For the frv, the return breakpoint is
1314 always at BP_ADDR. */
1315 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1317 if (abi
== FRV_ABI_FDPIC
)
1319 /* Set the GOT register for the FDPIC ABI. */
1320 regcache_cooked_write_unsigned
1321 (regcache
, first_gpr_regnum
+ 15,
1322 frv_fdpic_find_global_pointer (func_addr
));
1325 /* Finally, update the SP register. */
1326 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1332 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1333 const gdb_byte
*valbuf
)
1335 int len
= TYPE_LENGTH (type
);
1340 memset (val
, 0, sizeof (val
));
1341 memcpy (val
+ (4 - len
), valbuf
, len
);
1342 regcache_cooked_write (regcache
, 8, val
);
1346 regcache_cooked_write (regcache
, 8, valbuf
);
1347 regcache_cooked_write (regcache
, 9, (bfd_byte
*) valbuf
+ 4);
1350 internal_error (__FILE__
, __LINE__
,
1351 _("Don't know how to return a %d-byte value."), len
);
1354 static enum return_value_convention
1355 frv_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1356 struct type
*valtype
, struct regcache
*regcache
,
1357 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1359 int struct_return
= TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1360 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1361 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
;
1363 if (writebuf
!= NULL
)
1365 gdb_assert (!struct_return
);
1366 frv_store_return_value (valtype
, regcache
, writebuf
);
1369 if (readbuf
!= NULL
)
1371 gdb_assert (!struct_return
);
1372 frv_extract_return_value (valtype
, regcache
, readbuf
);
1376 return RETURN_VALUE_STRUCT_CONVENTION
;
1378 return RETURN_VALUE_REGISTER_CONVENTION
;
1382 /* Hardware watchpoint / breakpoint support for the FR500
1386 frv_check_watch_resources (struct gdbarch
*gdbarch
, int type
, int cnt
, int ot
)
1388 struct gdbarch_tdep
*var
= gdbarch_tdep (gdbarch
);
1390 /* Watchpoints not supported on simulator. */
1391 if (strcmp (target_shortname
, "sim") == 0)
1394 if (type
== bp_hardware_breakpoint
)
1396 if (var
->num_hw_breakpoints
== 0)
1398 else if (cnt
<= var
->num_hw_breakpoints
)
1403 if (var
->num_hw_watchpoints
== 0)
1407 else if (cnt
<= var
->num_hw_watchpoints
)
1415 frv_stopped_data_address (CORE_ADDR
*addr_p
)
1417 struct frame_info
*frame
= get_current_frame ();
1418 CORE_ADDR brr
, dbar0
, dbar1
, dbar2
, dbar3
;
1420 brr
= get_frame_register_unsigned (frame
, brr_regnum
);
1421 dbar0
= get_frame_register_unsigned (frame
, dbar0_regnum
);
1422 dbar1
= get_frame_register_unsigned (frame
, dbar1_regnum
);
1423 dbar2
= get_frame_register_unsigned (frame
, dbar2_regnum
);
1424 dbar3
= get_frame_register_unsigned (frame
, dbar3_regnum
);
1428 else if (brr
& (1<<10))
1430 else if (brr
& (1<<9))
1432 else if (brr
& (1<<8))
1441 frv_have_stopped_data_address (void)
1444 return frv_stopped_data_address (&addr
);
1448 frv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1450 return frame_unwind_register_unsigned (next_frame
, pc_regnum
);
1453 /* Given a GDB frame, determine the address of the calling function's
1454 frame. This will be used to create a new GDB frame struct. */
1457 frv_frame_this_id (struct frame_info
*this_frame
,
1458 void **this_prologue_cache
, struct frame_id
*this_id
)
1460 struct frv_unwind_cache
*info
1461 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1464 struct minimal_symbol
*msym_stack
;
1467 /* The FUNC is easy. */
1468 func
= get_frame_func (this_frame
);
1470 /* Check if the stack is empty. */
1471 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1472 if (msym_stack
&& info
->base
== SYMBOL_VALUE_ADDRESS (msym_stack
))
1475 /* Hopefully the prologue analysis either correctly determined the
1476 frame's base (which is the SP from the previous frame), or set
1477 that base to "NULL". */
1478 base
= info
->prev_sp
;
1482 id
= frame_id_build (base
, func
);
1486 static struct value
*
1487 frv_frame_prev_register (struct frame_info
*this_frame
,
1488 void **this_prologue_cache
, int regnum
)
1490 struct frv_unwind_cache
*info
1491 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1492 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1495 static const struct frame_unwind frv_frame_unwind
= {
1497 default_frame_unwind_stop_reason
,
1499 frv_frame_prev_register
,
1501 default_frame_sniffer
1505 frv_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1507 struct frv_unwind_cache
*info
1508 = frv_frame_unwind_cache (this_frame
, this_cache
);
1512 static const struct frame_base frv_frame_base
= {
1514 frv_frame_base_address
,
1515 frv_frame_base_address
,
1516 frv_frame_base_address
1520 frv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1522 return frame_unwind_register_unsigned (next_frame
, sp_regnum
);
1526 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
1527 frame. The frame ID's base needs to match the TOS value saved by
1528 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
1530 static struct frame_id
1531 frv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1533 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
, sp_regnum
);
1534 return frame_id_build (sp
, get_frame_pc (this_frame
));
1537 static struct gdbarch
*
1538 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1540 struct gdbarch
*gdbarch
;
1541 struct gdbarch_tdep
*var
;
1544 /* Check to see if we've already built an appropriate architecture
1545 object for this executable. */
1546 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1548 return arches
->gdbarch
;
1550 /* Select the right tdep structure for this variant. */
1551 var
= new_variant ();
1552 switch (info
.bfd_arch_info
->mach
)
1555 case bfd_mach_frvsimple
:
1556 case bfd_mach_fr500
:
1557 case bfd_mach_frvtomcat
:
1558 case bfd_mach_fr550
:
1559 set_variant_num_gprs (var
, 64);
1560 set_variant_num_fprs (var
, 64);
1563 case bfd_mach_fr400
:
1564 case bfd_mach_fr450
:
1565 set_variant_num_gprs (var
, 32);
1566 set_variant_num_fprs (var
, 32);
1570 /* Never heard of this variant. */
1574 /* Extract the ELF flags, if available. */
1575 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1576 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1578 if (elf_flags
& EF_FRV_FDPIC
)
1579 set_variant_abi_fdpic (var
);
1581 if (elf_flags
& EF_FRV_CPU_FR450
)
1582 set_variant_scratch_registers (var
);
1584 gdbarch
= gdbarch_alloc (&info
, var
);
1586 set_gdbarch_short_bit (gdbarch
, 16);
1587 set_gdbarch_int_bit (gdbarch
, 32);
1588 set_gdbarch_long_bit (gdbarch
, 32);
1589 set_gdbarch_long_long_bit (gdbarch
, 64);
1590 set_gdbarch_float_bit (gdbarch
, 32);
1591 set_gdbarch_double_bit (gdbarch
, 64);
1592 set_gdbarch_long_double_bit (gdbarch
, 64);
1593 set_gdbarch_ptr_bit (gdbarch
, 32);
1595 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1596 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1598 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1599 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1600 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1602 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1603 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1604 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1606 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1607 set_gdbarch_pseudo_register_write (gdbarch
, frv_pseudo_register_write
);
1609 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1610 set_gdbarch_skip_main_prologue (gdbarch
, frv_skip_main_prologue
);
1611 set_gdbarch_breakpoint_from_pc (gdbarch
, frv_breakpoint_from_pc
);
1612 set_gdbarch_adjust_breakpoint_address
1613 (gdbarch
, frv_adjust_breakpoint_address
);
1615 set_gdbarch_return_value (gdbarch
, frv_return_value
);
1618 set_gdbarch_unwind_pc (gdbarch
, frv_unwind_pc
);
1619 set_gdbarch_unwind_sp (gdbarch
, frv_unwind_sp
);
1620 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1621 frame_base_set_default (gdbarch
, &frv_frame_base
);
1622 /* We set the sniffer lower down after the OSABI hooks have been
1625 /* Settings for calling functions in the inferior. */
1626 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1627 set_gdbarch_dummy_id (gdbarch
, frv_dummy_id
);
1629 /* Settings that should be unnecessary. */
1630 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1632 /* Hardware watchpoint / breakpoint support. */
1633 switch (info
.bfd_arch_info
->mach
)
1636 case bfd_mach_frvsimple
:
1637 case bfd_mach_fr500
:
1638 case bfd_mach_frvtomcat
:
1639 /* fr500-style hardware debugging support. */
1640 var
->num_hw_watchpoints
= 4;
1641 var
->num_hw_breakpoints
= 4;
1644 case bfd_mach_fr400
:
1645 case bfd_mach_fr450
:
1646 /* fr400-style hardware debugging support. */
1647 var
->num_hw_watchpoints
= 2;
1648 var
->num_hw_breakpoints
= 4;
1652 /* Otherwise, assume we don't have hardware debugging support. */
1653 var
->num_hw_watchpoints
= 0;
1654 var
->num_hw_breakpoints
= 0;
1658 set_gdbarch_print_insn (gdbarch
, print_insn_frv
);
1659 if (frv_abi (gdbarch
) == FRV_ABI_FDPIC
)
1660 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
1661 frv_convert_from_func_ptr_addr
);
1663 set_solib_ops (gdbarch
, &frv_so_ops
);
1665 /* Hook in ABI-specific overrides, if they have been registered. */
1666 gdbarch_init_osabi (info
, gdbarch
);
1668 /* Set the fallback (prologue based) frame sniffer. */
1669 frame_unwind_append_unwinder (gdbarch
, &frv_frame_unwind
);
1671 /* Enable TLS support. */
1672 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1673 frv_fetch_objfile_link_map
);
1679 _initialize_frv_tdep (void)
1681 register_gdbarch_init (bfd_arch_frv
, frv_gdbarch_init
);