1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2 Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 #include "gdb_string.h"
25 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
32 #include "gdb_assert.h"
33 #include "sim-regno.h"
34 #include "gdb/sim-frv.h"
35 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
38 extern void _initialize_frv_tdep (void);
40 static gdbarch_init_ftype frv_gdbarch_init
;
42 static gdbarch_register_name_ftype frv_register_name
;
43 static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc
;
44 static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address
;
45 static gdbarch_skip_prologue_ftype frv_skip_prologue
;
47 /* Register numbers. The order in which these appear define the
48 remote protocol, so take care in changing them. */
50 /* Register numbers 0 -- 63 are always reserved for general-purpose
51 registers. The chip at hand may have less. */
55 struct_return_regnum
= 3,
58 /* Register numbers 64 -- 127 are always reserved for floating-point
59 registers. The chip at hand may have less. */
60 first_fpr_regnum
= 64,
61 last_fpr_regnum
= 127,
63 /* The PC register. */
66 /* Register numbers 129 on up are always reserved for special-purpose
68 first_spr_regnum
= 129,
82 last_spr_regnum
= 148,
84 /* The total number of registers we know exist. */
85 frv_num_regs
= last_spr_regnum
+ 1,
87 /* Pseudo registers */
88 first_pseudo_regnum
= frv_num_regs
,
90 /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
91 iacc0_regnum
= first_pseudo_regnum
+ 0,
93 last_pseudo_regnum
= iacc0_regnum
,
94 frv_num_pseudo_regs
= last_pseudo_regnum
- first_pseudo_regnum
+ 1,
97 static LONGEST frv_call_dummy_words
[] =
101 struct frv_unwind_cache
/* was struct frame_extra_info */
103 /* The previous frame's inner-most stack address. Used as this
104 frame ID's stack_addr. */
107 /* The frame's base, optionally used by the high-level debug info. */
110 /* Table indicating the location of each and every register. */
111 struct trad_frame_saved_reg
*saved_regs
;
115 /* A structure describing a particular variant of the FRV.
116 We allocate and initialize one of these structures when we create
117 the gdbarch object for a variant.
119 At the moment, all the FR variants we support differ only in which
120 registers are present; the portable code of GDB knows that
121 registers whose names are the empty string don't exist, so the
122 `register_names' array captures all the per-variant information we
125 in the future, if we need to have per-variant maps for raw size,
126 virtual type, etc., we should replace register_names with an array
127 of structures, each of which gives all the necessary info for one
128 register. Don't stick parallel arrays in here --- that's so
132 /* How many general-purpose registers does this variant have? */
135 /* How many floating-point registers does this variant have? */
138 /* How many hardware watchpoints can it support? */
139 int num_hw_watchpoints
;
141 /* How many hardware breakpoints can it support? */
142 int num_hw_breakpoints
;
144 /* Register names. */
145 char **register_names
;
148 #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
151 /* Allocate a new variant structure, and set up default values for all
153 static struct gdbarch_tdep
*
156 struct gdbarch_tdep
*var
;
160 var
= xmalloc (sizeof (*var
));
161 memset (var
, 0, sizeof (*var
));
165 var
->num_hw_watchpoints
= 0;
166 var
->num_hw_breakpoints
= 0;
168 /* By default, don't supply any general-purpose or floating-point
171 = (char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
173 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
174 var
->register_names
[r
] = "";
176 /* Do, however, supply default names for the known special-purpose
179 var
->register_names
[pc_regnum
] = "pc";
180 var
->register_names
[lr_regnum
] = "lr";
181 var
->register_names
[lcr_regnum
] = "lcr";
183 var
->register_names
[psr_regnum
] = "psr";
184 var
->register_names
[ccr_regnum
] = "ccr";
185 var
->register_names
[cccr_regnum
] = "cccr";
186 var
->register_names
[tbr_regnum
] = "tbr";
188 /* Debug registers. */
189 var
->register_names
[brr_regnum
] = "brr";
190 var
->register_names
[dbar0_regnum
] = "dbar0";
191 var
->register_names
[dbar1_regnum
] = "dbar1";
192 var
->register_names
[dbar2_regnum
] = "dbar2";
193 var
->register_names
[dbar3_regnum
] = "dbar3";
195 /* iacc0 (Only found on MB93405.) */
196 var
->register_names
[iacc0h_regnum
] = "iacc0h";
197 var
->register_names
[iacc0l_regnum
] = "iacc0l";
198 var
->register_names
[iacc0_regnum
] = "iacc0";
204 /* Indicate that the variant VAR has NUM_GPRS general-purpose
205 registers, and fill in the names array appropriately. */
207 set_variant_num_gprs (struct gdbarch_tdep
*var
, int num_gprs
)
211 var
->num_gprs
= num_gprs
;
213 for (r
= 0; r
< num_gprs
; ++r
)
217 sprintf (buf
, "gr%d", r
);
218 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
223 /* Indicate that the variant VAR has NUM_FPRS floating-point
224 registers, and fill in the names array appropriately. */
226 set_variant_num_fprs (struct gdbarch_tdep
*var
, int num_fprs
)
230 var
->num_fprs
= num_fprs
;
232 for (r
= 0; r
< num_fprs
; ++r
)
236 sprintf (buf
, "fr%d", r
);
237 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
243 frv_register_name (int reg
)
247 if (reg
>= frv_num_regs
+ frv_num_pseudo_regs
)
250 return CURRENT_VARIANT
->register_names
[reg
];
255 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
257 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
258 return builtin_type_float
;
259 else if (reg
== iacc0_regnum
)
260 return builtin_type_int64
;
262 return builtin_type_int32
;
266 frv_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
267 int reg
, void *buffer
)
269 if (reg
== iacc0_regnum
)
271 regcache_raw_read (regcache
, iacc0h_regnum
, buffer
);
272 regcache_raw_read (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
277 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
278 int reg
, const void *buffer
)
280 if (reg
== iacc0_regnum
)
282 regcache_raw_write (regcache
, iacc0h_regnum
, buffer
);
283 regcache_raw_write (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
288 frv_register_sim_regno (int reg
)
290 static const int spr_map
[] =
292 H_SPR_PSR
, /* psr_regnum */
293 H_SPR_CCR
, /* ccr_regnum */
294 H_SPR_CCCR
, /* cccr_regnum */
298 H_SPR_TBR
, /* tbr_regnum */
299 H_SPR_BRR
, /* brr_regnum */
300 H_SPR_DBAR0
, /* dbar0_regnum */
301 H_SPR_DBAR1
, /* dbar1_regnum */
302 H_SPR_DBAR2
, /* dbar2_regnum */
303 H_SPR_DBAR3
, /* dbar3_regnum */
308 H_SPR_LR
, /* lr_regnum */
309 H_SPR_LCR
, /* lcr_regnum */
310 H_SPR_IACC0H
, /* iacc0h_regnum */
311 H_SPR_IACC0L
/* iacc0l_regnum */
314 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
316 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
317 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
318 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
319 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
320 else if (pc_regnum
== reg
)
321 return SIM_FRV_PC_REGNUM
;
322 else if (reg
>= first_spr_regnum
323 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
325 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
327 if (spr_reg_offset
< 0)
328 return SIM_REGNO_DOES_NOT_EXIST
;
330 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
333 internal_error (__FILE__
, __LINE__
, "Bad register number %d", reg
);
336 static const unsigned char *
337 frv_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenp
)
339 static unsigned char breakpoint
[] = {0xc0, 0x70, 0x00, 0x01};
340 *lenp
= sizeof (breakpoint
);
344 /* Define the maximum number of instructions which may be packed into a
345 bundle (VLIW instruction). */
346 static const int max_instrs_per_bundle
= 8;
348 /* Define the size (in bytes) of an FR-V instruction. */
349 static const int frv_instr_size
= 4;
351 /* Adjust a breakpoint's address to account for the FR-V architecture's
352 constraint that a break instruction must not appear as any but the
353 first instruction in the bundle. */
355 frv_gdbarch_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
357 int count
= max_instrs_per_bundle
;
358 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
359 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
361 /* Find the end of the previous packing sequence. This will be indicated
362 by either attempting to access some inaccessible memory or by finding
363 an instruction word whose packing bit is set to one. */
364 while (count
-- > 0 && addr
>= func_start
)
366 char instr
[frv_instr_size
];
369 status
= read_memory_nobpt (addr
, instr
, sizeof instr
);
374 /* This is a big endian architecture, so byte zero will have most
375 significant byte. The most significant bit of this byte is the
380 addr
-= frv_instr_size
;
384 bpaddr
= addr
+ frv_instr_size
;
390 /* Return true if REG is a caller-saves ("scratch") register,
393 is_caller_saves_reg (int reg
)
395 return ((4 <= reg
&& reg
<= 7)
396 || (14 <= reg
&& reg
<= 15)
397 || (32 <= reg
&& reg
<= 47));
401 /* Return true if REG is a callee-saves register, false otherwise. */
403 is_callee_saves_reg (int reg
)
405 return ((16 <= reg
&& reg
<= 31)
406 || (48 <= reg
&& reg
<= 63));
410 /* Return true if REG is an argument register, false otherwise. */
412 is_argument_reg (int reg
)
414 return (8 <= reg
&& reg
<= 13);
417 /* Scan an FR-V prologue, starting at PC, until frame->PC.
418 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
419 We assume FRAME's saved_regs array has already been allocated and cleared.
420 Return the first PC value after the prologue.
422 Note that, for unoptimized code, we almost don't need this function
423 at all; all arguments and locals live on the stack, so we just need
424 the FP to find everything. The catch: structures passed by value
425 have their addresses living in registers; they're never spilled to
426 the stack. So if you ever want to be able to get to these
427 arguments in any frame but the top, you'll need to do this serious
428 prologue analysis. */
430 frv_analyze_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
431 struct frv_unwind_cache
*info
)
433 /* When writing out instruction bitpatterns, we use the following
434 letters to label instruction fields:
435 P - The parallel bit. We don't use this.
436 J - The register number of GRj in the instruction description.
437 K - The register number of GRk in the instruction description.
438 I - The register number of GRi.
439 S - a signed imediate offset.
440 U - an unsigned immediate offset.
442 The dots below the numbers indicate where hex digit boundaries
443 fall, to make it easier to check the numbers. */
445 /* Non-zero iff we've seen the instruction that initializes the
446 frame pointer for this function's frame. */
449 /* If fp_set is non_zero, then this is the distance from
450 the stack pointer to frame pointer: fp = sp + fp_offset. */
453 /* Total size of frame prior to any alloca operations. */
456 /* Flag indicating if lr has been saved on the stack. */
457 int lr_saved_on_stack
= 0;
459 /* The number of the general-purpose register we saved the return
460 address ("link register") in, or -1 if we haven't moved it yet. */
461 int lr_save_reg
= -1;
463 /* Offset (from sp) at which lr has been saved on the stack. */
465 int lr_sp_offset
= 0;
467 /* If gr_saved[i] is non-zero, then we've noticed that general
468 register i has been saved at gr_sp_offset[i] from the stack
471 int gr_sp_offset
[64];
473 /* The address of the most recently scanned prologue instruction. */
474 CORE_ADDR last_prologue_pc
;
476 /* The address of the next instruction. */
479 /* The upper bound to of the pc values to scan. */
482 memset (gr_saved
, 0, sizeof (gr_saved
));
484 last_prologue_pc
= pc
;
486 /* Try to compute an upper limit (on how far to scan) based on the
488 lim_pc
= skip_prologue_using_sal (pc
);
489 /* If there's no line number info, lim_pc will be 0. In that case,
490 set the limit to be 100 instructions away from pc. Hopefully, this
491 will be far enough away to account for the entire prologue. Don't
492 worry about overshooting the end of the function. The scan loop
493 below contains some checks to avoid scanning unreasonably far. */
497 /* If we have a frame, we don't want to scan past the frame's pc. This
498 will catch those cases where the pc is in the prologue. */
501 CORE_ADDR frame_pc
= frame_pc_unwind (next_frame
);
502 if (frame_pc
< lim_pc
)
506 /* Scan the prologue. */
509 LONGEST op
= read_memory_integer (pc
, 4);
512 /* The tests in this chain of ifs should be in order of
513 decreasing selectivity, so that more particular patterns get
514 to fire before less particular patterns. */
516 /* Some sort of control transfer instruction: stop scanning prologue.
517 Integer Conditional Branch:
518 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
519 Floating-point / media Conditional Branch:
520 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
521 LCR Conditional Branch to LR
522 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
523 Integer conditional Branches to LR
524 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
525 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
526 Floating-point/Media Branches to LR
527 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
528 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
530 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
531 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
533 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
535 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
536 Integer Conditional Trap
537 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
538 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
539 Floating-point /media Conditional Trap
540 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
541 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
543 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
545 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
546 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
547 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
548 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
549 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
551 /* Stop scanning; not in prologue any longer. */
555 /* Loading something from memory into fp probably means that
556 we're in the epilogue. Stop scanning the prologue.
558 X 000010 0000010 XXXXXX 000100 XXXXXX
560 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
561 else if ((op
& 0x7ffc0fc0) == 0x04080100
562 || (op
& 0x7ffc0000) == 0x04c80000)
567 /* Setting the FP from the SP:
569 P 000010 0100010 000001 000000000000 = 0x04881000
570 0 111111 1111111 111111 111111111111 = 0x7fffffff
572 We treat this as part of the prologue. */
573 else if ((op
& 0x7fffffff) == 0x04881000)
577 last_prologue_pc
= next_pc
;
580 /* Move the link register to the scratch register grJ, before saving:
582 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
583 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
585 We treat this as part of the prologue. */
586 else if ((op
& 0x7fffffc0) == 0x080d01c0)
588 int gr_j
= op
& 0x3f;
590 /* If we're moving it to a scratch register, that's fine. */
591 if (is_caller_saves_reg (gr_j
))
594 last_prologue_pc
= next_pc
;
598 /* To save multiple callee-saves registers on the stack, at
602 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
603 0 000000 1111111 111111 111111 111111 = 0x01ffffff
606 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
607 0 000000 1111111 111111 111111 111111 = 0x01ffffff
609 We treat this as part of the prologue, and record the register's
610 saved address in the frame structure. */
611 else if ((op
& 0x01ffffff) == 0x000c10c0
612 || (op
& 0x01ffffff) == 0x000c1100)
614 int gr_k
= ((op
>> 25) & 0x3f);
615 int ope
= ((op
>> 6) & 0x3f);
619 /* Is it an std or an stq? */
625 /* Is it really a callee-saves register? */
626 if (is_callee_saves_reg (gr_k
))
628 for (i
= 0; i
< count
; i
++)
630 gr_saved
[gr_k
+ i
] = 1;
631 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
633 last_prologue_pc
= next_pc
;
637 /* Adjusting the stack pointer. (The stack pointer is GR1.)
639 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
640 0 111111 1111111 111111 000000000000 = 0x7ffff000
642 We treat this as part of the prologue. */
643 else if ((op
& 0x7ffff000) == 0x02401000)
647 /* Sign-extend the twelve-bit field.
648 (Isn't there a better way to do this?) */
649 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
652 last_prologue_pc
= pc
;
656 /* If the prologue is being adjusted again, we've
657 likely gone too far; i.e. we're probably in the
663 /* Setting the FP to a constant distance from the SP:
665 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
666 0 111111 1111111 111111 000000000000 = 0x7ffff000
668 We treat this as part of the prologue. */
669 else if ((op
& 0x7ffff000) == 0x04401000)
671 /* Sign-extend the twelve-bit field.
672 (Isn't there a better way to do this?) */
673 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
676 last_prologue_pc
= pc
;
679 /* To spill an argument register to a scratch register:
681 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
682 0 000000 1111111 000000 111111111111 = 0x01fc0fff
684 For the time being, we treat this as a prologue instruction,
685 assuming that GRi is an argument register. This one's kind
686 of suspicious, because it seems like it could be part of a
687 legitimate body instruction. But we only come here when the
688 source info wasn't helpful, so we have to do the best we can.
689 Hopefully once GCC and GDB agree on how to emit line number
690 info for prologues, then this code will never come into play. */
691 else if ((op
& 0x01fc0fff) == 0x00880000)
693 int gr_i
= ((op
>> 12) & 0x3f);
695 /* Make sure that the source is an arg register; if it is, we'll
696 treat it as a prologue instruction. */
697 if (is_argument_reg (gr_i
))
698 last_prologue_pc
= next_pc
;
701 /* To spill 16-bit values to the stack:
703 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
704 0 000000 1111111 111111 000000000000 = 0x01fff000
706 And for 8-bit values, we use STB instructions.
708 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
709 0 000000 1111111 111111 000000000000 = 0x01fff000
711 We check that GRk is really an argument register, and treat
712 all such as part of the prologue. */
713 else if ( (op
& 0x01fff000) == 0x01442000
714 || (op
& 0x01fff000) == 0x01402000)
716 int gr_k
= ((op
>> 25) & 0x3f);
718 /* Make sure that GRk is really an argument register; treat
719 it as a prologue instruction if so. */
720 if (is_argument_reg (gr_k
))
721 last_prologue_pc
= next_pc
;
724 /* To save multiple callee-saves register on the stack, at a
728 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
729 0 000000 1111111 111111 000000000000 = 0x01fff000
732 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
733 0 000000 1111111 111111 000000000000 = 0x01fff000
735 We treat this as part of the prologue, and record the register's
736 saved address in the frame structure. */
737 else if ((op
& 0x01fff000) == 0x014c1000
738 || (op
& 0x01fff000) == 0x01501000)
740 int gr_k
= ((op
>> 25) & 0x3f);
744 /* Is it a stdi or a stqi? */
745 if ((op
& 0x01fff000) == 0x014c1000)
750 /* Is it really a callee-saves register? */
751 if (is_callee_saves_reg (gr_k
))
753 /* Sign-extend the twelve-bit field.
754 (Isn't there a better way to do this?) */
755 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
757 for (i
= 0; i
< count
; i
++)
759 gr_saved
[gr_k
+ i
] = 1;
760 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
762 last_prologue_pc
= next_pc
;
766 /* Storing any kind of integer register at any constant offset
767 from any other register.
770 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
771 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
774 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
775 0 000000 1111111 000000 000000000000 = 0x01fc0000
777 These could be almost anything, but a lot of prologue
778 instructions fall into this pattern, so let's decode the
779 instruction once, and then work at a higher level. */
780 else if (((op
& 0x01fc0fff) == 0x000c0080)
781 || ((op
& 0x01fc0000) == 0x01480000))
783 int gr_k
= ((op
>> 25) & 0x3f);
784 int gr_i
= ((op
>> 12) & 0x3f);
787 /* Are we storing with gr0 as an offset, or using an
789 if ((op
& 0x01fc0fff) == 0x000c0080)
792 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
794 /* If the address isn't relative to the SP or FP, it's not a
795 prologue instruction. */
796 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
798 /* Do nothing; not a prologue instruction. */
801 /* Saving the old FP in the new frame (relative to the SP). */
802 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
804 gr_saved
[fp_regnum
] = 1;
805 gr_sp_offset
[fp_regnum
] = offset
;
806 last_prologue_pc
= next_pc
;
809 /* Saving callee-saves register(s) on the stack, relative to
811 else if (gr_i
== sp_regnum
812 && is_callee_saves_reg (gr_k
))
815 if (gr_i
== sp_regnum
)
816 gr_sp_offset
[gr_k
] = offset
;
818 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
819 last_prologue_pc
= next_pc
;
822 /* Saving the scratch register holding the return address. */
823 else if (lr_save_reg
!= -1
824 && gr_k
== lr_save_reg
)
826 lr_saved_on_stack
= 1;
827 if (gr_i
== sp_regnum
)
828 lr_sp_offset
= offset
;
830 lr_sp_offset
= offset
+ fp_offset
;
831 last_prologue_pc
= next_pc
;
834 /* Spilling int-sized arguments to the stack. */
835 else if (is_argument_reg (gr_k
))
836 last_prologue_pc
= next_pc
;
841 if (next_frame
&& info
)
846 /* If we know the relationship between the stack and frame
847 pointers, record the addresses of the registers we noticed.
848 Note that we have to do this as a separate step at the end,
849 because instructions may save relative to the SP, but we need
850 their addresses relative to the FP. */
852 frame_unwind_unsigned_register (next_frame
, fp_regnum
, &this_base
);
854 frame_unwind_unsigned_register (next_frame
, sp_regnum
, &this_base
);
856 for (i
= 0; i
< 64; i
++)
858 info
->saved_regs
[i
].addr
= this_base
- fp_offset
+ gr_sp_offset
[i
];
860 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
861 info
->base
= this_base
;
863 /* If LR was saved on the stack, record its location. */
864 if (lr_saved_on_stack
)
865 info
->saved_regs
[lr_regnum
].addr
= this_base
- fp_offset
+ lr_sp_offset
;
867 /* The call instruction moves the caller's PC in the callee's LR.
868 Since this is an unwind, do the reverse. Copy the location of LR
869 into PC (the address / regnum) so that a request for PC will be
870 converted into a request for the LR. */
871 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
873 /* Save the previous frame's computed SP value. */
874 trad_frame_set_value (info
->saved_regs
, sp_regnum
, info
->prev_sp
);
877 return last_prologue_pc
;
882 frv_skip_prologue (CORE_ADDR pc
)
884 CORE_ADDR func_addr
, func_end
, new_pc
;
888 /* If the line table has entry for a line *within* the function
889 (i.e., not in the prologue, and not past the end), then that's
891 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
893 struct symtab_and_line sal
;
895 sal
= find_pc_line (func_addr
, 0);
897 if (sal
.line
!= 0 && sal
.end
< func_end
)
903 /* The FR-V prologue is at least five instructions long (twenty bytes).
904 If we didn't find a real source location past that, then
905 do a full analysis of the prologue. */
906 if (new_pc
< pc
+ 20)
907 new_pc
= frv_analyze_prologue (pc
, 0, 0);
913 static struct frv_unwind_cache
*
914 frv_frame_unwind_cache (struct frame_info
*next_frame
,
915 void **this_prologue_cache
)
917 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
921 struct frv_unwind_cache
*info
;
923 if ((*this_prologue_cache
))
924 return (*this_prologue_cache
);
926 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
927 (*this_prologue_cache
) = info
;
928 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
930 /* Prologue analysis does the rest... */
931 frv_analyze_prologue (frame_func_unwind (next_frame
), next_frame
, info
);
937 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
940 int len
= TYPE_LENGTH (type
);
945 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
946 store_unsigned_integer (valbuf
, len
, gpr8_val
);
951 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
952 store_unsigned_integer (valbuf
, 4, regval
);
953 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
954 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, regval
);
957 internal_error (__FILE__
, __LINE__
, "Illegal return value length: %d", len
);
961 frv_extract_struct_value_address (struct regcache
*regcache
)
964 regcache_cooked_read_unsigned (regcache
, struct_return_regnum
, &addr
);
969 frv_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
971 write_register (struct_return_regnum
, addr
);
975 frv_frameless_function_invocation (struct frame_info
*frame
)
977 return legacy_frameless_look_for_prologue (frame
);
981 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
983 /* Require dword alignment. */
984 return align_down (sp
, 8);
988 frv_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
989 struct regcache
*regcache
, CORE_ADDR bp_addr
,
990 int nargs
, struct value
**args
, CORE_ADDR sp
,
991 int struct_return
, CORE_ADDR struct_addr
)
998 struct type
*arg_type
;
1000 enum type_code typecode
;
1006 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1007 nargs
, (int) sp
, struct_return
, struct_addr
);
1011 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1012 stack_space
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), 4);
1014 stack_space
-= (6 * 4);
1015 if (stack_space
> 0)
1018 /* Make sure stack is dword aligned. */
1019 sp
= align_down (sp
, 8);
1026 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1029 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1032 arg_type
= check_typedef (VALUE_TYPE (arg
));
1033 len
= TYPE_LENGTH (arg_type
);
1034 typecode
= TYPE_CODE (arg_type
);
1036 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1038 store_unsigned_integer (valbuf
, 4, VALUE_ADDRESS (arg
));
1039 typecode
= TYPE_CODE_PTR
;
1045 val
= (char *) VALUE_CONTENTS (arg
);
1050 int partial_len
= (len
< 4 ? len
: 4);
1054 regval
= extract_unsigned_integer (val
, partial_len
);
1056 printf(" Argnum %d data %x -> reg %d\n",
1057 argnum
, (int) regval
, argreg
);
1059 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1065 printf(" Argnum %d data %x -> offset %d (%x)\n",
1066 argnum
, *((int *)val
), stack_offset
, (int) (sp
+ stack_offset
));
1068 write_memory (sp
+ stack_offset
, val
, partial_len
);
1069 stack_offset
+= align_up (partial_len
, 4);
1076 /* Set the return address. For the frv, the return breakpoint is
1077 always at BP_ADDR. */
1078 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1080 /* Finally, update the SP register. */
1081 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1087 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1090 int len
= TYPE_LENGTH (type
);
1095 memset (val
, 0, sizeof (val
));
1096 memcpy (val
+ (4 - len
), valbuf
, len
);
1097 regcache_cooked_write (regcache
, 8, val
);
1101 regcache_cooked_write (regcache
, 8, valbuf
);
1102 regcache_cooked_write (regcache
, 9, (bfd_byte
*) valbuf
+ 4);
1105 internal_error (__FILE__
, __LINE__
,
1106 "Don't know how to return a %d-byte value.", len
);
1110 /* Hardware watchpoint / breakpoint support for the FR500
1114 frv_check_watch_resources (int type
, int cnt
, int ot
)
1116 struct gdbarch_tdep
*var
= CURRENT_VARIANT
;
1118 /* Watchpoints not supported on simulator. */
1119 if (strcmp (target_shortname
, "sim") == 0)
1122 if (type
== bp_hardware_breakpoint
)
1124 if (var
->num_hw_breakpoints
== 0)
1126 else if (cnt
<= var
->num_hw_breakpoints
)
1131 if (var
->num_hw_watchpoints
== 0)
1135 else if (cnt
<= var
->num_hw_watchpoints
)
1143 frv_stopped_data_address (void)
1145 CORE_ADDR brr
, dbar0
, dbar1
, dbar2
, dbar3
;
1147 brr
= read_register (brr_regnum
);
1148 dbar0
= read_register (dbar0_regnum
);
1149 dbar1
= read_register (dbar1_regnum
);
1150 dbar2
= read_register (dbar2_regnum
);
1151 dbar3
= read_register (dbar3_regnum
);
1155 else if (brr
& (1<<10))
1157 else if (brr
& (1<<9))
1159 else if (brr
& (1<<8))
1166 frv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1168 return frame_unwind_register_unsigned (next_frame
, pc_regnum
);
1171 /* Given a GDB frame, determine the address of the calling function's
1172 frame. This will be used to create a new GDB frame struct. */
1175 frv_frame_this_id (struct frame_info
*next_frame
,
1176 void **this_prologue_cache
, struct frame_id
*this_id
)
1178 struct frv_unwind_cache
*info
1179 = frv_frame_unwind_cache (next_frame
, this_prologue_cache
);
1182 struct minimal_symbol
*msym_stack
;
1185 /* The FUNC is easy. */
1186 func
= frame_func_unwind (next_frame
);
1188 /* Check if the stack is empty. */
1189 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1190 if (msym_stack
&& info
->base
== SYMBOL_VALUE_ADDRESS (msym_stack
))
1193 /* Hopefully the prologue analysis either correctly determined the
1194 frame's base (which is the SP from the previous frame), or set
1195 that base to "NULL". */
1196 base
= info
->prev_sp
;
1200 id
= frame_id_build (base
, func
);
1202 /* Check that we're not going round in circles with the same frame
1203 ID (but avoid applying the test to sentinel frames which do go
1204 round in circles). Can't use frame_id_eq() as that doesn't yet
1205 compare the frame's PC value. */
1206 if (frame_relative_level (next_frame
) >= 0
1207 && get_frame_type (next_frame
) != DUMMY_FRAME
1208 && frame_id_eq (get_frame_id (next_frame
), id
))
1215 frv_frame_prev_register (struct frame_info
*next_frame
,
1216 void **this_prologue_cache
,
1217 int regnum
, int *optimizedp
,
1218 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1219 int *realnump
, void *bufferp
)
1221 struct frv_unwind_cache
*info
1222 = frv_frame_unwind_cache (next_frame
, this_prologue_cache
);
1223 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1224 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
1227 static const struct frame_unwind frv_frame_unwind
= {
1230 frv_frame_prev_register
1233 static const struct frame_unwind
*
1234 frv_frame_sniffer (struct frame_info
*next_frame
)
1236 return &frv_frame_unwind
;
1240 frv_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1242 struct frv_unwind_cache
*info
1243 = frv_frame_unwind_cache (next_frame
, this_cache
);
1247 static const struct frame_base frv_frame_base
= {
1249 frv_frame_base_address
,
1250 frv_frame_base_address
,
1251 frv_frame_base_address
1255 frv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1257 return frame_unwind_register_unsigned (next_frame
, sp_regnum
);
1261 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1262 dummy frame. The frame ID's base needs to match the TOS value
1263 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1266 static struct frame_id
1267 frv_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1269 return frame_id_build (frv_unwind_sp (gdbarch
, next_frame
),
1270 frame_pc_unwind (next_frame
));
1274 static struct gdbarch
*
1275 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1277 struct gdbarch
*gdbarch
;
1278 struct gdbarch_tdep
*var
;
1280 /* Check to see if we've already built an appropriate architecture
1281 object for this executable. */
1282 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1284 return arches
->gdbarch
;
1286 /* Select the right tdep structure for this variant. */
1287 var
= new_variant ();
1288 switch (info
.bfd_arch_info
->mach
)
1291 case bfd_mach_frvsimple
:
1292 case bfd_mach_fr500
:
1293 case bfd_mach_frvtomcat
:
1294 case bfd_mach_fr550
:
1295 set_variant_num_gprs (var
, 64);
1296 set_variant_num_fprs (var
, 64);
1299 case bfd_mach_fr400
:
1300 set_variant_num_gprs (var
, 32);
1301 set_variant_num_fprs (var
, 32);
1305 /* Never heard of this variant. */
1309 gdbarch
= gdbarch_alloc (&info
, var
);
1311 set_gdbarch_short_bit (gdbarch
, 16);
1312 set_gdbarch_int_bit (gdbarch
, 32);
1313 set_gdbarch_long_bit (gdbarch
, 32);
1314 set_gdbarch_long_long_bit (gdbarch
, 64);
1315 set_gdbarch_float_bit (gdbarch
, 32);
1316 set_gdbarch_double_bit (gdbarch
, 64);
1317 set_gdbarch_long_double_bit (gdbarch
, 64);
1318 set_gdbarch_ptr_bit (gdbarch
, 32);
1320 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1321 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1323 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1324 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1325 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1327 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1328 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1329 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1331 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1332 set_gdbarch_pseudo_register_write (gdbarch
, frv_pseudo_register_write
);
1334 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1335 set_gdbarch_breakpoint_from_pc (gdbarch
, frv_breakpoint_from_pc
);
1336 set_gdbarch_adjust_breakpoint_address (gdbarch
, frv_gdbarch_adjust_breakpoint_address
);
1338 set_gdbarch_deprecated_frameless_function_invocation (gdbarch
, frv_frameless_function_invocation
);
1340 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
1341 set_gdbarch_extract_return_value (gdbarch
, frv_extract_return_value
);
1343 set_gdbarch_deprecated_store_struct_return (gdbarch
, frv_store_struct_return
);
1344 set_gdbarch_store_return_value (gdbarch
, frv_store_return_value
);
1345 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, frv_extract_struct_value_address
);
1348 set_gdbarch_unwind_pc (gdbarch
, frv_unwind_pc
);
1349 set_gdbarch_unwind_sp (gdbarch
, frv_unwind_sp
);
1350 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1351 frame_unwind_append_sniffer (gdbarch
, frv_frame_sniffer
);
1352 frame_base_set_default (gdbarch
, &frv_frame_base
);
1354 /* Settings for calling functions in the inferior. */
1355 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1356 set_gdbarch_unwind_dummy_id (gdbarch
, frv_unwind_dummy_id
);
1358 /* Settings that should be unnecessary. */
1359 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1361 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
1363 set_gdbarch_remote_translate_xfer_address
1364 (gdbarch
, generic_remote_translate_xfer_address
);
1366 /* Hardware watchpoint / breakpoint support. */
1367 switch (info
.bfd_arch_info
->mach
)
1370 case bfd_mach_frvsimple
:
1371 case bfd_mach_fr500
:
1372 case bfd_mach_frvtomcat
:
1373 /* fr500-style hardware debugging support. */
1374 var
->num_hw_watchpoints
= 4;
1375 var
->num_hw_breakpoints
= 4;
1378 case bfd_mach_fr400
:
1379 /* fr400-style hardware debugging support. */
1380 var
->num_hw_watchpoints
= 2;
1381 var
->num_hw_breakpoints
= 4;
1385 /* Otherwise, assume we don't have hardware debugging support. */
1386 var
->num_hw_watchpoints
= 0;
1387 var
->num_hw_breakpoints
= 0;
1391 set_gdbarch_print_insn (gdbarch
, print_insn_frv
);
1397 _initialize_frv_tdep (void)
1399 register_gdbarch_init (bfd_arch_frv
, frv_gdbarch_init
);