1 /* Debug register code for the i386.
3 Copyright (C) 2009-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* Support for 8-byte wide hw watchpoints. */
25 #ifndef TARGET_HAS_DR_LEN_8
26 /* NOTE: sizeof (long) == 4 on win64. */
27 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
30 enum target_hw_bp_type
32 hw_write
= 0, /* Common HW watchpoint */
33 hw_read
= 1, /* Read HW watchpoint */
34 hw_access
= 2, /* Access HW watchpoint */
35 hw_execute
= 3 /* Execute HW breakpoint */
38 /* DR7 Debug Control register fields. */
40 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
41 #define DR_CONTROL_SHIFT 16
42 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
43 #define DR_CONTROL_SIZE 4
45 /* Watchpoint/breakpoint read/write fields in DR7. */
46 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
47 #define DR_RW_WRITE (0x1) /* Break on data writes. */
48 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
50 /* This is here for completeness. No platform supports this
51 functionality yet (as of March 2001). Note that the DE flag in the
52 CR4 register needs to be set to support this. */
54 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
57 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
58 is so we could OR this with the read/write field defined above. */
59 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
60 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
61 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
62 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
64 /* Local and Global Enable flags in DR7.
66 When the Local Enable flag is set, the breakpoint/watchpoint is
67 enabled only for the current task; the processor automatically
68 clears this flag on every task switch. When the Global Enable flag
69 is set, the breakpoint/watchpoint is enabled for all tasks; the
70 processor never clears this flag.
72 Currently, all watchpoint are locally enabled. If you need to
73 enable them globally, read the comment which pertains to this in
74 i386_insert_aligned_watchpoint below. */
75 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
76 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
77 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
79 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
80 flags). These are only required on i386, to allow detection of the
81 exact instruction which caused a watchpoint to break; i486 and
82 later processors do that automatically. We set these flags for
83 backwards compatibility. */
84 #define DR_LOCAL_SLOWDOWN (0x100)
85 #define DR_GLOBAL_SLOWDOWN (0x200)
87 /* Fields reserved by Intel. This includes the GD (General Detect
88 Enable) flag, which causes a debug exception to be generated when a
89 MOV instruction accesses one of the debug registers.
91 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
92 #define DR_CONTROL_RESERVED (0xFC00)
94 /* Auxiliary helper macros. */
96 /* A value that masks all fields in DR7 that are reserved by Intel. */
97 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
99 /* The I'th debug register is vacant if its Local and Global Enable
100 bits are reset in the Debug Control register. */
101 #define I386_DR_VACANT(state, i) \
102 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
104 /* Locally enable the break/watchpoint in the I'th debug register. */
105 #define I386_DR_LOCAL_ENABLE(state, i) \
107 (state)->dr_control_mirror |= \
108 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
111 /* Globally enable the break/watchpoint in the I'th debug register. */
112 #define I386_DR_GLOBAL_ENABLE(state, i) \
114 (state)->dr_control_mirror |= \
115 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
118 /* Disable the break/watchpoint in the I'th debug register. */
119 #define I386_DR_DISABLE(state, i) \
121 (state)->dr_control_mirror &= \
122 ~(3 << (DR_ENABLE_SIZE * (i))); \
125 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
126 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
128 (state)->dr_control_mirror &= \
129 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
130 (state)->dr_control_mirror |= \
131 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
134 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
135 #define I386_DR_GET_RW_LEN(dr7, i) \
137 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
139 /* Did the watchpoint whose address is in the I'th register break? */
140 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
142 /* A macro to loop over all debug registers. */
143 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
145 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
146 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
148 /* Implementation. */
150 /* Clear the reference counts and forget everything we knew about the
154 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
158 ALL_DEBUG_REGISTERS (i
)
160 state
->dr_mirror
[i
] = 0;
161 state
->dr_ref_count
[i
] = 0;
163 state
->dr_control_mirror
= 0;
164 state
->dr_status_mirror
= 0;
167 /* Print the values of the mirrored debug registers. This is enabled via
168 the "set debug-hw-points 1" monitor command. */
171 i386_show_dr (struct i386_debug_reg_state
*state
,
172 const char *func
, CORE_ADDR addr
,
173 int len
, enum target_hw_bp_type type
)
177 fprintf (stderr
, "%s", func
);
179 fprintf (stderr
, " (addr=%lx, len=%d, type=%s)",
180 (unsigned long) addr
, len
,
181 type
== hw_write
? "data-write"
182 : (type
== hw_read
? "data-read"
183 : (type
== hw_access
? "data-read/write"
184 : (type
== hw_execute
? "instruction-execute"
185 /* FIXME: if/when I/O read/write
186 watchpoints are supported, add them
189 fprintf (stderr
, ":\n");
190 fprintf (stderr
, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
191 state
->dr_control_mirror
, state
->dr_status_mirror
);
192 ALL_DEBUG_REGISTERS (i
)
195 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
196 i
, paddress (state
->dr_mirror
[i
]),
197 state
->dr_ref_count
[i
],
198 i
+ 1, paddress (state
->dr_mirror
[i
+ 1]),
199 state
->dr_ref_count
[i
+ 1]);
204 /* Return the value of a 4-bit field for DR7 suitable for watching a
205 region of LEN bytes for accesses of type TYPE. LEN is assumed to
206 have the value of 1, 2, or 4. */
209 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
222 fatal ("The i386 doesn't support data-read watchpoints.\n");
227 /* Not yet supported. */
234 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
241 return (DR_LEN_1
| rw
);
243 return (DR_LEN_2
| rw
);
245 return (DR_LEN_4
| rw
);
247 if (TARGET_HAS_DR_LEN_8
)
248 return (DR_LEN_8
| rw
);
249 /* ELSE FALL THROUGH */
252 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
256 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
257 according to the length of the region to watch. LEN_RW_BITS is the
258 value of the bits from DR7 which describes the length and access
259 type of the region to be watched by this watchpoint. Return 0 on
260 success, -1 on failure. */
263 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
264 CORE_ADDR addr
, unsigned len_rw_bits
)
268 /* First, look for an occupied debug register with the same address
269 and the same RW and LEN definitions. If we find one, we can
270 reuse it for this watchpoint as well (and save a register). */
271 ALL_DEBUG_REGISTERS (i
)
273 if (!I386_DR_VACANT (state
, i
)
274 && state
->dr_mirror
[i
] == addr
275 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
277 state
->dr_ref_count
[i
]++;
282 /* Next, look for a vacant debug register. */
283 ALL_DEBUG_REGISTERS (i
)
285 if (I386_DR_VACANT (state
, i
))
289 /* No more debug registers! */
293 /* Now set up the register I to watch our region. */
295 /* Record the info in our local mirrored array. */
296 state
->dr_mirror
[i
] = addr
;
297 state
->dr_ref_count
[i
] = 1;
298 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
299 /* Note: we only enable the watchpoint locally, i.e. in the current
300 task. Currently, no i386 target allows or supports global
301 watchpoints; however, if any target would want that in the
302 future, GDB should probably provide a command to control whether
303 to enable watchpoints globally or locally, and the code below
304 should use global or local enable and slow-down flags as
306 I386_DR_LOCAL_ENABLE (state
, i
);
307 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
308 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
313 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
314 according to the length of the region to watch. LEN_RW_BITS is the
315 value of the bits from DR7 which describes the length and access
316 type of the region watched by this watchpoint. Return 0 on
317 success, -1 on failure. */
320 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
321 CORE_ADDR addr
, unsigned len_rw_bits
)
325 ALL_DEBUG_REGISTERS (i
)
327 if (!I386_DR_VACANT (state
, i
)
328 && state
->dr_mirror
[i
] == addr
329 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
331 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
333 /* Reset our mirror. */
334 state
->dr_mirror
[i
] = 0;
335 I386_DR_DISABLE (state
, i
);
344 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
345 number of debug registers required to watch a region at address
346 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
347 successful insertion or removal, a positive number when queried
348 about the number of registers, or -1 on failure. If WHAT is not a
349 valid value, bombs through internal_error. */
352 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
353 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
354 enum target_hw_bp_type type
)
357 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
359 static const int size_try_array
[8][8] =
361 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
362 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
363 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
364 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
365 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
366 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
367 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
368 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
373 int align
= addr
% max_wp_len
;
374 /* Four (eight on AMD64) is the maximum length a debug register
376 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
377 int size
= size_try_array
[try][align
];
379 if (what
== WP_COUNT
)
381 /* size_try_array[] is defined such that each iteration
382 through the loop is guaranteed to produce an address and a
383 size that can be watched with a single debug register.
384 Thus, for counting the registers required to watch a
385 region, we simply need to increment the count on each
391 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
393 if (what
== WP_INSERT
)
394 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
395 else if (what
== WP_REMOVE
)
396 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
399 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
413 #define Z_PACKET_HW_BP '1'
414 #define Z_PACKET_WRITE_WP '2'
415 #define Z_PACKET_READ_WP '3'
416 #define Z_PACKET_ACCESS_WP '4'
418 /* Map the protocol watchpoint type TYPE to enum target_hw_bp_type. */
420 static enum target_hw_bp_type
421 Z_packet_to_hw_type (char type
)
427 case Z_PACKET_WRITE_WP
:
429 case Z_PACKET_READ_WP
:
431 case Z_PACKET_ACCESS_WP
:
434 fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type
);
438 /* Update the inferior debug registers state, in INF_STATE, with the
439 new debug registers state, in NEW_STATE. */
442 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*inf_state
,
443 struct i386_debug_reg_state
*new_state
)
447 ALL_DEBUG_REGISTERS (i
)
449 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (inf_state
, i
))
450 i386_dr_low_set_addr (new_state
, i
);
452 gdb_assert (new_state
->dr_mirror
[i
] == inf_state
->dr_mirror
[i
]);
455 if (new_state
->dr_control_mirror
!= inf_state
->dr_control_mirror
)
456 i386_dr_low_set_control (new_state
);
458 *inf_state
= *new_state
;
461 /* Insert a watchpoint to watch a memory region which starts at
462 address ADDR and whose length is LEN bytes. Watch memory accesses
463 of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
466 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
467 char type_from_packet
, CORE_ADDR addr
, int len
)
470 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
471 /* Work on a local copy of the debug registers, and on success,
472 commit the change back to the inferior. */
473 struct i386_debug_reg_state local_state
= *state
;
476 return 1; /* unsupported */
478 if (((len
!= 1 && len
!= 2 && len
!= 4)
479 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
482 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_INSERT
,
487 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
489 retval
= i386_insert_aligned_watchpoint (&local_state
, addr
, len_rw
);
493 i386_update_inferior_debug_regs (state
, &local_state
);
496 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
501 /* Remove a watchpoint that watched the memory region which starts at
502 address ADDR, whose length is LEN bytes, and for accesses of the
503 type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
506 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
507 char type_from_packet
, CORE_ADDR addr
, int len
)
510 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
511 /* Work on a local copy of the debug registers, and on success,
512 commit the change back to the inferior. */
513 struct i386_debug_reg_state local_state
= *state
;
515 if (((len
!= 1 && len
!= 2 && len
!= 4)
516 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
519 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_REMOVE
,
524 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
526 retval
= i386_remove_aligned_watchpoint (&local_state
, addr
, len_rw
);
530 i386_update_inferior_debug_regs (state
, &local_state
);
533 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
538 /* Return non-zero if we can watch a memory region that starts at
539 address ADDR and whose length is LEN bytes. */
542 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
543 CORE_ADDR addr
, int len
)
547 /* Compute how many aligned watchpoints we would need to cover this
549 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
550 addr
, len
, hw_write
);
551 return nregs
<= DR_NADDR
? 1 : 0;
554 /* If the inferior has some break/watchpoint that triggered, set the
555 address associated with that break/watchpoint and return true.
556 Otherwise, return false. */
559 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
565 /* The current thread's DR_STATUS. We always need to read this to
566 check whether some watchpoint caused the trap. */
568 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
569 data breakpoint trap. Only fetch it when necessary, to avoid an
570 unnecessary extra syscall when no watchpoint triggered. */
572 unsigned control
= 0;
574 /* In non-stop/async, threads can be running while we change the
575 global dr_mirror (and friends). Say, we set a watchpoint, and
576 let threads resume. Now, say you delete the watchpoint, or
577 add/remove watchpoints such that dr_mirror changes while threads
578 are running. On targets that support non-stop,
579 inserting/deleting watchpoints updates the global dr_mirror only.
580 It does not update the real thread's debug registers; that's only
581 done prior to resume. Instead, if threads are running when the
582 mirror changes, a temporary and transparent stop on all threads
583 is forced so they can get their copy of the debug registers
584 updated on re-resume. Now, say, a thread hit a watchpoint before
585 having been updated with the new dr_mirror contents, and we
586 haven't yet handled the corresponding SIGTRAP. If we trusted
587 dr_mirror below, we'd mistake the real trapped address (from the
588 last time we had updated debug registers in the thread) with
589 whatever was currently in dr_mirror. So to fix this, dr_mirror
590 always represents intention, what we _want_ threads to have in
591 debug registers. To get at the address and cause of the trap, we
592 need to read the state the thread still has in its debug
595 In sum, always get the current debug register values the current
596 thread has, instead of trusting the global mirror. If the thread
597 was running when we last changed watchpoints, the mirror no
598 longer represents what was set in this thread's debug
600 status
= i386_dr_low_get_status ();
602 ALL_DEBUG_REGISTERS (i
)
604 if (!I386_DR_WATCH_HIT (status
, i
))
609 control
= i386_dr_low_get_control ();
613 /* This second condition makes sure DRi is set up for a data
614 watchpoint, not a hardware breakpoint. The reason is that
615 GDB doesn't call the target_stopped_data_address method
616 except for data watchpoints. In other words, I'm being
618 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
620 addr
= i386_dr_low_get_addr (i
);
623 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
627 if (debug_hw_points
&& addr
== 0)
628 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
635 /* Return true if the inferior has some watchpoint that triggered.
636 Otherwise return false. */
639 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
642 return i386_low_stopped_data_address (state
, &addr
);