1 /* Debug register code for the i386.
3 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* Support for hardware watchpoints and breakpoints using the i386
27 This provides several functions for inserting and removing
28 hardware-assisted breakpoints and watchpoints, testing if one or
29 more of the watchpoints triggered and at what address, checking
30 whether a given region can be watched, etc.
32 The functions below implement debug registers sharing by reference
33 counts, and allow to watch regions up to 16 bytes long. */
35 /* Debug register size, in bytes. */
36 /* NOTE: sizeof (long) == 4 on win64. */
37 #define i386_get_debug_register_length() (sizeof (void *))
39 /* Support for 8-byte wide hw watchpoints. */
40 #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8)
42 /* DR7 Debug Control register fields. */
44 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
45 #define DR_CONTROL_SHIFT 16
46 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
47 #define DR_CONTROL_SIZE 4
49 /* Watchpoint/breakpoint read/write fields in DR7. */
50 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
51 #define DR_RW_WRITE (0x1) /* Break on data writes. */
52 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
54 /* This is here for completeness. No platform supports this
55 functionality yet (as of March 2001). Note that the DE flag in the
56 CR4 register needs to be set to support this. */
58 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
61 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
62 is so we could OR this with the read/write field defined above. */
63 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
64 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
65 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
66 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
68 /* Local and Global Enable flags in DR7.
70 When the Local Enable flag is set, the breakpoint/watchpoint is
71 enabled only for the current task; the processor automatically
72 clears this flag on every task switch. When the Global Enable flag
73 is set, the breakpoint/watchpoint is enabled for all tasks; the
74 processor never clears this flag.
76 Currently, all watchpoint are locally enabled. If you need to
77 enable them globally, read the comment which pertains to this in
78 i386_insert_aligned_watchpoint below. */
79 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
80 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
81 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
83 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
84 flags). These are only required on i386, to allow detection of the
85 exact instruction which caused a watchpoint to break; i486 and
86 later processors do that automatically. We set these flags for
87 backwards compatibility. */
88 #define DR_LOCAL_SLOWDOWN (0x100)
89 #define DR_GLOBAL_SLOWDOWN (0x200)
91 /* Fields reserved by Intel. This includes the GD (General Detect
92 Enable) flag, which causes a debug exception to be generated when a
93 MOV instruction accesses one of the debug registers.
95 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
96 #define DR_CONTROL_RESERVED (0xFC00)
98 /* Auxiliary helper macros. */
100 /* A value that masks all fields in DR7 that are reserved by Intel. */
101 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
103 /* The I'th debug register is vacant if its Local and Global Enable
104 bits are reset in the Debug Control register. */
105 #define I386_DR_VACANT(state, i) \
106 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
108 /* Locally enable the break/watchpoint in the I'th debug register. */
109 #define I386_DR_LOCAL_ENABLE(state, i) \
111 (state)->dr_control_mirror |= \
112 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
115 /* Globally enable the break/watchpoint in the I'th debug register. */
116 #define I386_DR_GLOBAL_ENABLE(state, i) \
118 (state)->dr_control_mirror |= \
119 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
122 /* Disable the break/watchpoint in the I'th debug register. */
123 #define I386_DR_DISABLE(state, i) \
125 (state)->dr_control_mirror &= \
126 ~(3 << (DR_ENABLE_SIZE * (i))); \
129 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
130 #define I386_DR_SET_RW_LEN(state, i, rwlen) \
132 (state)->dr_control_mirror &= \
133 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
134 (state)->dr_control_mirror |= \
135 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
138 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
139 #define I386_DR_GET_RW_LEN(dr7, i) \
141 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
143 /* Did the watchpoint whose address is in the I'th register break? */
144 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
146 /* A macro to loop over all debug registers. */
147 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
149 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
150 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
152 /* Implementation. */
154 /* Clear the reference counts and forget everything we knew about the
158 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
162 ALL_DEBUG_REGISTERS (i
)
164 state
->dr_mirror
[i
] = 0;
165 state
->dr_ref_count
[i
] = 0;
167 state
->dr_control_mirror
= 0;
168 state
->dr_status_mirror
= 0;
171 /* Print the values of the mirrored debug registers. */
174 i386_show_dr (struct i386_debug_reg_state
*state
,
175 const char *func
, CORE_ADDR addr
,
176 int len
, enum target_hw_bp_type type
)
180 debug_printf ("%s", func
);
182 debug_printf (" (addr=%s, len=%d, type=%s)",
184 type
== hw_write
? "data-write"
185 : (type
== hw_read
? "data-read"
186 : (type
== hw_access
? "data-read/write"
187 : (type
== hw_execute
? "instruction-execute"
188 /* FIXME: if/when I/O read/write
189 watchpoints are supported, add them
192 debug_printf (":\n");
193 debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
194 phex (state
->dr_control_mirror
, 8),
195 phex (state
->dr_status_mirror
, 8));
196 ALL_DEBUG_REGISTERS (i
)
199 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
200 i
, phex (state
->dr_mirror
[i
],
201 i386_get_debug_register_length ()),
202 state
->dr_ref_count
[i
],
203 i
+ 1, phex (state
->dr_mirror
[i
+ 1],
204 i386_get_debug_register_length ()),
205 state
->dr_ref_count
[i
+ 1]);
210 /* Return the value of a 4-bit field for DR7 suitable for watching a
211 region of LEN bytes for accesses of type TYPE. LEN is assumed to
212 have the value of 1, 2, or 4. */
215 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
228 fatal ("The i386 doesn't support data-read watchpoints.\n");
233 /* Not yet supported. */
240 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
247 return (DR_LEN_1
| rw
);
249 return (DR_LEN_2
| rw
);
251 return (DR_LEN_4
| rw
);
253 if (TARGET_HAS_DR_LEN_8
)
254 return (DR_LEN_8
| rw
);
255 /* ELSE FALL THROUGH */
258 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
262 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
263 according to the length of the region to watch. LEN_RW_BITS is the
264 value of the bits from DR7 which describes the length and access
265 type of the region to be watched by this watchpoint. Return 0 on
266 success, -1 on failure. */
269 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
270 CORE_ADDR addr
, unsigned len_rw_bits
)
274 /* First, look for an occupied debug register with the same address
275 and the same RW and LEN definitions. If we find one, we can
276 reuse it for this watchpoint as well (and save a register). */
277 ALL_DEBUG_REGISTERS (i
)
279 if (!I386_DR_VACANT (state
, i
)
280 && state
->dr_mirror
[i
] == addr
281 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
283 state
->dr_ref_count
[i
]++;
288 /* Next, look for a vacant debug register. */
289 ALL_DEBUG_REGISTERS (i
)
291 if (I386_DR_VACANT (state
, i
))
295 /* No more debug registers! */
299 /* Now set up the register I to watch our region. */
301 /* Record the info in our local mirrored array. */
302 state
->dr_mirror
[i
] = addr
;
303 state
->dr_ref_count
[i
] = 1;
304 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
305 /* Note: we only enable the watchpoint locally, i.e. in the current
306 task. Currently, no i386 target allows or supports global
307 watchpoints; however, if any target would want that in the
308 future, GDB should probably provide a command to control whether
309 to enable watchpoints globally or locally, and the code below
310 should use global or local enable and slow-down flags as
312 I386_DR_LOCAL_ENABLE (state
, i
);
313 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
314 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
319 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
320 according to the length of the region to watch. LEN_RW_BITS is the
321 value of the bits from DR7 which describes the length and access
322 type of the region watched by this watchpoint. Return 0 on
323 success, -1 on failure. */
326 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
327 CORE_ADDR addr
, unsigned len_rw_bits
)
331 ALL_DEBUG_REGISTERS (i
)
333 if (!I386_DR_VACANT (state
, i
)
334 && state
->dr_mirror
[i
] == addr
335 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
337 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
339 /* Reset our mirror. */
340 state
->dr_mirror
[i
] = 0;
341 I386_DR_DISABLE (state
, i
);
350 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
351 number of debug registers required to watch a region at address
352 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
353 successful insertion or removal, a positive number when queried
354 about the number of registers, or -1 on failure. If WHAT is not a
355 valid value, bombs through internal_error. */
358 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
359 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
360 enum target_hw_bp_type type
)
363 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
365 static const int size_try_array
[8][8] =
367 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
368 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
369 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
370 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
371 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
372 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
373 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
374 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
379 int align
= addr
% max_wp_len
;
380 /* Four (eight on AMD64) is the maximum length a debug register
382 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
383 int size
= size_try_array
[try][align
];
385 if (what
== WP_COUNT
)
387 /* size_try_array[] is defined such that each iteration
388 through the loop is guaranteed to produce an address and a
389 size that can be watched with a single debug register.
390 Thus, for counting the registers required to watch a
391 region, we simply need to increment the count on each
397 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
399 if (what
== WP_INSERT
)
400 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
401 else if (what
== WP_REMOVE
)
402 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
405 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
419 /* Update the inferior debug registers state, in INF_STATE, with the
420 new debug registers state, in NEW_STATE. */
423 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*inf_state
,
424 struct i386_debug_reg_state
*new_state
)
428 ALL_DEBUG_REGISTERS (i
)
430 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (inf_state
, i
))
431 i386_dr_low_set_addr (new_state
, i
);
433 gdb_assert (new_state
->dr_mirror
[i
] == inf_state
->dr_mirror
[i
]);
436 if (new_state
->dr_control_mirror
!= inf_state
->dr_control_mirror
)
437 i386_dr_low_set_control (new_state
);
439 *inf_state
= *new_state
;
442 /* Insert a watchpoint to watch a memory region which starts at
443 address ADDR and whose length is LEN bytes. Watch memory accesses
444 of the type TYPE. Return 0 on success, -1 on failure. */
447 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
448 enum target_hw_bp_type type
,
449 CORE_ADDR addr
, int len
)
452 /* Work on a local copy of the debug registers, and on success,
453 commit the change back to the inferior. */
454 struct i386_debug_reg_state local_state
= *state
;
457 return 1; /* unsupported */
459 if (((len
!= 1 && len
!= 2 && len
!= 4)
460 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
463 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
469 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
471 retval
= i386_insert_aligned_watchpoint (&local_state
,
476 i386_update_inferior_debug_regs (state
, &local_state
);
479 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
484 /* Remove a watchpoint that watched the memory region which starts at
485 address ADDR, whose length is LEN bytes, and for accesses of the
486 type TYPE. Return 0 on success, -1 on failure. */
489 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
490 enum target_hw_bp_type type
,
491 CORE_ADDR addr
, int len
)
494 /* Work on a local copy of the debug registers, and on success,
495 commit the change back to the inferior. */
496 struct i386_debug_reg_state local_state
= *state
;
498 if (((len
!= 1 && len
!= 2 && len
!= 4)
499 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
502 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
508 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
510 retval
= i386_remove_aligned_watchpoint (&local_state
,
515 i386_update_inferior_debug_regs (state
, &local_state
);
518 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
523 /* Return non-zero if we can watch a memory region that starts at
524 address ADDR and whose length is LEN bytes. */
527 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
528 CORE_ADDR addr
, int len
)
532 /* Compute how many aligned watchpoints we would need to cover this
534 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
535 addr
, len
, hw_write
);
536 return nregs
<= DR_NADDR
? 1 : 0;
539 /* If the inferior has some break/watchpoint that triggered, set the
540 address associated with that break/watchpoint and return non-zero.
541 Otherwise, return zero. */
544 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
550 /* The current thread's DR_STATUS. We always need to read this to
551 check whether some watchpoint caused the trap. */
553 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
554 data breakpoint trap. Only fetch it when necessary, to avoid an
555 unnecessary extra syscall when no watchpoint triggered. */
557 unsigned control
= 0;
559 /* In non-stop/async, threads can be running while we change the
560 global dr_mirror (and friends). Say, we set a watchpoint, and
561 let threads resume. Now, say you delete the watchpoint, or
562 add/remove watchpoints such that dr_mirror changes while threads
563 are running. On targets that support non-stop,
564 inserting/deleting watchpoints updates the global dr_mirror only.
565 It does not update the real thread's debug registers; that's only
566 done prior to resume. Instead, if threads are running when the
567 mirror changes, a temporary and transparent stop on all threads
568 is forced so they can get their copy of the debug registers
569 updated on re-resume. Now, say, a thread hit a watchpoint before
570 having been updated with the new dr_mirror contents, and we
571 haven't yet handled the corresponding SIGTRAP. If we trusted
572 dr_mirror below, we'd mistake the real trapped address (from the
573 last time we had updated debug registers in the thread) with
574 whatever was currently in dr_mirror. So to fix this, dr_mirror
575 always represents intention, what we _want_ threads to have in
576 debug registers. To get at the address and cause of the trap, we
577 need to read the state the thread still has in its debug
580 In sum, always get the current debug register values the current
581 thread has, instead of trusting the global mirror. If the thread
582 was running when we last changed watchpoints, the mirror no
583 longer represents what was set in this thread's debug
585 status
= i386_dr_low_get_status ();
587 ALL_DEBUG_REGISTERS (i
)
589 if (!I386_DR_WATCH_HIT (status
, i
))
594 control
= i386_dr_low_get_control ();
598 /* This second condition makes sure DRi is set up for a data
599 watchpoint, not a hardware breakpoint. The reason is that
600 GDB doesn't call the target_stopped_data_address method
601 except for data watchpoints. In other words, I'm being
603 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
605 addr
= i386_dr_low_get_addr (i
);
608 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
612 if (debug_hw_points
&& addr
== 0)
613 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
620 /* Return non-zero if the inferior has some watchpoint that triggered.
621 Otherwise return zero. */
624 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
627 return i386_low_stopped_data_address (state
, &addr
);