1 /* Debug register code for the i386.
3 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* Support for 8-byte wide hw watchpoints. */
25 #ifndef TARGET_HAS_DR_LEN_8
26 /* NOTE: sizeof (long) == 4 on win64. */
27 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
30 /* DR7 Debug Control register fields. */
32 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
33 #define DR_CONTROL_SHIFT 16
34 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
35 #define DR_CONTROL_SIZE 4
37 /* Watchpoint/breakpoint read/write fields in DR7. */
38 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
39 #define DR_RW_WRITE (0x1) /* Break on data writes. */
40 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
42 /* This is here for completeness. No platform supports this
43 functionality yet (as of March 2001). Note that the DE flag in the
44 CR4 register needs to be set to support this. */
46 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
49 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
50 is so we could OR this with the read/write field defined above. */
51 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
52 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
53 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
54 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
56 /* Local and Global Enable flags in DR7.
58 When the Local Enable flag is set, the breakpoint/watchpoint is
59 enabled only for the current task; the processor automatically
60 clears this flag on every task switch. When the Global Enable flag
61 is set, the breakpoint/watchpoint is enabled for all tasks; the
62 processor never clears this flag.
64 Currently, all watchpoint are locally enabled. If you need to
65 enable them globally, read the comment which pertains to this in
66 i386_insert_aligned_watchpoint below. */
67 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
68 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
69 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
71 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
72 flags). These are only required on i386, to allow detection of the
73 exact instruction which caused a watchpoint to break; i486 and
74 later processors do that automatically. We set these flags for
75 backwards compatibility. */
76 #define DR_LOCAL_SLOWDOWN (0x100)
77 #define DR_GLOBAL_SLOWDOWN (0x200)
79 /* Fields reserved by Intel. This includes the GD (General Detect
80 Enable) flag, which causes a debug exception to be generated when a
81 MOV instruction accesses one of the debug registers.
83 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
84 #define DR_CONTROL_RESERVED (0xFC00)
86 /* Auxiliary helper macros. */
88 /* A value that masks all fields in DR7 that are reserved by Intel. */
89 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
91 /* The I'th debug register is vacant if its Local and Global Enable
92 bits are reset in the Debug Control register. */
93 #define I386_DR_VACANT(state, i) \
94 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
96 /* Locally enable the break/watchpoint in the I'th debug register. */
97 #define I386_DR_LOCAL_ENABLE(state, i) \
99 (state)->dr_control_mirror |= \
100 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
103 /* Globally enable the break/watchpoint in the I'th debug register. */
104 #define I386_DR_GLOBAL_ENABLE(state, i) \
106 (state)->dr_control_mirror |= \
107 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
110 /* Disable the break/watchpoint in the I'th debug register. */
111 #define I386_DR_DISABLE(state, i) \
113 (state)->dr_control_mirror &= \
114 ~(3 << (DR_ENABLE_SIZE * (i))); \
117 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
118 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
120 (state)->dr_control_mirror &= \
121 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
122 (state)->dr_control_mirror |= \
123 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
126 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
127 #define I386_DR_GET_RW_LEN(dr7, i) \
129 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
131 /* Did the watchpoint whose address is in the I'th register break? */
132 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
134 /* A macro to loop over all debug registers. */
135 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
137 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
138 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
140 /* Implementation. */
142 /* Clear the reference counts and forget everything we knew about the
146 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
150 ALL_DEBUG_REGISTERS (i
)
152 state
->dr_mirror
[i
] = 0;
153 state
->dr_ref_count
[i
] = 0;
155 state
->dr_control_mirror
= 0;
156 state
->dr_status_mirror
= 0;
159 /* Print the values of the mirrored debug registers. This is enabled via
160 the "set debug-hw-points 1" monitor command. */
163 i386_show_dr (struct i386_debug_reg_state
*state
,
164 const char *func
, CORE_ADDR addr
,
165 int len
, enum target_hw_bp_type type
)
169 fprintf (stderr
, "%s", func
);
171 fprintf (stderr
, " (addr=%lx, len=%d, type=%s)",
172 (unsigned long) addr
, len
,
173 type
== hw_write
? "data-write"
174 : (type
== hw_read
? "data-read"
175 : (type
== hw_access
? "data-read/write"
176 : (type
== hw_execute
? "instruction-execute"
177 /* FIXME: if/when I/O read/write
178 watchpoints are supported, add them
181 fprintf (stderr
, ":\n");
182 fprintf (stderr
, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
183 state
->dr_control_mirror
, state
->dr_status_mirror
);
184 ALL_DEBUG_REGISTERS (i
)
187 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
188 i
, paddress (state
->dr_mirror
[i
]),
189 state
->dr_ref_count
[i
],
190 i
+ 1, paddress (state
->dr_mirror
[i
+ 1]),
191 state
->dr_ref_count
[i
+ 1]);
196 /* Return the value of a 4-bit field for DR7 suitable for watching a
197 region of LEN bytes for accesses of type TYPE. LEN is assumed to
198 have the value of 1, 2, or 4. */
201 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
214 fatal ("The i386 doesn't support data-read watchpoints.\n");
219 /* Not yet supported. */
226 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
233 return (DR_LEN_1
| rw
);
235 return (DR_LEN_2
| rw
);
237 return (DR_LEN_4
| rw
);
239 if (TARGET_HAS_DR_LEN_8
)
240 return (DR_LEN_8
| rw
);
241 /* ELSE FALL THROUGH */
244 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
248 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
249 according to the length of the region to watch. LEN_RW_BITS is the
250 value of the bits from DR7 which describes the length and access
251 type of the region to be watched by this watchpoint. Return 0 on
252 success, -1 on failure. */
255 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
256 CORE_ADDR addr
, unsigned len_rw_bits
)
260 /* First, look for an occupied debug register with the same address
261 and the same RW and LEN definitions. If we find one, we can
262 reuse it for this watchpoint as well (and save a register). */
263 ALL_DEBUG_REGISTERS (i
)
265 if (!I386_DR_VACANT (state
, i
)
266 && state
->dr_mirror
[i
] == addr
267 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
269 state
->dr_ref_count
[i
]++;
274 /* Next, look for a vacant debug register. */
275 ALL_DEBUG_REGISTERS (i
)
277 if (I386_DR_VACANT (state
, i
))
281 /* No more debug registers! */
285 /* Now set up the register I to watch our region. */
287 /* Record the info in our local mirrored array. */
288 state
->dr_mirror
[i
] = addr
;
289 state
->dr_ref_count
[i
] = 1;
290 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
291 /* Note: we only enable the watchpoint locally, i.e. in the current
292 task. Currently, no i386 target allows or supports global
293 watchpoints; however, if any target would want that in the
294 future, GDB should probably provide a command to control whether
295 to enable watchpoints globally or locally, and the code below
296 should use global or local enable and slow-down flags as
298 I386_DR_LOCAL_ENABLE (state
, i
);
299 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
300 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
305 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
306 according to the length of the region to watch. LEN_RW_BITS is the
307 value of the bits from DR7 which describes the length and access
308 type of the region watched by this watchpoint. Return 0 on
309 success, -1 on failure. */
312 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
313 CORE_ADDR addr
, unsigned len_rw_bits
)
317 ALL_DEBUG_REGISTERS (i
)
319 if (!I386_DR_VACANT (state
, i
)
320 && state
->dr_mirror
[i
] == addr
321 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
323 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
325 /* Reset our mirror. */
326 state
->dr_mirror
[i
] = 0;
327 I386_DR_DISABLE (state
, i
);
336 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
337 number of debug registers required to watch a region at address
338 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
339 successful insertion or removal, a positive number when queried
340 about the number of registers, or -1 on failure. If WHAT is not a
341 valid value, bombs through internal_error. */
344 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
345 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
346 enum target_hw_bp_type type
)
349 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
351 static const int size_try_array
[8][8] =
353 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
354 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
355 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
356 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
357 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
358 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
359 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
360 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
365 int align
= addr
% max_wp_len
;
366 /* Four (eight on AMD64) is the maximum length a debug register
368 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
369 int size
= size_try_array
[try][align
];
371 if (what
== WP_COUNT
)
373 /* size_try_array[] is defined such that each iteration
374 through the loop is guaranteed to produce an address and a
375 size that can be watched with a single debug register.
376 Thus, for counting the registers required to watch a
377 region, we simply need to increment the count on each
383 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
385 if (what
== WP_INSERT
)
386 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
387 else if (what
== WP_REMOVE
)
388 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
391 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
405 /* Update the inferior debug registers state, in INF_STATE, with the
406 new debug registers state, in NEW_STATE. */
409 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*inf_state
,
410 struct i386_debug_reg_state
*new_state
)
414 ALL_DEBUG_REGISTERS (i
)
416 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (inf_state
, i
))
417 i386_dr_low_set_addr (new_state
, i
);
419 gdb_assert (new_state
->dr_mirror
[i
] == inf_state
->dr_mirror
[i
]);
422 if (new_state
->dr_control_mirror
!= inf_state
->dr_control_mirror
)
423 i386_dr_low_set_control (new_state
);
425 *inf_state
= *new_state
;
428 /* Insert a watchpoint to watch a memory region which starts at
429 address ADDR and whose length is LEN bytes. Watch memory accesses
430 of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
433 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
434 enum target_hw_bp_type type
,
435 CORE_ADDR addr
, int len
)
438 /* Work on a local copy of the debug registers, and on success,
439 commit the change back to the inferior. */
440 struct i386_debug_reg_state local_state
= *state
;
443 return 1; /* unsupported */
445 if (((len
!= 1 && len
!= 2 && len
!= 4)
446 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
449 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_INSERT
,
454 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
456 retval
= i386_insert_aligned_watchpoint (&local_state
, addr
, len_rw
);
460 i386_update_inferior_debug_regs (state
, &local_state
);
463 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
468 /* Remove a watchpoint that watched the memory region which starts at
469 address ADDR, whose length is LEN bytes, and for accesses of the
470 type TYPE. Return 0 on success, -1 on failure. */
473 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
474 enum target_hw_bp_type type
,
475 CORE_ADDR addr
, int len
)
478 /* Work on a local copy of the debug registers, and on success,
479 commit the change back to the inferior. */
480 struct i386_debug_reg_state local_state
= *state
;
482 if (((len
!= 1 && len
!= 2 && len
!= 4)
483 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
486 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_REMOVE
,
491 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
493 retval
= i386_remove_aligned_watchpoint (&local_state
, addr
, len_rw
);
497 i386_update_inferior_debug_regs (state
, &local_state
);
500 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
505 /* Return non-zero if we can watch a memory region that starts at
506 address ADDR and whose length is LEN bytes. */
509 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
510 CORE_ADDR addr
, int len
)
514 /* Compute how many aligned watchpoints we would need to cover this
516 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
517 addr
, len
, hw_write
);
518 return nregs
<= DR_NADDR
? 1 : 0;
521 /* If the inferior has some break/watchpoint that triggered, set the
522 address associated with that break/watchpoint and return true.
523 Otherwise, return false. */
526 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
532 /* The current thread's DR_STATUS. We always need to read this to
533 check whether some watchpoint caused the trap. */
535 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
536 data breakpoint trap. Only fetch it when necessary, to avoid an
537 unnecessary extra syscall when no watchpoint triggered. */
539 unsigned control
= 0;
541 /* In non-stop/async, threads can be running while we change the
542 global dr_mirror (and friends). Say, we set a watchpoint, and
543 let threads resume. Now, say you delete the watchpoint, or
544 add/remove watchpoints such that dr_mirror changes while threads
545 are running. On targets that support non-stop,
546 inserting/deleting watchpoints updates the global dr_mirror only.
547 It does not update the real thread's debug registers; that's only
548 done prior to resume. Instead, if threads are running when the
549 mirror changes, a temporary and transparent stop on all threads
550 is forced so they can get their copy of the debug registers
551 updated on re-resume. Now, say, a thread hit a watchpoint before
552 having been updated with the new dr_mirror contents, and we
553 haven't yet handled the corresponding SIGTRAP. If we trusted
554 dr_mirror below, we'd mistake the real trapped address (from the
555 last time we had updated debug registers in the thread) with
556 whatever was currently in dr_mirror. So to fix this, dr_mirror
557 always represents intention, what we _want_ threads to have in
558 debug registers. To get at the address and cause of the trap, we
559 need to read the state the thread still has in its debug
562 In sum, always get the current debug register values the current
563 thread has, instead of trusting the global mirror. If the thread
564 was running when we last changed watchpoints, the mirror no
565 longer represents what was set in this thread's debug
567 status
= i386_dr_low_get_status ();
569 ALL_DEBUG_REGISTERS (i
)
571 if (!I386_DR_WATCH_HIT (status
, i
))
576 control
= i386_dr_low_get_control ();
580 /* This second condition makes sure DRi is set up for a data
581 watchpoint, not a hardware breakpoint. The reason is that
582 GDB doesn't call the target_stopped_data_address method
583 except for data watchpoints. In other words, I'm being
585 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
587 addr
= i386_dr_low_get_addr (i
);
590 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
594 if (debug_hw_points
&& addr
== 0)
595 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
602 /* Return true if the inferior has some watchpoint that triggered.
603 Otherwise return false. */
606 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
609 return i386_low_stopped_data_address (state
, &addr
);