1 /* Debug register code for the i386.
3 Copyright (C) 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* Support for 8-byte wide hw watchpoints. */
25 #ifndef TARGET_HAS_DR_LEN_8
26 /* NOTE: sizeof (long) == 4 on win64. */
27 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
30 enum target_hw_bp_type
32 hw_write
= 0, /* Common HW watchpoint */
33 hw_read
= 1, /* Read HW watchpoint */
34 hw_access
= 2, /* Access HW watchpoint */
35 hw_execute
= 3 /* Execute HW breakpoint */
38 /* DR7 Debug Control register fields. */
40 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
41 #define DR_CONTROL_SHIFT 16
42 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
43 #define DR_CONTROL_SIZE 4
45 /* Watchpoint/breakpoint read/write fields in DR7. */
46 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
47 #define DR_RW_WRITE (0x1) /* Break on data writes. */
48 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
50 /* This is here for completeness. No platform supports this
51 functionality yet (as of March 2001). Note that the DE flag in the
52 CR4 register needs to be set to support this. */
54 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
57 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
58 is so we could OR this with the read/write field defined above. */
59 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
60 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
61 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
62 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
64 /* Local and Global Enable flags in DR7.
66 When the Local Enable flag is set, the breakpoint/watchpoint is
67 enabled only for the current task; the processor automatically
68 clears this flag on every task switch. When the Global Enable flag
69 is set, the breakpoint/watchpoint is enabled for all tasks; the
70 processor never clears this flag.
72 Currently, all watchpoint are locally enabled. If you need to
73 enable them globally, read the comment which pertains to this in
74 i386_insert_aligned_watchpoint below. */
75 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
76 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
77 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
79 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
80 flags). These are only required on i386, to allow detection of the
81 exact instruction which caused a watchpoint to break; i486 and
82 later processors do that automatically. We set these flags for
83 backwards compatibility. */
84 #define DR_LOCAL_SLOWDOWN (0x100)
85 #define DR_GLOBAL_SLOWDOWN (0x200)
87 /* Fields reserved by Intel. This includes the GD (General Detect
88 Enable) flag, which causes a debug exception to be generated when a
89 MOV instruction accesses one of the debug registers.
91 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
92 #define DR_CONTROL_RESERVED (0xFC00)
94 /* Auxiliary helper macros. */
96 /* A value that masks all fields in DR7 that are reserved by Intel. */
97 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
99 /* The I'th debug register is vacant if its Local and Global Enable
100 bits are reset in the Debug Control register. */
101 #define I386_DR_VACANT(state, i) \
102 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
104 /* Locally enable the break/watchpoint in the I'th debug register. */
105 #define I386_DR_LOCAL_ENABLE(state, i) \
107 (state)->dr_control_mirror |= \
108 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
111 /* Globally enable the break/watchpoint in the I'th debug register. */
112 #define I386_DR_GLOBAL_ENABLE(state, i) \
114 (state)->dr_control_mirror |= \
115 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
118 /* Disable the break/watchpoint in the I'th debug register. */
119 #define I386_DR_DISABLE(state, i) \
121 (state)->dr_control_mirror &= \
122 ~(3 << (DR_ENABLE_SIZE * (i))); \
125 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
126 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
128 (state)->dr_control_mirror &= \
129 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
130 (state)->dr_control_mirror |= \
131 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
134 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
135 #define I386_DR_GET_RW_LEN(dr7, i) \
137 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
139 /* Did the watchpoint whose address is in the I'th register break? */
140 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
142 /* A macro to loop over all debug registers. */
143 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
145 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
146 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
148 /* Implementation. */
150 /* Clear the reference counts and forget everything we knew about the
154 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
158 ALL_DEBUG_REGISTERS (i
)
160 state
->dr_mirror
[i
] = 0;
161 state
->dr_ref_count
[i
] = 0;
163 state
->dr_control_mirror
= 0;
164 state
->dr_status_mirror
= 0;
167 /* Print the values of the mirrored debug registers. This is enabled via
168 the "set debug-hw-points 1" monitor command. */
171 i386_show_dr (struct i386_debug_reg_state
*state
,
172 const char *func
, CORE_ADDR addr
,
173 int len
, enum target_hw_bp_type type
)
177 fprintf (stderr
, "%s", func
);
179 fprintf (stderr
, " (addr=%lx, len=%d, type=%s)",
180 (unsigned long) addr
, len
,
181 type
== hw_write
? "data-write"
182 : (type
== hw_read
? "data-read"
183 : (type
== hw_access
? "data-read/write"
184 : (type
== hw_execute
? "instruction-execute"
185 /* FIXME: if/when I/O read/write
186 watchpoints are supported, add them
189 fprintf (stderr
, ":\n");
190 fprintf (stderr
, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
191 state
->dr_control_mirror
, state
->dr_status_mirror
);
192 ALL_DEBUG_REGISTERS (i
)
195 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
196 i
, paddress (state
->dr_mirror
[i
]),
197 state
->dr_ref_count
[i
],
198 i
+ 1, paddress (state
->dr_mirror
[i
+ 1]),
199 state
->dr_ref_count
[i
+ 1]);
204 /* Return the value of a 4-bit field for DR7 suitable for watching a
205 region of LEN bytes for accesses of type TYPE. LEN is assumed to
206 have the value of 1, 2, or 4. */
209 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
222 fatal ("The i386 doesn't support data-read watchpoints.\n");
227 /* Not yet supported. */
234 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
241 return (DR_LEN_1
| rw
);
243 return (DR_LEN_2
| rw
);
245 return (DR_LEN_4
| rw
);
247 if (TARGET_HAS_DR_LEN_8
)
248 return (DR_LEN_8
| rw
);
251 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
255 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
256 according to the length of the region to watch. LEN_RW_BITS is the
257 value of the bits from DR7 which describes the length and access
258 type of the region to be watched by this watchpoint. Return 0 on
259 success, -1 on failure. */
262 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
263 CORE_ADDR addr
, unsigned len_rw_bits
)
267 /* First, look for an occupied debug register with the same address
268 and the same RW and LEN definitions. If we find one, we can
269 reuse it for this watchpoint as well (and save a register). */
270 ALL_DEBUG_REGISTERS (i
)
272 if (!I386_DR_VACANT (state
, i
)
273 && state
->dr_mirror
[i
] == addr
274 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
276 state
->dr_ref_count
[i
]++;
281 /* Next, look for a vacant debug register. */
282 ALL_DEBUG_REGISTERS (i
)
284 if (I386_DR_VACANT (state
, i
))
288 /* No more debug registers! */
292 /* Now set up the register I to watch our region. */
294 /* Record the info in our local mirrored array. */
295 state
->dr_mirror
[i
] = addr
;
296 state
->dr_ref_count
[i
] = 1;
297 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
298 /* Note: we only enable the watchpoint locally, i.e. in the current
299 task. Currently, no i386 target allows or supports global
300 watchpoints; however, if any target would want that in the
301 future, GDB should probably provide a command to control whether
302 to enable watchpoints globally or locally, and the code below
303 should use global or local enable and slow-down flags as
305 I386_DR_LOCAL_ENABLE (state
, i
);
306 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
307 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
309 /* Finally, actually pass the info to the inferior. */
310 i386_dr_low_set_addr (state
, i
);
311 i386_dr_low_set_control (state
);
316 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
317 according to the length of the region to watch. LEN_RW_BITS is the
318 value of the bits from DR7 which describes the length and access
319 type of the region watched by this watchpoint. Return 0 on
320 success, -1 on failure. */
323 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
324 CORE_ADDR addr
, unsigned len_rw_bits
)
328 ALL_DEBUG_REGISTERS (i
)
330 if (!I386_DR_VACANT (state
, i
)
331 && state
->dr_mirror
[i
] == addr
332 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
334 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
336 /* Reset our mirror. */
337 state
->dr_mirror
[i
] = 0;
338 I386_DR_DISABLE (state
, i
);
339 /* Reset it in the inferior. */
340 i386_dr_low_set_control (state
);
341 i386_dr_low_set_addr (state
, i
);
350 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
351 number of debug registers required to watch a region at address
352 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
353 successful insertion or removal, a positive number when queried
354 about the number of registers, or -1 on failure. If WHAT is not a
355 valid value, bombs through internal_error. */
358 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
359 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
360 enum target_hw_bp_type type
)
362 int retval
= 0, status
= 0;
363 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
365 static const int size_try_array
[8][8] =
367 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
368 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
369 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
370 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
371 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
372 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
373 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
374 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
379 int align
= addr
% max_wp_len
;
380 /* Four (eight on AMD64) is the maximum length a debug register
382 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
383 int size
= size_try_array
[try][align
];
385 if (what
== WP_COUNT
)
387 /* size_try_array[] is defined such that each iteration
388 through the loop is guaranteed to produce an address and a
389 size that can be watched with a single debug register.
390 Thus, for counting the registers required to watch a
391 region, we simply need to increment the count on each
397 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
399 if (what
== WP_INSERT
)
400 status
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
401 else if (what
== WP_REMOVE
)
402 status
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
405 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
408 /* We keep the loop going even after a failure, because some
409 of the other aligned watchpoints might still succeed
410 (e.g. if they watch addresses that are already watched,
411 in which case we just increment the reference counts of
412 occupied debug registers). If we break out of the loop
413 too early, we could cause those addresses watched by
414 other watchpoints to be disabled when breakpoint.c reacts
415 to our failure to insert this watchpoint and tries to
428 #define Z_PACKET_WRITE_WP '2'
429 #define Z_PACKET_READ_WP '3'
430 #define Z_PACKET_ACCESS_WP '4'
432 /* Map the protocol watchpoint type TYPE to enum target_hw_bp_type. */
434 static enum target_hw_bp_type
435 Z_packet_to_hw_type (char type
)
439 case Z_PACKET_WRITE_WP
:
441 case Z_PACKET_READ_WP
:
443 case Z_PACKET_ACCESS_WP
:
446 fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type
);
450 /* Insert a watchpoint to watch a memory region which starts at
451 address ADDR and whose length is LEN bytes. Watch memory accesses
452 of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
455 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
456 char type_from_packet
, CORE_ADDR addr
, int len
)
459 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
462 return 1; /* unsupported */
464 if (((len
!= 1 && len
!= 2 && len
!= 4)
465 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
468 retval
= i386_handle_nonaligned_watchpoint (state
, WP_INSERT
,
473 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
475 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
479 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
484 /* Remove a watchpoint that watched the memory region which starts at
485 address ADDR, whose length is LEN bytes, and for accesses of the
486 type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
489 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
490 char type_from_packet
, CORE_ADDR addr
, int len
)
493 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
495 if (((len
!= 1 && len
!= 2 && len
!= 4)
496 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
499 retval
= i386_handle_nonaligned_watchpoint (state
, WP_REMOVE
,
504 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
506 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
510 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
515 /* Return non-zero if we can watch a memory region that starts at
516 address ADDR and whose length is LEN bytes. */
519 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
520 CORE_ADDR addr
, int len
)
524 /* Compute how many aligned watchpoints we would need to cover this
526 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
527 addr
, len
, hw_write
);
528 return nregs
<= DR_NADDR
? 1 : 0;
531 /* If the inferior has some break/watchpoint that triggered, set the
532 address associated with that break/watchpoint and return true.
533 Otherwise, return false. */
536 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
545 /* Get the current values the inferior has. If the thread was
546 running when we last changed watchpoints, the mirror no longer
547 represents what was set in this LWP's debug registers. */
548 status
= i386_dr_low_get_status ();
549 control
= i386_dr_low_get_control ();
551 ALL_DEBUG_REGISTERS (i
)
553 if (I386_DR_WATCH_HIT (status
, i
)
554 /* This second condition makes sure DRi is set up for a data
555 watchpoint, not a hardware breakpoint. The reason is
556 that GDB doesn't call the target_stopped_data_address
557 method except for data watchpoints. In other words, I'm
559 && I386_DR_GET_RW_LEN (control
, i
) != 0)
561 addr
= i386_dr_low_get_addr (i
);
564 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
568 if (debug_hw_points
&& addr
== 0)
569 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
576 /* Return true if the inferior has some watchpoint that triggered.
577 Otherwise return false. */
580 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
583 return i386_low_stopped_data_address (state
, &addr
);
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