1 /* Debug register code for the i386.
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 /* Support for 8-byte wide hw watchpoints. */
26 #ifndef TARGET_HAS_DR_LEN_8
27 /* NOTE: sizeof (long) == 4 on win64. */
28 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
31 enum target_hw_bp_type
33 hw_write
= 0, /* Common HW watchpoint */
34 hw_read
= 1, /* Read HW watchpoint */
35 hw_access
= 2, /* Access HW watchpoint */
36 hw_execute
= 3 /* Execute HW breakpoint */
39 /* DR7 Debug Control register fields. */
41 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
42 #define DR_CONTROL_SHIFT 16
43 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
44 #define DR_CONTROL_SIZE 4
46 /* Watchpoint/breakpoint read/write fields in DR7. */
47 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
48 #define DR_RW_WRITE (0x1) /* Break on data writes. */
49 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
51 /* This is here for completeness. No platform supports this
52 functionality yet (as of March 2001). Note that the DE flag in the
53 CR4 register needs to be set to support this. */
55 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
58 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
59 is so we could OR this with the read/write field defined above. */
60 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
61 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
62 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
63 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
65 /* Local and Global Enable flags in DR7.
67 When the Local Enable flag is set, the breakpoint/watchpoint is
68 enabled only for the current task; the processor automatically
69 clears this flag on every task switch. When the Global Enable flag
70 is set, the breakpoint/watchpoint is enabled for all tasks; the
71 processor never clears this flag.
73 Currently, all watchpoint are locally enabled. If you need to
74 enable them globally, read the comment which pertains to this in
75 i386_insert_aligned_watchpoint below. */
76 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
77 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
78 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
80 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
81 flags). These are only required on i386, to allow detection of the
82 exact instruction which caused a watchpoint to break; i486 and
83 later processors do that automatically. We set these flags for
84 backwards compatibility. */
85 #define DR_LOCAL_SLOWDOWN (0x100)
86 #define DR_GLOBAL_SLOWDOWN (0x200)
88 /* Fields reserved by Intel. This includes the GD (General Detect
89 Enable) flag, which causes a debug exception to be generated when a
90 MOV instruction accesses one of the debug registers.
92 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
93 #define DR_CONTROL_RESERVED (0xFC00)
95 /* Auxiliary helper macros. */
97 /* A value that masks all fields in DR7 that are reserved by Intel. */
98 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
100 /* The I'th debug register is vacant if its Local and Global Enable
101 bits are reset in the Debug Control register. */
102 #define I386_DR_VACANT(state, i) \
103 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
105 /* Locally enable the break/watchpoint in the I'th debug register. */
106 #define I386_DR_LOCAL_ENABLE(state, i) \
108 (state)->dr_control_mirror |= \
109 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
112 /* Globally enable the break/watchpoint in the I'th debug register. */
113 #define I386_DR_GLOBAL_ENABLE(state, i) \
115 (state)->dr_control_mirror |= \
116 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
119 /* Disable the break/watchpoint in the I'th debug register. */
120 #define I386_DR_DISABLE(state, i) \
122 (state)->dr_control_mirror &= \
123 ~(3 << (DR_ENABLE_SIZE * (i))); \
126 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
127 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
129 (state)->dr_control_mirror &= \
130 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
131 (state)->dr_control_mirror |= \
132 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
135 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
136 #define I386_DR_GET_RW_LEN(state, i) \
137 (((state)->dr_control_mirror \
138 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
140 /* Did the watchpoint whose address is in the I'th register break? */
141 #define I386_DR_WATCH_HIT(state,i) ((state)->dr_status_mirror & (1 << (i)))
143 /* A macro to loop over all debug registers. */
144 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
146 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
147 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
149 /* Implementation. */
151 /* Clear the reference counts and forget everything we knew about the
155 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
159 ALL_DEBUG_REGISTERS (i
)
161 state
->dr_mirror
[i
] = 0;
162 state
->dr_ref_count
[i
] = 0;
164 state
->dr_control_mirror
= 0;
165 state
->dr_status_mirror
= 0;
168 /* Print the values of the mirrored debug registers. This is enabled via
169 the "set debug-hw-points 1" monitor command. */
172 i386_show_dr (struct i386_debug_reg_state
*state
,
173 const char *func
, CORE_ADDR addr
,
174 int len
, enum target_hw_bp_type type
)
178 fprintf (stderr
, "%s", func
);
180 fprintf (stderr
, " (addr=%lx, len=%d, type=%s)",
181 (unsigned long) addr
, len
,
182 type
== hw_write
? "data-write"
183 : (type
== hw_read
? "data-read"
184 : (type
== hw_access
? "data-read/write"
185 : (type
== hw_execute
? "instruction-execute"
186 /* FIXME: if/when I/O read/write
187 watchpoints are supported, add them
190 fprintf (stderr
, ":\n");
191 fprintf (stderr
, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
192 state
->dr_control_mirror
, state
->dr_status_mirror
);
193 ALL_DEBUG_REGISTERS (i
)
196 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
197 i
, paddress (state
->dr_mirror
[i
]),
198 state
->dr_ref_count
[i
],
199 i
+ 1, paddress (state
->dr_mirror
[i
+ 1]),
200 state
->dr_ref_count
[i
+ 1]);
205 /* Return the value of a 4-bit field for DR7 suitable for watching a
206 region of LEN bytes for accesses of type TYPE. LEN is assumed to
207 have the value of 1, 2, or 4. */
210 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
223 /* The i386 doesn't support data-read watchpoints. */
228 /* Not yet supported. */
235 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
242 return (DR_LEN_1
| rw
);
244 return (DR_LEN_2
| rw
);
246 return (DR_LEN_4
| rw
);
248 if (TARGET_HAS_DR_LEN_8
)
249 return (DR_LEN_8
| rw
);
252 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
256 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
257 according to the length of the region to watch. LEN_RW_BITS is the
258 value of the bits from DR7 which describes the length and access
259 type of the region to be watched by this watchpoint. Return 0 on
260 success, -1 on failure. */
263 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
264 CORE_ADDR addr
, unsigned len_rw_bits
)
268 /* First, look for an occupied debug register with the same address
269 and the same RW and LEN definitions. If we find one, we can
270 reuse it for this watchpoint as well (and save a register). */
271 ALL_DEBUG_REGISTERS (i
)
273 if (!I386_DR_VACANT (state
, i
)
274 && state
->dr_mirror
[i
] == addr
275 && I386_DR_GET_RW_LEN (state
, i
) == len_rw_bits
)
277 state
->dr_ref_count
[i
]++;
282 /* Next, look for a vacant debug register. */
283 ALL_DEBUG_REGISTERS (i
)
285 if (I386_DR_VACANT (state
, i
))
289 /* No more debug registers! */
293 /* Now set up the register I to watch our region. */
295 /* Record the info in our local mirrored array. */
296 state
->dr_mirror
[i
] = addr
;
297 state
->dr_ref_count
[i
] = 1;
298 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
299 /* Note: we only enable the watchpoint locally, i.e. in the current
300 task. Currently, no i386 target allows or supports global
301 watchpoints; however, if any target would want that in the
302 future, GDB should probably provide a command to control whether
303 to enable watchpoints globally or locally, and the code below
304 should use global or local enable and slow-down flags as
306 I386_DR_LOCAL_ENABLE (state
, i
);
307 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
308 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
310 /* Finally, actually pass the info to the inferior. */
311 i386_dr_low_set_addr (state
, i
);
312 i386_dr_low_set_control (state
);
317 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
318 according to the length of the region to watch. LEN_RW_BITS is the
319 value of the bits from DR7 which describes the length and access
320 type of the region watched by this watchpoint. Return 0 on
321 success, -1 on failure. */
324 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
325 CORE_ADDR addr
, unsigned len_rw_bits
)
329 ALL_DEBUG_REGISTERS (i
)
331 if (!I386_DR_VACANT (state
, i
)
332 && state
->dr_mirror
[i
] == addr
333 && I386_DR_GET_RW_LEN (state
, i
) == len_rw_bits
)
335 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
337 /* Reset our mirror. */
338 state
->dr_mirror
[i
] = 0;
339 I386_DR_DISABLE (state
, i
);
340 /* Reset it in the inferior. */
341 i386_dr_low_set_control (state
);
342 i386_dr_low_set_addr (state
, i
);
351 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
352 number of debug registers required to watch a region at address
353 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
354 successful insertion or removal, a positive number when queried
355 about the number of registers, or -1 on failure. If WHAT is not a
356 valid value, bombs through internal_error. */
359 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
360 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
361 enum target_hw_bp_type type
)
363 int retval
= 0, status
= 0;
364 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
366 static const int size_try_array
[8][8] =
368 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
369 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
370 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
371 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
372 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
373 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
374 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
375 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
380 int align
= addr
% max_wp_len
;
381 /* Four (eight on AMD64) is the maximum length a debug register
383 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
384 int size
= size_try_array
[try][align
];
386 if (what
== WP_COUNT
)
388 /* size_try_array[] is defined such that each iteration
389 through the loop is guaranteed to produce an address and a
390 size that can be watched with a single debug register.
391 Thus, for counting the registers required to watch a
392 region, we simply need to increment the count on each
398 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
400 if (what
== WP_INSERT
)
401 status
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
402 else if (what
== WP_REMOVE
)
403 status
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
406 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
409 /* We keep the loop going even after a failure, because some
410 of the other aligned watchpoints might still succeed
411 (e.g. if they watch addresses that are already watched,
412 in which case we just increment the reference counts of
413 occupied debug registers). If we break out of the loop
414 too early, we could cause those addresses watched by
415 other watchpoints to be disabled when breakpoint.c reacts
416 to our failure to insert this watchpoint and tries to
429 #define Z_PACKET_WRITE_WP '2'
430 #define Z_PACKET_READ_WP '3'
431 #define Z_PACKET_ACCESS_WP '4'
433 /* Map the protocol watchpoint type TYPE to enum target_hw_bp_type. */
435 static enum target_hw_bp_type
436 Z_packet_to_hw_type (char type
)
440 case Z_PACKET_WRITE_WP
:
442 case Z_PACKET_READ_WP
:
444 case Z_PACKET_ACCESS_WP
:
447 fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type
);
451 /* Insert a watchpoint to watch a memory region which starts at
452 address ADDR and whose length is LEN bytes. Watch memory accesses
453 of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
456 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
457 char type_from_packet
, CORE_ADDR addr
, int len
)
460 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
462 if (((len
!= 1 && len
!= 2 && len
!= 4)
463 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
466 retval
= i386_handle_nonaligned_watchpoint (state
, WP_INSERT
,
471 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
473 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
477 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
482 /* Remove a watchpoint that watched the memory region which starts at
483 address ADDR, whose length is LEN bytes, and for accesses of the
484 type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
487 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
488 char type_from_packet
, CORE_ADDR addr
, int len
)
491 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
493 if (((len
!= 1 && len
!= 2 && len
!= 4)
494 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
497 retval
= i386_handle_nonaligned_watchpoint (state
, WP_REMOVE
,
502 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
504 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
508 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
513 /* Return non-zero if we can watch a memory region that starts at
514 address ADDR and whose length is LEN bytes. */
517 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
518 CORE_ADDR addr
, int len
)
522 /* Compute how many aligned watchpoints we would need to cover this
524 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
525 addr
, len
, hw_write
);
526 return nregs
<= DR_NADDR
? 1 : 0;
529 /* If the inferior has some break/watchpoint that triggered, set the
530 address associated with that break/watchpoint and return true.
531 Otherwise, return false. */
534 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
541 /* Get dr_status_mirror for use by I386_DR_WATCH_HIT. */
542 i386_dr_low_get_status (state
);
544 ALL_DEBUG_REGISTERS (i
)
546 if (I386_DR_WATCH_HIT (state
, i
)
547 /* This second condition makes sure DRi is set up for a data
548 watchpoint, not a hardware breakpoint. The reason is
549 that GDB doesn't call the target_stopped_data_address
550 method except for data watchpoints. In other words, I'm
552 && I386_DR_GET_RW_LEN (state
, i
) != 0)
554 addr
= state
->dr_mirror
[i
];
557 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
561 if (debug_hw_points
&& addr
== 0)
562 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
569 /* Return true if the inferior has some watchpoint that triggered.
570 Otherwise return false. */
573 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
576 return i386_low_stopped_data_address (state
, &addr
);
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