1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
42 /* Defined in auto-generated files. */
43 void init_registers_aarch64 (void);
44 extern const struct target_desc
*tdesc_aarch64
;
50 #define AARCH64_X_REGS_NUM 31
51 #define AARCH64_V_REGS_NUM 32
52 #define AARCH64_X0_REGNO 0
53 #define AARCH64_SP_REGNO 31
54 #define AARCH64_PC_REGNO 32
55 #define AARCH64_CPSR_REGNO 33
56 #define AARCH64_V0_REGNO 34
57 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
58 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
60 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
62 /* Per-process arch-specific data we want to keep. */
64 struct arch_process_info
66 /* Hardware breakpoint/watchpoint data.
67 The reason for them to be per-process rather than per-thread is
68 due to the lack of information in the gdbserver environment;
69 gdbserver is not told that whether a requested hardware
70 breakpoint/watchpoint is thread specific or not, so it has to set
71 each hw bp/wp for every thread in the current process. The
72 higher level bp/wp management in gdb will resume a thread if a hw
73 bp/wp trap is not expected for it. Since the hw bp/wp setting is
74 same for each thread, it is reasonable for the data to live here.
76 struct aarch64_debug_reg_state debug_reg_state
;
79 /* Return true if the size of register 0 is 8 byte. */
84 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
86 return register_size (regcache
->tdesc
, 0) == 8;
89 /* Implementation of linux_target_ops method "cannot_store_register". */
92 aarch64_cannot_store_register (int regno
)
94 return regno
>= AARCH64_NUM_REGS
;
97 /* Implementation of linux_target_ops method "cannot_fetch_register". */
100 aarch64_cannot_fetch_register (int regno
)
102 return regno
>= AARCH64_NUM_REGS
;
106 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
108 struct user_pt_regs
*regset
= buf
;
111 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
112 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
113 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
114 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
115 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
119 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
121 const struct user_pt_regs
*regset
= buf
;
124 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
125 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
126 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
127 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
128 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
132 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
134 struct user_fpsimd_state
*regset
= buf
;
137 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
138 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
139 collect_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
140 collect_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
144 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
146 const struct user_fpsimd_state
*regset
= buf
;
149 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
150 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
151 supply_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
152 supply_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
155 /* Enable miscellaneous debugging output. The name is historical - it
156 was originally used to debug LinuxThreads support. */
157 extern int debug_threads
;
159 /* Implementation of linux_target_ops method "get_pc". */
162 aarch64_get_pc (struct regcache
*regcache
)
164 if (register_size (regcache
->tdesc
, 0) == 8)
168 collect_register_by_name (regcache
, "pc", &pc
);
170 debug_printf ("stop pc is %08lx\n", pc
);
177 collect_register_by_name (regcache
, "pc", &pc
);
179 debug_printf ("stop pc is %04x\n", pc
);
184 /* Implementation of linux_target_ops method "set_pc". */
187 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
189 if (register_size (regcache
->tdesc
, 0) == 8)
191 unsigned long newpc
= pc
;
192 supply_register_by_name (regcache
, "pc", &newpc
);
196 unsigned int newpc
= pc
;
197 supply_register_by_name (regcache
, "pc", &newpc
);
201 #define aarch64_breakpoint_len 4
203 /* AArch64 BRK software debug mode instruction.
204 This instruction needs to match gdb/aarch64-tdep.c
205 (aarch64_default_breakpoint). */
206 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
208 /* Implementation of linux_target_ops method "breakpoint_at". */
211 aarch64_breakpoint_at (CORE_ADDR where
)
213 gdb_byte insn
[aarch64_breakpoint_len
];
215 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
216 aarch64_breakpoint_len
);
217 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
224 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
228 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
230 state
->dr_addr_bp
[i
] = 0;
231 state
->dr_ctrl_bp
[i
] = 0;
232 state
->dr_ref_count_bp
[i
] = 0;
235 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
237 state
->dr_addr_wp
[i
] = 0;
238 state
->dr_ctrl_wp
[i
] = 0;
239 state
->dr_ref_count_wp
[i
] = 0;
243 /* Return the pointer to the debug register state structure in the
244 current process' arch-specific data area. */
246 struct aarch64_debug_reg_state
*
247 aarch64_get_debug_reg_state (pid_t pid
)
249 struct process_info
*proc
= find_process_pid (pid
);
251 return &proc
->priv
->arch_private
->debug_reg_state
;
254 /* Implementation of linux_target_ops method "supports_z_point_type". */
257 aarch64_supports_z_point_type (char z_type
)
263 if (!extended_protocol
&& is_64bit_tdesc ())
265 /* Only enable Z0 packet in non-multi-arch debugging. If
266 extended protocol is used, don't enable Z0 packet because
267 GDBserver may attach to 32-bit process. */
272 /* Disable Z0 packet so that GDBserver doesn't have to handle
273 different breakpoint instructions (aarch64, arm, thumb etc)
274 in multi-arch debugging. */
279 case Z_PACKET_WRITE_WP
:
280 case Z_PACKET_READ_WP
:
281 case Z_PACKET_ACCESS_WP
:
288 /* Implementation of linux_target_ops method "insert_point".
290 It actually only records the info of the to-be-inserted bp/wp;
291 the actual insertion will happen when threads are resumed. */
294 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
295 int len
, struct raw_breakpoint
*bp
)
298 enum target_hw_bp_type targ_type
;
299 struct aarch64_debug_reg_state
*state
300 = aarch64_get_debug_reg_state (pid_of (current_thread
));
303 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
304 (unsigned long) addr
, len
);
306 /* Determine the type from the raw breakpoint type. */
307 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
309 if (targ_type
!= hw_execute
)
311 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
312 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
313 1 /* is_insert */, state
);
319 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */,
323 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
329 /* Implementation of linux_target_ops method "remove_point".
331 It actually only records the info of the to-be-removed bp/wp,
332 the actual removal will be done when threads are resumed. */
335 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
336 int len
, struct raw_breakpoint
*bp
)
339 enum target_hw_bp_type targ_type
;
340 struct aarch64_debug_reg_state
*state
341 = aarch64_get_debug_reg_state (pid_of (current_thread
));
344 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
345 (unsigned long) addr
, len
);
347 /* Determine the type from the raw breakpoint type. */
348 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
350 /* Set up state pointers. */
351 if (targ_type
!= hw_execute
)
353 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
357 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */,
361 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
367 /* Implementation of linux_target_ops method "stopped_data_address". */
370 aarch64_stopped_data_address (void)
374 struct aarch64_debug_reg_state
*state
;
376 pid
= lwpid_of (current_thread
);
378 /* Get the siginfo. */
379 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
380 return (CORE_ADDR
) 0;
382 /* Need to be a hardware breakpoint/watchpoint trap. */
383 if (siginfo
.si_signo
!= SIGTRAP
384 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
385 return (CORE_ADDR
) 0;
387 /* Check if the address matches any watched address. */
388 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
389 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
391 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
392 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
393 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
394 if (state
->dr_ref_count_wp
[i
]
395 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
396 && addr_trap
>= addr_watch
397 && addr_trap
< addr_watch
+ len
)
401 return (CORE_ADDR
) 0;
404 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
407 aarch64_stopped_by_watchpoint (void)
409 if (aarch64_stopped_data_address () != 0)
415 /* Fetch the thread-local storage pointer for libthread_db. */
418 ps_get_thread_area (const struct ps_prochandle
*ph
,
419 lwpid_t lwpid
, int idx
, void **base
)
421 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
425 /* Implementation of linux_target_ops method "siginfo_fixup". */
428 aarch64_linux_siginfo_fixup (siginfo_t
*native
, void *inf
, int direction
)
430 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
431 if (!is_64bit_tdesc ())
434 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
437 aarch64_siginfo_from_compat_siginfo (native
,
438 (struct compat_siginfo
*) inf
);
446 /* Implementation of linux_target_ops method "linux_new_process". */
448 static struct arch_process_info
*
449 aarch64_linux_new_process (void)
451 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
453 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
458 /* Implementation of linux_target_ops method "linux_new_fork". */
461 aarch64_linux_new_fork (struct process_info
*parent
,
462 struct process_info
*child
)
464 /* These are allocated by linux_add_process. */
465 gdb_assert (parent
->priv
!= NULL
466 && parent
->priv
->arch_private
!= NULL
);
467 gdb_assert (child
->priv
!= NULL
468 && child
->priv
->arch_private
!= NULL
);
470 /* Linux kernel before 2.6.33 commit
471 72f674d203cd230426437cdcf7dd6f681dad8b0d
472 will inherit hardware debug registers from parent
473 on fork/vfork/clone. Newer Linux kernels create such tasks with
474 zeroed debug registers.
476 GDB core assumes the child inherits the watchpoints/hw
477 breakpoints of the parent, and will remove them all from the
478 forked off process. Copy the debug registers mirrors into the
479 new process so that all breakpoints and watchpoints can be
480 removed together. The debug registers mirror will become zeroed
481 in the end before detaching the forked off process, thus making
482 this compatible with older Linux kernels too. */
484 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
487 /* Return the right target description according to the ELF file of
490 static const struct target_desc
*
491 aarch64_linux_read_description (void)
493 unsigned int machine
;
497 tid
= lwpid_of (current_thread
);
499 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
502 return tdesc_aarch64
;
504 return tdesc_arm_with_neon
;
507 /* Implementation of linux_target_ops method "arch_setup". */
510 aarch64_arch_setup (void)
512 current_process ()->tdesc
= aarch64_linux_read_description ();
514 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
517 static struct regset_info aarch64_regsets
[] =
519 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
520 sizeof (struct user_pt_regs
), GENERAL_REGS
,
521 aarch64_fill_gregset
, aarch64_store_gregset
},
522 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
523 sizeof (struct user_fpsimd_state
), FP_REGS
,
524 aarch64_fill_fpregset
, aarch64_store_fpregset
526 { 0, 0, 0, -1, -1, NULL
, NULL
}
529 static struct regsets_info aarch64_regsets_info
=
531 aarch64_regsets
, /* regsets */
533 NULL
, /* disabled_regsets */
536 static struct regs_info regs_info_aarch64
=
538 NULL
, /* regset_bitmap */
540 &aarch64_regsets_info
,
543 /* Implementation of linux_target_ops method "regs_info". */
545 static const struct regs_info
*
546 aarch64_regs_info (void)
548 if (is_64bit_tdesc ())
549 return ®s_info_aarch64
;
551 return ®s_info_aarch32
;
554 /* Implementation of linux_target_ops method "supports_tracepoints". */
557 aarch64_supports_tracepoints (void)
559 if (current_thread
== NULL
)
563 /* We don't support tracepoints on aarch32 now. */
564 return is_64bit_tdesc ();
568 /* Implementation of linux_target_ops method "get_thread_area". */
571 aarch64_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
576 iovec
.iov_base
= ®
;
577 iovec
.iov_len
= sizeof (reg
);
579 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
587 /* Extract a signed value from a bit field within an instruction
590 INSN is the instruction opcode.
592 WIDTH specifies the width of the bit field to extract (in bits).
594 OFFSET specifies the least significant bit of the field where bits
595 are numbered zero counting from least to most significant. */
598 extract_signed_bitfield (uint32_t insn
, unsigned width
, unsigned offset
)
600 unsigned shift_l
= sizeof (int32_t) * 8 - (offset
+ width
);
601 unsigned shift_r
= sizeof (int32_t) * 8 - width
;
603 return ((int32_t) insn
<< shift_l
) >> shift_r
;
606 /* Decode an opcode if it represents an LDR or LDRSW instruction taking a
607 literal offset from the current PC.
609 ADDR specifies the address of the opcode.
610 INSN specifies the opcode to test.
611 IS_W is set if the instruction is LDRSW.
612 IS64 receives size field from the decoded instruction.
613 RT receives the 'rt' field from the decoded instruction.
614 OFFSET receives the 'imm' field from the decoded instruction.
616 Return 1 if the opcodes matches and is decoded, otherwise 0. */
619 aarch64_decode_ldr_literal (CORE_ADDR addr
, uint32_t insn
, int *is_w
,
620 int *is64
, unsigned *rt
, int32_t *offset
)
622 /* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
623 /* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
624 if ((insn
& 0x3f000000) == 0x18000000)
626 *is_w
= (insn
>> 31) & 0x1;
630 /* LDRSW always takes a 64-bit destination registers. */
634 *is64
= (insn
>> 30) & 0x1;
636 *rt
= (insn
>> 0) & 0x1f;
637 *offset
= extract_signed_bitfield (insn
, 19, 5) << 2;
640 debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
641 core_addr_to_string_nz (addr
), insn
,
642 *is_w
? "ldrsw" : "ldr",
643 *is64
? "x" : "w", *rt
);
651 /* List of opcodes that we need for building the jump pad and relocating
656 /* B 0001 01ii iiii iiii iiii iiii iiii iiii */
657 /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
658 /* B.COND 0101 0100 iiii iiii iiii iiii iii0 cccc */
659 /* CBZ s011 0100 iiii iiii iiii iiii iiir rrrr */
660 /* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
661 /* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
662 /* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
665 BCOND
= 0x40000000 | B
,
666 CBZ
= 0x20000000 | B
,
667 CBNZ
= 0x21000000 | B
,
668 TBZ
= 0x36000000 | B
,
669 TBNZ
= 0x37000000 | B
,
670 /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
672 /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
674 /* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
675 /* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
676 /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
677 /* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
680 STP_SIMD_VFP
= 0x04000000 | STP
,
681 LDP_SIMD_VFP
= 0x04000000 | LDP
,
682 /* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
683 /* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
684 /* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
686 LDR
= 0x00400000 | STR
,
687 LDRSW
= 0x80800000 | STR
,
688 /* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
690 /* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
692 /* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
694 /* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
695 /* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
697 MOVK
= 0x20000000 | MOV
,
698 /* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
699 /* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
700 /* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
702 SUB
= 0x40000000 | ADD
,
703 SUBS
= 0x20000000 | SUB
,
704 /* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
705 /* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
706 /* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
707 /* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
709 ORR
= 0x20000000 | AND
,
710 ORN
= 0x00200000 | ORR
,
711 EOR
= 0x40000000 | AND
,
712 /* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
713 /* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
714 /* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
716 LSRV
= 0x00000400 | LSLV
,
717 ASRV
= 0x00000800 | LSLV
,
718 /* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
720 /* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
721 UBFM
= 0x40000000 | SBFM
,
722 /* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
724 /* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
726 /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
727 /* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
729 MRS
= 0x00200000 | MSR
,
730 /* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
732 SEVL
= (5 << 5) | HINT
,
733 WFE
= (2 << 5) | HINT
,
734 NOP
= (0 << 5) | HINT
,
737 /* List of condition codes that we need. */
739 enum aarch64_condition_codes
750 /* Representation of a general purpose register of the form xN or wN.
752 This type is used by emitting functions that take registers as operands. */
754 struct aarch64_register
760 /* Representation of an operand. At this time, it only supports register
761 and immediate types. */
763 struct aarch64_operand
765 /* Type of the operand. */
771 /* Value of the operand according to the type. */
775 struct aarch64_register reg
;
779 /* List of registers that we are currently using, we can add more here as
780 we need to use them. */
782 /* General purpose scratch registers (64 bit). */
783 static const struct aarch64_register x0
= { 0, 1 };
784 static const struct aarch64_register x1
= { 1, 1 };
785 static const struct aarch64_register x2
= { 2, 1 };
786 static const struct aarch64_register x3
= { 3, 1 };
787 static const struct aarch64_register x4
= { 4, 1 };
789 /* General purpose scratch registers (32 bit). */
790 static const struct aarch64_register w0
= { 0, 0 };
791 static const struct aarch64_register w2
= { 2, 0 };
793 /* Intra-procedure scratch registers. */
794 static const struct aarch64_register ip0
= { 16, 1 };
796 /* Special purpose registers. */
797 static const struct aarch64_register fp
= { 29, 1 };
798 static const struct aarch64_register lr
= { 30, 1 };
799 static const struct aarch64_register sp
= { 31, 1 };
800 static const struct aarch64_register xzr
= { 31, 1 };
802 /* Dynamically allocate a new register. If we know the register
803 statically, we should make it a global as above instead of using this
806 static struct aarch64_register
807 aarch64_register (unsigned num
, int is64
)
809 return (struct aarch64_register
) { num
, is64
};
812 /* Helper function to create a register operand, for instructions with
813 different types of operands.
816 p += emit_mov (p, x0, register_operand (x1)); */
818 static struct aarch64_operand
819 register_operand (struct aarch64_register reg
)
821 struct aarch64_operand operand
;
823 operand
.type
= OPERAND_REGISTER
;
829 /* Helper function to create an immediate operand, for instructions with
830 different types of operands.
833 p += emit_mov (p, x0, immediate_operand (12)); */
835 static struct aarch64_operand
836 immediate_operand (uint32_t imm
)
838 struct aarch64_operand operand
;
840 operand
.type
= OPERAND_IMMEDIATE
;
846 /* Representation of a memory operand, used for load and store
849 The types correspond to the following variants:
851 MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
852 MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
853 MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
855 struct aarch64_memory_operand
857 /* Type of the operand. */
860 MEMORY_OPERAND_OFFSET
,
861 MEMORY_OPERAND_PREINDEX
,
862 MEMORY_OPERAND_POSTINDEX
,
864 /* Index from the base register. */
868 /* Helper function to create an offset memory operand.
871 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
873 static struct aarch64_memory_operand
874 offset_memory_operand (int32_t offset
)
876 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
879 /* Helper function to create a pre-index memory operand.
882 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
884 static struct aarch64_memory_operand
885 preindex_memory_operand (int32_t index
)
887 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
890 /* Helper function to create a post-index memory operand.
893 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
895 static struct aarch64_memory_operand
896 postindex_memory_operand (int32_t index
)
898 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
901 /* System control registers. These special registers can be written and
902 read with the MRS and MSR instructions.
904 - NZCV: Condition flags. GDB refers to this register under the CPSR
906 - FPSR: Floating-point status register.
907 - FPCR: Floating-point control registers.
908 - TPIDR_EL0: Software thread ID register. */
910 enum aarch64_system_control_registers
912 /* op0 op1 crn crm op2 */
913 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
914 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
915 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
916 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
919 /* Helper macro to mask and shift a value into a bitfield. */
921 #define ENCODE(val, size, offset) \
922 ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
924 /* Write a 32-bit unsigned integer INSN info *BUF. Return the number of
925 instructions written (aka. 1). */
928 emit_insn (uint32_t *buf
, uint32_t insn
)
934 /* Write a B or BL instruction into *BUF.
939 IS_BL specifies if the link register should be updated.
940 OFFSET is the immediate offset from the current PC. It is
941 byte-addressed but should be 4 bytes aligned. It has a limited range of
942 +/- 128MB (26 bits << 2). */
945 emit_b (uint32_t *buf
, int is_bl
, int32_t offset
)
947 uint32_t imm26
= ENCODE (offset
>> 2, 26, 0);
950 return emit_insn (buf
, BL
| imm26
);
952 return emit_insn (buf
, B
| imm26
);
955 /* Write a BCOND instruction into *BUF.
959 COND specifies the condition field.
960 OFFSET is the immediate offset from the current PC. It is
961 byte-addressed but should be 4 bytes aligned. It has a limited range of
962 +/- 1MB (19 bits << 2). */
965 emit_bcond (uint32_t *buf
, unsigned cond
, int32_t offset
)
967 return emit_insn (buf
, BCOND
| ENCODE (offset
>> 2, 19, 5)
968 | ENCODE (cond
, 4, 0));
971 /* Write a CBZ or CBNZ instruction into *BUF.
976 IS_CBNZ distinguishes between CBZ and CBNZ instructions.
977 RN is the register to test.
978 OFFSET is the immediate offset from the current PC. It is
979 byte-addressed but should be 4 bytes aligned. It has a limited range of
980 +/- 1MB (19 bits << 2). */
983 emit_cb (uint32_t *buf
, int is_cbnz
, struct aarch64_register rt
,
986 uint32_t imm19
= ENCODE (offset
>> 2, 19, 5);
987 uint32_t sf
= ENCODE (rt
.is64
, 1, 31);
990 return emit_insn (buf
, CBNZ
| sf
| imm19
| ENCODE (rt
.num
, 5, 0));
992 return emit_insn (buf
, CBZ
| sf
| imm19
| ENCODE (rt
.num
, 5, 0));
995 /* Write a TBZ or TBNZ instruction into *BUF.
997 TBZ rt, #bit, #offset
998 TBNZ rt, #bit, #offset
1000 IS_TBNZ distinguishes between TBZ and TBNZ instructions.
1001 RT is the register to test.
1002 BIT is the index of the bit to test in register RT.
1003 OFFSET is the immediate offset from the current PC. It is
1004 byte-addressed but should be 4 bytes aligned. It has a limited range of
1005 +/- 32KB (14 bits << 2). */
1008 emit_tb (uint32_t *buf
, int is_tbnz
, unsigned bit
,
1009 struct aarch64_register rt
, int32_t offset
)
1011 uint32_t imm14
= ENCODE (offset
>> 2, 14, 5);
1012 uint32_t b40
= ENCODE (bit
, 5, 19);
1013 uint32_t b5
= ENCODE (bit
>> 5, 1, 31);
1016 return emit_insn (buf
, TBNZ
| b5
| b40
| imm14
| ENCODE (rt
.num
, 5, 0));
1018 return emit_insn (buf
, TBZ
| b5
| b40
| imm14
| ENCODE (rt
.num
, 5, 0));
1021 /* Write a BLR instruction into *BUF.
1025 RN is the register to branch to. */
1028 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
1030 return emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
1033 /* Write a RET instruction into *BUF.
1037 RN is the register to branch to. */
1040 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
1042 return emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
1046 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
1047 struct aarch64_register rt
,
1048 struct aarch64_register rt2
,
1049 struct aarch64_register rn
,
1050 struct aarch64_memory_operand operand
)
1054 uint32_t write_back
;
1057 opc
= ENCODE (2, 2, 30);
1059 opc
= ENCODE (0, 2, 30);
1061 switch (operand
.type
)
1063 case MEMORY_OPERAND_OFFSET
:
1065 pre_index
= ENCODE (1, 1, 24);
1066 write_back
= ENCODE (0, 1, 23);
1069 case MEMORY_OPERAND_POSTINDEX
:
1071 pre_index
= ENCODE (0, 1, 24);
1072 write_back
= ENCODE (1, 1, 23);
1075 case MEMORY_OPERAND_PREINDEX
:
1077 pre_index
= ENCODE (1, 1, 24);
1078 write_back
= ENCODE (1, 1, 23);
1085 return emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1086 | ENCODE (operand
.index
>> 3, 7, 15)
1087 | ENCODE (rt2
.num
, 5, 10)
1088 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1091 /* Write a STP instruction into *BUF.
1093 STP rt, rt2, [rn, #offset]
1094 STP rt, rt2, [rn, #index]!
1095 STP rt, rt2, [rn], #index
1097 RT and RT2 are the registers to store.
1098 RN is the base address register.
1099 OFFSET is the immediate to add to the base address. It is limited to a
1100 -512 .. 504 range (7 bits << 3). */
1103 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1104 struct aarch64_register rt2
, struct aarch64_register rn
,
1105 struct aarch64_memory_operand operand
)
1107 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1110 /* Write a LDP instruction into *BUF.
1112 LDP rt, rt2, [rn, #offset]
1113 LDP rt, rt2, [rn, #index]!
1114 LDP rt, rt2, [rn], #index
1116 RT and RT2 are the registers to store.
1117 RN is the base address register.
1118 OFFSET is the immediate to add to the base address. It is limited to a
1119 -512 .. 504 range (7 bits << 3). */
1122 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1123 struct aarch64_register rt2
, struct aarch64_register rn
,
1124 struct aarch64_memory_operand operand
)
1126 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1129 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1131 LDP qt, qt2, [rn, #offset]
1133 RT and RT2 are the Q registers to store.
1134 RN is the base address register.
1135 OFFSET is the immediate to add to the base address. It is limited to
1136 -1024 .. 1008 range (7 bits << 4). */
1139 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1140 struct aarch64_register rn
, int32_t offset
)
1142 uint32_t opc
= ENCODE (2, 2, 30);
1143 uint32_t pre_index
= ENCODE (1, 1, 24);
1145 return emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1146 | ENCODE (offset
>> 4, 7, 15) | ENCODE (rt2
, 5, 10)
1147 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1150 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1152 STP qt, qt2, [rn, #offset]
1154 RT and RT2 are the Q registers to store.
1155 RN is the base address register.
1156 OFFSET is the immediate to add to the base address. It is limited to
1157 -1024 .. 1008 range (7 bits << 4). */
1160 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1161 struct aarch64_register rn
, int32_t offset
)
1163 uint32_t opc
= ENCODE (2, 2, 30);
1164 uint32_t pre_index
= ENCODE (1, 1, 24);
1166 return emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1167 | ENCODE (offset
>> 4, 7, 15) | ENCODE (rt2
, 5, 10)
1168 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1171 /* Helper function emitting a load or store instruction. */
1174 emit_load_store (uint32_t *buf
, uint32_t size
, enum aarch64_opcodes opcode
,
1175 struct aarch64_register rt
, struct aarch64_register rn
,
1176 struct aarch64_memory_operand operand
)
1180 switch (operand
.type
)
1182 case MEMORY_OPERAND_OFFSET
:
1184 op
= ENCODE (1, 1, 24);
1186 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1187 | ENCODE (operand
.index
>> 3, 12, 10)
1188 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1190 case MEMORY_OPERAND_POSTINDEX
:
1192 uint32_t post_index
= ENCODE (1, 2, 10);
1194 op
= ENCODE (0, 1, 24);
1196 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1197 | post_index
| ENCODE (operand
.index
, 9, 12)
1198 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1200 case MEMORY_OPERAND_PREINDEX
:
1202 uint32_t pre_index
= ENCODE (3, 2, 10);
1204 op
= ENCODE (0, 1, 24);
1206 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1207 | pre_index
| ENCODE (operand
.index
, 9, 12)
1208 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1215 /* Write a LDR instruction into *BUF.
1217 LDR rt, [rn, #offset]
1218 LDR rt, [rn, #index]!
1219 LDR rt, [rn], #index
1221 RT is the register to store.
1222 RN is the base address register.
1223 OFFSET is the immediate to add to the base address. It is limited to
1224 0 .. 32760 range (12 bits << 3). */
1227 emit_ldr (uint32_t *buf
, struct aarch64_register rt
,
1228 struct aarch64_register rn
, struct aarch64_memory_operand operand
)
1230 return emit_load_store (buf
, rt
.is64
? 3 : 2, LDR
, rt
, rn
, operand
);
1233 /* Write a LDRH instruction into *BUF.
1235 LDRH wt, [xn, #offset]
1236 LDRH wt, [xn, #index]!
1237 LDRH wt, [xn], #index
1239 RT is the register to store.
1240 RN is the base address register.
1241 OFFSET is the immediate to add to the base address. It is limited to
1242 0 .. 32760 range (12 bits << 3). */
1245 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1246 struct aarch64_register rn
,
1247 struct aarch64_memory_operand operand
)
1249 return emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1252 /* Write a LDRB instruction into *BUF.
1254 LDRB wt, [xn, #offset]
1255 LDRB wt, [xn, #index]!
1256 LDRB wt, [xn], #index
1258 RT is the register to store.
1259 RN is the base address register.
1260 OFFSET is the immediate to add to the base address. It is limited to
1261 0 .. 32760 range (12 bits << 3). */
1264 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1265 struct aarch64_register rn
,
1266 struct aarch64_memory_operand operand
)
1268 return emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1271 /* Write a LDRSW instruction into *BUF. The register size is 64-bit.
1273 LDRSW xt, [rn, #offset]
1274 LDRSW xt, [rn, #index]!
1275 LDRSW xt, [rn], #index
1277 RT is the register to store.
1278 RN is the base address register.
1279 OFFSET is the immediate to add to the base address. It is limited to
1280 0 .. 16380 range (12 bits << 2). */
1283 emit_ldrsw (uint32_t *buf
, struct aarch64_register rt
,
1284 struct aarch64_register rn
,
1285 struct aarch64_memory_operand operand
)
1287 return emit_load_store (buf
, 3, LDRSW
, rt
, rn
, operand
);
1290 /* Write a STR instruction into *BUF.
1292 STR rt, [rn, #offset]
1293 STR rt, [rn, #index]!
1294 STR rt, [rn], #index
1296 RT is the register to store.
1297 RN is the base address register.
1298 OFFSET is the immediate to add to the base address. It is limited to
1299 0 .. 32760 range (12 bits << 3). */
1302 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1303 struct aarch64_register rn
,
1304 struct aarch64_memory_operand operand
)
1306 return emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1309 /* Helper function emitting an exclusive load or store instruction. */
1312 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1313 enum aarch64_opcodes opcode
,
1314 struct aarch64_register rs
,
1315 struct aarch64_register rt
,
1316 struct aarch64_register rt2
,
1317 struct aarch64_register rn
)
1319 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1320 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1321 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1324 /* Write a LAXR instruction into *BUF.
1328 RT is the destination register.
1329 RN is the base address register. */
1332 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1333 struct aarch64_register rn
)
1335 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1339 /* Write a STXR instruction into *BUF.
1343 RS is the result register, it indicates if the store succeeded or not.
1344 RT is the destination register.
1345 RN is the base address register. */
1348 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1349 struct aarch64_register rt
, struct aarch64_register rn
)
1351 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1355 /* Write a STLR instruction into *BUF.
1359 RT is the register to store.
1360 RN is the base address register. */
1363 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1364 struct aarch64_register rn
)
1366 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1370 /* Helper function for data processing instructions with register sources. */
1373 emit_data_processing_reg (uint32_t *buf
, enum aarch64_opcodes opcode
,
1374 struct aarch64_register rd
,
1375 struct aarch64_register rn
,
1376 struct aarch64_register rm
)
1378 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1380 return emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1381 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1384 /* Helper function for data processing instructions taking either a register
1388 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1389 struct aarch64_register rd
,
1390 struct aarch64_register rn
,
1391 struct aarch64_operand operand
)
1393 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1394 /* The opcode is different for register and immediate source operands. */
1395 uint32_t operand_opcode
;
1397 if (operand
.type
== OPERAND_IMMEDIATE
)
1399 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1400 operand_opcode
= ENCODE (8, 4, 25);
1402 return emit_insn (buf
, opcode
| operand_opcode
| size
1403 | ENCODE (operand
.imm
, 12, 10)
1404 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1408 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1409 operand_opcode
= ENCODE (5, 4, 25);
1411 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1416 /* Write an ADD instruction into *BUF.
1421 This function handles both an immediate and register add.
1423 RD is the destination register.
1424 RN is the input register.
1425 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1426 OPERAND_REGISTER. */
1429 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1430 struct aarch64_register rn
, struct aarch64_operand operand
)
1432 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1435 /* Write a SUB instruction into *BUF.
1440 This function handles both an immediate and register sub.
1442 RD is the destination register.
1443 RN is the input register.
1444 IMM is the immediate to substract to RN. */
1447 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1448 struct aarch64_register rn
, struct aarch64_operand operand
)
1450 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1453 /* Write a MOV instruction into *BUF.
1458 This function handles both a wide immediate move and a register move,
1459 with the condition that the source register is not xzr. xzr and the
1460 stack pointer share the same encoding and this function only supports
1463 RD is the destination register.
1464 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1465 OPERAND_REGISTER. */
1468 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1469 struct aarch64_operand operand
)
1471 if (operand
.type
== OPERAND_IMMEDIATE
)
1473 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1474 /* Do not shift the immediate. */
1475 uint32_t shift
= ENCODE (0, 2, 21);
1477 return emit_insn (buf
, MOV
| size
| shift
1478 | ENCODE (operand
.imm
, 16, 5)
1479 | ENCODE (rd
.num
, 5, 0));
1482 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1485 /* Write a MOVK instruction into *BUF.
1487 MOVK rd, #imm, lsl #shift
1489 RD is the destination register.
1490 IMM is the immediate.
1491 SHIFT is the logical shift left to apply to IMM. */
1494 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1497 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1499 return emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1500 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1503 /* Write instructions into *BUF in order to move ADDR into a register.
1504 ADDR can be a 64-bit value.
1506 This function will emit a series of MOV and MOVK instructions, such as:
1509 MOVK xd, #(addr >> 16), lsl #16
1510 MOVK xd, #(addr >> 32), lsl #32
1511 MOVK xd, #(addr >> 48), lsl #48 */
1514 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1518 /* The MOV (wide immediate) instruction clears to top bits of the
1520 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1522 if ((addr
>> 16) != 0)
1523 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1527 if ((addr
>> 32) != 0)
1528 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1532 if ((addr
>> 48) != 0)
1533 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1538 /* Write a SUBS instruction into *BUF.
1542 This instruction update the condition flags.
1544 RD is the destination register.
1545 RN and RM are the source registers. */
1548 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1549 struct aarch64_register rn
, struct aarch64_operand operand
)
1551 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1554 /* Write a CMP instruction into *BUF.
1558 This instruction is an alias of SUBS xzr, rn, rm.
1560 RN and RM are the registers to compare. */
1563 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1564 struct aarch64_operand operand
)
1566 return emit_subs (buf
, xzr
, rn
, operand
);
1569 /* Write a AND instruction into *BUF.
1573 RD is the destination register.
1574 RN and RM are the source registers. */
1577 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1578 struct aarch64_register rn
, struct aarch64_register rm
)
1580 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1583 /* Write a ORR instruction into *BUF.
1587 RD is the destination register.
1588 RN and RM are the source registers. */
1591 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1592 struct aarch64_register rn
, struct aarch64_register rm
)
1594 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1597 /* Write a ORN instruction into *BUF.
1601 RD is the destination register.
1602 RN and RM are the source registers. */
1605 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1606 struct aarch64_register rn
, struct aarch64_register rm
)
1608 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1611 /* Write a EOR instruction into *BUF.
1615 RD is the destination register.
1616 RN and RM are the source registers. */
1619 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1620 struct aarch64_register rn
, struct aarch64_register rm
)
1622 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1625 /* Write a MVN instruction into *BUF.
1629 This is an alias for ORN rd, xzr, rm.
1631 RD is the destination register.
1632 RM is the source register. */
1635 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1636 struct aarch64_register rm
)
1638 return emit_orn (buf
, rd
, xzr
, rm
);
1641 /* Write a LSLV instruction into *BUF.
1645 RD is the destination register.
1646 RN and RM are the source registers. */
1649 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1650 struct aarch64_register rn
, struct aarch64_register rm
)
1652 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1655 /* Write a LSRV instruction into *BUF.
1659 RD is the destination register.
1660 RN and RM are the source registers. */
1663 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1664 struct aarch64_register rn
, struct aarch64_register rm
)
1666 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1669 /* Write a ASRV instruction into *BUF.
1673 RD is the destination register.
1674 RN and RM are the source registers. */
1677 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1678 struct aarch64_register rn
, struct aarch64_register rm
)
1680 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1683 /* Write a MUL instruction into *BUF.
1687 RD is the destination register.
1688 RN and RM are the source registers. */
1691 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1692 struct aarch64_register rn
, struct aarch64_register rm
)
1694 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1697 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1701 RT is the destination register.
1702 SYSTEM_REG is special purpose register to read. */
1705 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1706 enum aarch64_system_control_registers system_reg
)
1708 return emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1709 | ENCODE (rt
.num
, 5, 0));
1712 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1716 SYSTEM_REG is special purpose register to write.
1717 RT is the input register. */
1720 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1721 struct aarch64_register rt
)
1723 return emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1724 | ENCODE (rt
.num
, 5, 0));
1727 /* Write a SEVL instruction into *BUF.
1729 This is a hint instruction telling the hardware to trigger an event. */
1732 emit_sevl (uint32_t *buf
)
1734 return emit_insn (buf
, SEVL
);
1737 /* Write a WFE instruction into *BUF.
1739 This is a hint instruction telling the hardware to wait for an event. */
1742 emit_wfe (uint32_t *buf
)
1744 return emit_insn (buf
, WFE
);
1747 /* Write a SBFM instruction into *BUF.
1749 SBFM rd, rn, #immr, #imms
1751 This instruction moves the bits from #immr to #imms into the
1752 destination, sign extending the result.
1754 RD is the destination register.
1755 RN is the source register.
1756 IMMR is the bit number to start at (least significant bit).
1757 IMMS is the bit number to stop at (most significant bit). */
1760 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1761 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1763 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1764 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1766 return emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1767 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1768 | ENCODE (rd
.num
, 5, 0));
1771 /* Write a SBFX instruction into *BUF.
1773 SBFX rd, rn, #lsb, #width
1775 This instruction moves #width bits from #lsb into the destination, sign
1776 extending the result. This is an alias for:
1778 SBFM rd, rn, #lsb, #(lsb + width - 1)
1780 RD is the destination register.
1781 RN is the source register.
1782 LSB is the bit number to start at (least significant bit).
1783 WIDTH is the number of bits to move. */
1786 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1787 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1789 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1792 /* Write a UBFM instruction into *BUF.
1794 UBFM rd, rn, #immr, #imms
1796 This instruction moves the bits from #immr to #imms into the
1797 destination, extending the result with zeros.
1799 RD is the destination register.
1800 RN is the source register.
1801 IMMR is the bit number to start at (least significant bit).
1802 IMMS is the bit number to stop at (most significant bit). */
1805 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1806 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1808 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1809 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1811 return emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1812 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1813 | ENCODE (rd
.num
, 5, 0));
1816 /* Write a UBFX instruction into *BUF.
1818 UBFX rd, rn, #lsb, #width
1820 This instruction moves #width bits from #lsb into the destination,
1821 extending the result with zeros. This is an alias for:
1823 UBFM rd, rn, #lsb, #(lsb + width - 1)
1825 RD is the destination register.
1826 RN is the source register.
1827 LSB is the bit number to start at (least significant bit).
1828 WIDTH is the number of bits to move. */
1831 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1832 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1834 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1837 /* Write a CSINC instruction into *BUF.
1839 CSINC rd, rn, rm, cond
1841 This instruction conditionally increments rn or rm and places the result
1842 in rd. rn is chosen is the condition is true.
1844 RD is the destination register.
1845 RN and RM are the source registers.
1846 COND is the encoded condition. */
1849 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1850 struct aarch64_register rn
, struct aarch64_register rm
,
1853 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1855 return emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1856 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1857 | ENCODE (rd
.num
, 5, 0));
1860 /* Write a CSET instruction into *BUF.
1864 This instruction conditionally write 1 or 0 in the destination register.
1865 1 is written if the condition is true. This is an alias for:
1867 CSINC rd, xzr, xzr, !cond
1869 Note that the condition needs to be inverted.
1871 RD is the destination register.
1872 RN and RM are the source registers.
1873 COND is the encoded condition. */
1876 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1878 /* The least significant bit of the condition needs toggling in order to
1880 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1883 /* Write a NOP instruction into *BUF. */
1886 emit_nop (uint32_t *buf
)
1888 return emit_insn (buf
, NOP
);
1891 /* Write LEN instructions from BUF into the inferior memory at *TO.
1893 Note instructions are always little endian on AArch64, unlike data. */
1896 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1898 size_t byte_len
= len
* sizeof (uint32_t);
1899 #if (__BYTE_ORDER == __BIG_ENDIAN)
1900 uint32_t *le_buf
= xmalloc (byte_len
);
1903 for (i
= 0; i
< len
; i
++)
1904 le_buf
[i
] = htole32 (buf
[i
]);
1906 write_inferior_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1910 write_inferior_memory (*to
, (const unsigned char *) buf
, byte_len
);
1916 /* Helper function. Return 1 if VAL can be encoded in BITS bits. */
1919 can_encode_int32 (int32_t val
, unsigned bits
)
1921 /* This must be an arithemic shift. */
1922 int32_t rest
= val
>> bits
;
1924 return rest
== 0 || rest
== -1;
1927 /* Relocate an instruction from OLDLOC to *TO. This function will also
1928 increment TO by the number of bytes the new instruction(s) take(s).
1930 PC relative instructions need to be handled specifically:
1937 - LDR/LDRSW (literal) */
1940 aarch64_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1959 target_read_uint32 (oldloc
, &insn
);
1961 if (aarch64_decode_b (oldloc
, insn
, &is_bl
, &offset
))
1963 offset
= (oldloc
- *to
+ offset
);
1965 if (can_encode_int32 (offset
, 28))
1966 p
+= emit_b (p
, is_bl
, offset
);
1970 else if (aarch64_decode_bcond (oldloc
, insn
, &cond
, &offset
))
1972 offset
= (oldloc
- *to
+ offset
);
1974 if (can_encode_int32 (offset
, 21))
1975 p
+= emit_bcond (p
, cond
, offset
);
1976 else if (can_encode_int32 (offset
, 28))
1978 /* The offset is out of range for a conditional branch
1979 instruction but not for a unconditional branch. We can use
1980 the following instructions instead:
1982 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1983 B NOT_TAKEN ; Else jump over TAKEN and continue.
1990 p
+= emit_bcond (p
, cond
, 8);
1991 p
+= emit_b (p
, 0, 8);
1992 p
+= emit_b (p
, 0, offset
- 8);
1997 else if (aarch64_decode_cb (oldloc
, insn
, &is64
, &is_cbnz
, &rn
, &offset
))
1999 offset
= (oldloc
- *to
+ offset
);
2001 if (can_encode_int32 (offset
, 21))
2002 p
+= emit_cb (p
, is_cbnz
, aarch64_register (rn
, is64
), offset
);
2003 else if (can_encode_int32 (offset
, 28))
2005 /* The offset is out of range for a compare and branch
2006 instruction but not for a unconditional branch. We can use
2007 the following instructions instead:
2009 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2010 B NOT_TAKEN ; Else jump over TAKEN and continue.
2016 p
+= emit_cb (p
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2017 p
+= emit_b (p
, 0, 8);
2018 p
+= emit_b (p
, 0, offset
- 8);
2023 else if (aarch64_decode_tb (oldloc
, insn
, &is_tbnz
, &bit
, &rt
, &offset
))
2025 offset
= (oldloc
- *to
+ offset
);
2027 if (can_encode_int32 (offset
, 16))
2028 p
+= emit_tb (p
, is_tbnz
, bit
, aarch64_register (rt
, 1), offset
);
2029 else if (can_encode_int32 (offset
, 28))
2031 /* The offset is out of range for a test bit and branch
2032 instruction but not for a unconditional branch. We can use
2033 the following instructions instead:
2035 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2036 B NOT_TAKEN ; Else jump over TAKEN and continue.
2042 p
+= emit_tb (p
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2043 p
+= emit_b (p
, 0, 8);
2044 p
+= emit_b (p
, 0, offset
- 8);
2049 else if (aarch64_decode_adr (oldloc
, insn
, &is_adrp
, &rd
, &offset
))
2052 /* We know exactly the address the ADR{P,} instruction will compute.
2053 We can just write it to the destination register. */
2054 CORE_ADDR address
= oldloc
+ offset
;
2058 /* Clear the lower 12 bits of the offset to get the 4K page. */
2059 p
+= emit_mov_addr (p
, aarch64_register (rd
, 1),
2063 p
+= emit_mov_addr (p
, aarch64_register (rd
, 1), address
);
2065 else if (aarch64_decode_ldr_literal (oldloc
, insn
, &is_sw
, &is64
, &rt
,
2068 /* We know exactly what address to load from, and what register we
2071 MOV xd, #(oldloc + offset)
2072 MOVK xd, #((oldloc + offset) >> 16), lsl #16
2075 LDR xd, [xd] ; or LDRSW xd, [xd]
2078 CORE_ADDR address
= oldloc
+ offset
;
2080 p
+= emit_mov_addr (p
, aarch64_register (rt
, 1), address
);
2083 p
+= emit_ldrsw (p
, aarch64_register (rt
, 1),
2084 aarch64_register (rt
, 1),
2085 offset_memory_operand (0));
2087 p
+= emit_ldr (p
, aarch64_register (rt
, is64
),
2088 aarch64_register (rt
, 1),
2089 offset_memory_operand (0));
2093 /* The instruction is not PC relative. Just re-emit it at the new
2095 p
+= emit_insn (p
, insn
);
2098 append_insns (to
, p
- buf
, buf
);
2101 /* Implementation of linux_target_ops method
2102 "install_fast_tracepoint_jump_pad". */
2105 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
2107 CORE_ADDR collector
,
2110 CORE_ADDR
*jump_entry
,
2111 CORE_ADDR
*trampoline
,
2112 ULONGEST
*trampoline_size
,
2113 unsigned char *jjump_pad_insn
,
2114 ULONGEST
*jjump_pad_insn_size
,
2115 CORE_ADDR
*adjusted_insn_addr
,
2116 CORE_ADDR
*adjusted_insn_addr_end
,
2123 CORE_ADDR buildaddr
= *jump_entry
;
2125 /* We need to save the current state on the stack both to restore it
2126 later and to collect register values when the tracepoint is hit.
2128 The saved registers are pushed in a layout that needs to be in sync
2129 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2130 the supply_fast_tracepoint_registers function will fill in the
2131 register cache from a pointer to saved registers on the stack we build
2134 For simplicity, we set the size of each cell on the stack to 16 bytes.
2135 This way one cell can hold any register type, from system registers
2136 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2137 has to be 16 bytes aligned anyway.
2139 Note that the CPSR register does not exist on AArch64. Instead we
2140 can access system bits describing the process state with the
2141 MRS/MSR instructions, namely the condition flags. We save them as
2142 if they are part of a CPSR register because that's how GDB
2143 interprets these system bits. At the moment, only the condition
2144 flags are saved in CPSR (NZCV).
2146 Stack layout, each cell is 16 bytes (descending):
2148 High *-------- SIMD&FP registers from 31 down to 0. --------*
2154 *---- General purpose registers from 30 down to 0. ----*
2160 *------------- Special purpose registers. -------------*
2163 | CPSR (NZCV) | 5 cells
2166 *------------- collecting_t object --------------------*
2167 | TPIDR_EL0 | struct tracepoint * |
2168 Low *------------------------------------------------------*
2170 After this stack is set up, we issue a call to the collector, passing
2171 it the saved registers at (SP + 16). */
2173 /* Push SIMD&FP registers on the stack:
2175 SUB sp, sp, #(32 * 16)
2177 STP q30, q31, [sp, #(30 * 16)]
2182 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2183 for (i
= 30; i
>= 0; i
-= 2)
2184 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2186 /* Push general puspose registers on the stack. Note that we do not need
2187 to push x31 as it represents the xzr register and not the stack
2188 pointer in a STR instruction.
2190 SUB sp, sp, #(31 * 16)
2192 STR x30, [sp, #(30 * 16)]
2197 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2198 for (i
= 30; i
>= 0; i
-= 1)
2199 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2200 offset_memory_operand (i
* 16));
2202 /* Make space for 5 more cells.
2204 SUB sp, sp, #(5 * 16)
2207 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2212 ADD x4, sp, #((32 + 31 + 5) * 16)
2213 STR x4, [sp, #(4 * 16)]
2216 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2217 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2219 /* Save PC (tracepoint address):
2224 STR x3, [sp, #(3 * 16)]
2228 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2229 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2231 /* Save CPSR (NZCV), FPSR and FPCR:
2237 STR x2, [sp, #(2 * 16)]
2238 STR x1, [sp, #(1 * 16)]
2239 STR x0, [sp, #(0 * 16)]
2242 p
+= emit_mrs (p
, x2
, NZCV
);
2243 p
+= emit_mrs (p
, x1
, FPSR
);
2244 p
+= emit_mrs (p
, x0
, FPCR
);
2245 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2246 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2247 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2249 /* Push the collecting_t object. It consist of the address of the
2250 tracepoint and an ID for the current thread. We get the latter by
2251 reading the tpidr_el0 system register. It corresponds to the
2252 NT_ARM_TLS register accessible with ptrace.
2259 STP x0, x1, [sp, #-16]!
2263 p
+= emit_mov_addr (p
, x0
, tpoint
);
2264 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2265 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2269 The shared memory for the lock is at lockaddr. It will hold zero
2270 if no-one is holding the lock, otherwise it contains the address of
2271 the collecting_t object on the stack of the thread which acquired it.
2273 At this stage, the stack pointer points to this thread's collecting_t
2276 We use the following registers:
2277 - x0: Address of the lock.
2278 - x1: Pointer to collecting_t object.
2279 - x2: Scratch register.
2285 ; Trigger an event local to this core. So the following WFE
2286 ; instruction is ignored.
2289 ; Wait for an event. The event is triggered by either the SEVL
2290 ; or STLR instructions (store release).
2293 ; Atomically read at lockaddr. This marks the memory location as
2294 ; exclusive. This instruction also has memory constraints which
2295 ; make sure all previous data reads and writes are done before
2299 ; Try again if another thread holds the lock.
2302 ; We can lock it! Write the address of the collecting_t object.
2303 ; This instruction will fail if the memory location is not marked
2304 ; as exclusive anymore. If it succeeds, it will remove the
2305 ; exclusive mark on the memory location. This way, if another
2306 ; thread executes this instruction before us, we will fail and try
2313 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2314 p
+= emit_mov (p
, x1
, register_operand (sp
));
2318 p
+= emit_ldaxr (p
, x2
, x0
);
2319 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2320 p
+= emit_stxr (p
, w2
, x1
, x0
);
2321 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2323 /* Call collector (struct tracepoint *, unsigned char *):
2328 ; Saved registers start after the collecting_t object.
2331 ; We use an intra-procedure-call scratch register.
2332 MOV ip0, #(collector)
2335 ; And call back to C!
2340 p
+= emit_mov_addr (p
, x0
, tpoint
);
2341 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2343 p
+= emit_mov_addr (p
, ip0
, collector
);
2344 p
+= emit_blr (p
, ip0
);
2346 /* Release the lock.
2351 ; This instruction is a normal store with memory ordering
2352 ; constraints. Thanks to this we do not have to put a data
2353 ; barrier instruction to make sure all data read and writes are done
2354 ; before this instruction is executed. Furthermore, this instrucion
2355 ; will trigger an event, letting other threads know they can grab
2360 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2361 p
+= emit_stlr (p
, xzr
, x0
);
2363 /* Free collecting_t object:
2368 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2370 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2371 registers from the stack.
2373 LDR x2, [sp, #(2 * 16)]
2374 LDR x1, [sp, #(1 * 16)]
2375 LDR x0, [sp, #(0 * 16)]
2381 ADD sp, sp #(5 * 16)
2384 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2385 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2386 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2387 p
+= emit_msr (p
, NZCV
, x2
);
2388 p
+= emit_msr (p
, FPSR
, x1
);
2389 p
+= emit_msr (p
, FPCR
, x0
);
2391 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2393 /* Pop general purpose registers:
2397 LDR x30, [sp, #(30 * 16)]
2399 ADD sp, sp, #(31 * 16)
2402 for (i
= 0; i
<= 30; i
+= 1)
2403 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2404 offset_memory_operand (i
* 16));
2405 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2407 /* Pop SIMD&FP registers:
2411 LDP q30, q31, [sp, #(30 * 16)]
2413 ADD sp, sp, #(32 * 16)
2416 for (i
= 0; i
<= 30; i
+= 2)
2417 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2418 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2420 /* Write the code into the inferior memory. */
2421 append_insns (&buildaddr
, p
- buf
, buf
);
2423 /* Now emit the relocated instruction. */
2424 *adjusted_insn_addr
= buildaddr
;
2425 aarch64_relocate_instruction (&buildaddr
, tpaddr
);
2426 *adjusted_insn_addr_end
= buildaddr
;
2428 /* We may not have been able to relocate the instruction. */
2429 if (*adjusted_insn_addr
== *adjusted_insn_addr_end
)
2432 "E.Could not relocate instruction from %s to %s.",
2433 core_addr_to_string_nz (tpaddr
),
2434 core_addr_to_string_nz (buildaddr
));
2438 /* Go back to the start of the buffer. */
2441 /* Emit a branch back from the jump pad. */
2442 offset
= (tpaddr
+ orig_size
- buildaddr
);
2443 if (!can_encode_int32 (offset
, 28))
2446 "E.Jump back from jump pad too far from tracepoint "
2447 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2452 p
+= emit_b (p
, 0, offset
);
2453 append_insns (&buildaddr
, p
- buf
, buf
);
2455 /* Give the caller a branch instruction into the jump pad. */
2456 offset
= (*jump_entry
- tpaddr
);
2457 if (!can_encode_int32 (offset
, 28))
2460 "E.Jump pad too far from tracepoint "
2461 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2466 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2467 *jjump_pad_insn_size
= 4;
2469 /* Return the end address of our pad. */
2470 *jump_entry
= buildaddr
;
2475 /* Helper function writing LEN instructions from START into
2476 current_insn_ptr. */
2479 emit_ops_insns (const uint32_t *start
, int len
)
2481 CORE_ADDR buildaddr
= current_insn_ptr
;
2484 debug_printf ("Adding %d instrucions at %s\n",
2485 len
, paddress (buildaddr
));
2487 append_insns (&buildaddr
, len
, start
);
2488 current_insn_ptr
= buildaddr
;
2491 /* Pop a register from the stack. */
2494 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2496 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2499 /* Push a register on the stack. */
2502 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2504 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2507 /* Implementation of emit_ops method "emit_prologue". */
2510 aarch64_emit_prologue (void)
2515 /* This function emit a prologue for the following function prototype:
2517 enum eval_result_type f (unsigned char *regs,
2520 The first argument is a buffer of raw registers. The second
2521 argument is the result of
2522 evaluating the expression, which will be set to whatever is on top of
2523 the stack at the end.
2525 The stack set up by the prologue is as such:
2527 High *------------------------------------------------------*
2530 | x1 (ULONGEST *value) |
2531 | x0 (unsigned char *regs) |
2532 Low *------------------------------------------------------*
2534 As we are implementing a stack machine, each opcode can expand the
2535 stack so we never know how far we are from the data saved by this
2536 prologue. In order to be able refer to value and regs later, we save
2537 the current stack pointer in the frame pointer. This way, it is not
2538 clobbered when calling C functions.
2540 Finally, throughtout every operation, we are using register x0 as the
2541 top of the stack, and x1 as a scratch register. */
2543 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2544 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2545 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2547 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2550 emit_ops_insns (buf
, p
- buf
);
2553 /* Implementation of emit_ops method "emit_epilogue". */
2556 aarch64_emit_epilogue (void)
2561 /* Store the result of the expression (x0) in *value. */
2562 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2563 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2564 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2566 /* Restore the previous state. */
2567 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2568 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2570 /* Return expr_eval_no_error. */
2571 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2572 p
+= emit_ret (p
, lr
);
2574 emit_ops_insns (buf
, p
- buf
);
2577 /* Implementation of emit_ops method "emit_add". */
2580 aarch64_emit_add (void)
2585 p
+= emit_pop (p
, x1
);
2586 p
+= emit_add (p
, x0
, x0
, register_operand (x1
));
2588 emit_ops_insns (buf
, p
- buf
);
2591 /* Implementation of emit_ops method "emit_sub". */
2594 aarch64_emit_sub (void)
2599 p
+= emit_pop (p
, x1
);
2600 p
+= emit_sub (p
, x0
, x0
, register_operand (x1
));
2602 emit_ops_insns (buf
, p
- buf
);
2605 /* Implementation of emit_ops method "emit_mul". */
2608 aarch64_emit_mul (void)
2613 p
+= emit_pop (p
, x1
);
2614 p
+= emit_mul (p
, x0
, x1
, x0
);
2616 emit_ops_insns (buf
, p
- buf
);
2619 /* Implementation of emit_ops method "emit_lsh". */
2622 aarch64_emit_lsh (void)
2627 p
+= emit_pop (p
, x1
);
2628 p
+= emit_lslv (p
, x0
, x1
, x0
);
2630 emit_ops_insns (buf
, p
- buf
);
2633 /* Implementation of emit_ops method "emit_rsh_signed". */
2636 aarch64_emit_rsh_signed (void)
2641 p
+= emit_pop (p
, x1
);
2642 p
+= emit_asrv (p
, x0
, x1
, x0
);
2644 emit_ops_insns (buf
, p
- buf
);
2647 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2650 aarch64_emit_rsh_unsigned (void)
2655 p
+= emit_pop (p
, x1
);
2656 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2658 emit_ops_insns (buf
, p
- buf
);
2661 /* Implementation of emit_ops method "emit_ext". */
2664 aarch64_emit_ext (int arg
)
2669 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2671 emit_ops_insns (buf
, p
- buf
);
2674 /* Implementation of emit_ops method "emit_log_not". */
2677 aarch64_emit_log_not (void)
2682 /* If the top of the stack is 0, replace it with 1. Else replace it with
2685 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2686 p
+= emit_cset (p
, x0
, EQ
);
2688 emit_ops_insns (buf
, p
- buf
);
2691 /* Implementation of emit_ops method "emit_bit_and". */
2694 aarch64_emit_bit_and (void)
2699 p
+= emit_pop (p
, x1
);
2700 p
+= emit_and (p
, x0
, x0
, x1
);
2702 emit_ops_insns (buf
, p
- buf
);
2705 /* Implementation of emit_ops method "emit_bit_or". */
2708 aarch64_emit_bit_or (void)
2713 p
+= emit_pop (p
, x1
);
2714 p
+= emit_orr (p
, x0
, x0
, x1
);
2716 emit_ops_insns (buf
, p
- buf
);
2719 /* Implementation of emit_ops method "emit_bit_xor". */
2722 aarch64_emit_bit_xor (void)
2727 p
+= emit_pop (p
, x1
);
2728 p
+= emit_eor (p
, x0
, x0
, x1
);
2730 emit_ops_insns (buf
, p
- buf
);
2733 /* Implementation of emit_ops method "emit_bit_not". */
2736 aarch64_emit_bit_not (void)
2741 p
+= emit_mvn (p
, x0
, x0
);
2743 emit_ops_insns (buf
, p
- buf
);
2746 /* Implementation of emit_ops method "emit_equal". */
2749 aarch64_emit_equal (void)
2754 p
+= emit_pop (p
, x1
);
2755 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2756 p
+= emit_cset (p
, x0
, EQ
);
2758 emit_ops_insns (buf
, p
- buf
);
2761 /* Implementation of emit_ops method "emit_less_signed". */
2764 aarch64_emit_less_signed (void)
2769 p
+= emit_pop (p
, x1
);
2770 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2771 p
+= emit_cset (p
, x0
, LT
);
2773 emit_ops_insns (buf
, p
- buf
);
2776 /* Implementation of emit_ops method "emit_less_unsigned". */
2779 aarch64_emit_less_unsigned (void)
2784 p
+= emit_pop (p
, x1
);
2785 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2786 p
+= emit_cset (p
, x0
, LO
);
2788 emit_ops_insns (buf
, p
- buf
);
2791 /* Implementation of emit_ops method "emit_ref". */
2794 aarch64_emit_ref (int size
)
2802 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2805 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2808 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2811 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2814 /* Unknown size, bail on compilation. */
2819 emit_ops_insns (buf
, p
- buf
);
2822 /* Implementation of emit_ops method "emit_if_goto". */
2825 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2830 /* The Z flag is set or cleared here. */
2831 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2832 /* This instruction must not change the Z flag. */
2833 p
+= emit_pop (p
, x0
);
2834 /* Branch over the next instruction if x0 == 0. */
2835 p
+= emit_bcond (p
, EQ
, 8);
2837 /* The NOP instruction will be patched with an unconditional branch. */
2839 *offset_p
= (p
- buf
) * 4;
2844 emit_ops_insns (buf
, p
- buf
);
2847 /* Implementation of emit_ops method "emit_goto". */
2850 aarch64_emit_goto (int *offset_p
, int *size_p
)
2855 /* The NOP instruction will be patched with an unconditional branch. */
2862 emit_ops_insns (buf
, p
- buf
);
2865 /* Implementation of emit_ops method "write_goto_address". */
2868 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2872 emit_b (&insn
, 0, to
- from
);
2873 append_insns (&from
, 1, &insn
);
2876 /* Implementation of emit_ops method "emit_const". */
2879 aarch64_emit_const (LONGEST num
)
2884 p
+= emit_mov_addr (p
, x0
, num
);
2886 emit_ops_insns (buf
, p
- buf
);
2889 /* Implementation of emit_ops method "emit_call". */
2892 aarch64_emit_call (CORE_ADDR fn
)
2897 p
+= emit_mov_addr (p
, ip0
, fn
);
2898 p
+= emit_blr (p
, ip0
);
2900 emit_ops_insns (buf
, p
- buf
);
2903 /* Implementation of emit_ops method "emit_reg". */
2906 aarch64_emit_reg (int reg
)
2911 /* Set x0 to unsigned char *regs. */
2912 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2913 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2914 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2916 emit_ops_insns (buf
, p
- buf
);
2918 aarch64_emit_call (get_raw_reg_func_addr ());
2921 /* Implementation of emit_ops method "emit_pop". */
2924 aarch64_emit_pop (void)
2929 p
+= emit_pop (p
, x0
);
2931 emit_ops_insns (buf
, p
- buf
);
2934 /* Implementation of emit_ops method "emit_stack_flush". */
2937 aarch64_emit_stack_flush (void)
2942 p
+= emit_push (p
, x0
);
2944 emit_ops_insns (buf
, p
- buf
);
2947 /* Implementation of emit_ops method "emit_zero_ext". */
2950 aarch64_emit_zero_ext (int arg
)
2955 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2957 emit_ops_insns (buf
, p
- buf
);
2960 /* Implementation of emit_ops method "emit_swap". */
2963 aarch64_emit_swap (void)
2968 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2969 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2970 p
+= emit_mov (p
, x0
, register_operand (x1
));
2972 emit_ops_insns (buf
, p
- buf
);
2975 /* Implementation of emit_ops method "emit_stack_adjust". */
2978 aarch64_emit_stack_adjust (int n
)
2980 /* This is not needed with our design. */
2984 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2986 emit_ops_insns (buf
, p
- buf
);
2989 /* Implementation of emit_ops method "emit_int_call_1". */
2992 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2997 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2999 emit_ops_insns (buf
, p
- buf
);
3001 aarch64_emit_call (fn
);
3004 /* Implementation of emit_ops method "emit_void_call_2". */
3007 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3012 /* Push x0 on the stack. */
3013 aarch64_emit_stack_flush ();
3015 /* Setup arguments for the function call:
3018 x1: top of the stack
3023 p
+= emit_mov (p
, x1
, register_operand (x0
));
3024 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3026 emit_ops_insns (buf
, p
- buf
);
3028 aarch64_emit_call (fn
);
3031 aarch64_emit_pop ();
3034 /* Implementation of emit_ops method "emit_eq_goto". */
3037 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
3042 p
+= emit_pop (p
, x1
);
3043 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3044 /* Branch over the next instruction if x0 != x1. */
3045 p
+= emit_bcond (p
, NE
, 8);
3046 /* The NOP instruction will be patched with an unconditional branch. */
3048 *offset_p
= (p
- buf
) * 4;
3053 emit_ops_insns (buf
, p
- buf
);
3056 /* Implementation of emit_ops method "emit_ne_goto". */
3059 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
3064 p
+= emit_pop (p
, x1
);
3065 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3066 /* Branch over the next instruction if x0 == x1. */
3067 p
+= emit_bcond (p
, EQ
, 8);
3068 /* The NOP instruction will be patched with an unconditional branch. */
3070 *offset_p
= (p
- buf
) * 4;
3075 emit_ops_insns (buf
, p
- buf
);
3078 /* Implementation of emit_ops method "emit_lt_goto". */
3081 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
3086 p
+= emit_pop (p
, x1
);
3087 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3088 /* Branch over the next instruction if x0 >= x1. */
3089 p
+= emit_bcond (p
, GE
, 8);
3090 /* The NOP instruction will be patched with an unconditional branch. */
3092 *offset_p
= (p
- buf
) * 4;
3097 emit_ops_insns (buf
, p
- buf
);
3100 /* Implementation of emit_ops method "emit_le_goto". */
3103 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
3108 p
+= emit_pop (p
, x1
);
3109 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3110 /* Branch over the next instruction if x0 > x1. */
3111 p
+= emit_bcond (p
, GT
, 8);
3112 /* The NOP instruction will be patched with an unconditional branch. */
3114 *offset_p
= (p
- buf
) * 4;
3119 emit_ops_insns (buf
, p
- buf
);
3122 /* Implementation of emit_ops method "emit_gt_goto". */
3125 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3130 p
+= emit_pop (p
, x1
);
3131 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3132 /* Branch over the next instruction if x0 <= x1. */
3133 p
+= emit_bcond (p
, LE
, 8);
3134 /* The NOP instruction will be patched with an unconditional branch. */
3136 *offset_p
= (p
- buf
) * 4;
3141 emit_ops_insns (buf
, p
- buf
);
3144 /* Implementation of emit_ops method "emit_ge_got". */
3147 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3152 p
+= emit_pop (p
, x1
);
3153 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3154 /* Branch over the next instruction if x0 <= x1. */
3155 p
+= emit_bcond (p
, LT
, 8);
3156 /* The NOP instruction will be patched with an unconditional branch. */
3158 *offset_p
= (p
- buf
) * 4;
3163 emit_ops_insns (buf
, p
- buf
);
3166 static struct emit_ops aarch64_emit_ops_impl
=
3168 aarch64_emit_prologue
,
3169 aarch64_emit_epilogue
,
3174 aarch64_emit_rsh_signed
,
3175 aarch64_emit_rsh_unsigned
,
3177 aarch64_emit_log_not
,
3178 aarch64_emit_bit_and
,
3179 aarch64_emit_bit_or
,
3180 aarch64_emit_bit_xor
,
3181 aarch64_emit_bit_not
,
3183 aarch64_emit_less_signed
,
3184 aarch64_emit_less_unsigned
,
3186 aarch64_emit_if_goto
,
3188 aarch64_write_goto_address
,
3193 aarch64_emit_stack_flush
,
3194 aarch64_emit_zero_ext
,
3196 aarch64_emit_stack_adjust
,
3197 aarch64_emit_int_call_1
,
3198 aarch64_emit_void_call_2
,
3199 aarch64_emit_eq_goto
,
3200 aarch64_emit_ne_goto
,
3201 aarch64_emit_lt_goto
,
3202 aarch64_emit_le_goto
,
3203 aarch64_emit_gt_goto
,
3204 aarch64_emit_ge_got
,
3207 /* Implementation of linux_target_ops method "emit_ops". */
3209 static struct emit_ops
*
3210 aarch64_emit_ops (void)
3212 return &aarch64_emit_ops_impl
;
3215 /* Implementation of linux_target_ops method
3216 "get_min_fast_tracepoint_insn_len". */
3219 aarch64_get_min_fast_tracepoint_insn_len (void)
3224 /* Implementation of linux_target_ops method "supports_range_stepping". */
3227 aarch64_supports_range_stepping (void)
3232 struct linux_target_ops the_low_target
=
3236 aarch64_cannot_fetch_register
,
3237 aarch64_cannot_store_register
,
3238 NULL
, /* fetch_register */
3241 (const unsigned char *) &aarch64_breakpoint
,
3242 aarch64_breakpoint_len
,
3243 NULL
, /* breakpoint_reinsert_addr */
3244 0, /* decr_pc_after_break */
3245 aarch64_breakpoint_at
,
3246 aarch64_supports_z_point_type
,
3247 aarch64_insert_point
,
3248 aarch64_remove_point
,
3249 aarch64_stopped_by_watchpoint
,
3250 aarch64_stopped_data_address
,
3251 NULL
, /* collect_ptrace_register */
3252 NULL
, /* supply_ptrace_register */
3253 aarch64_linux_siginfo_fixup
,
3254 aarch64_linux_new_process
,
3255 aarch64_linux_new_thread
,
3256 aarch64_linux_new_fork
,
3257 aarch64_linux_prepare_to_resume
,
3258 NULL
, /* process_qsupported */
3259 aarch64_supports_tracepoints
,
3260 aarch64_get_thread_area
,
3261 aarch64_install_fast_tracepoint_jump_pad
,
3263 aarch64_get_min_fast_tracepoint_insn_len
,
3264 aarch64_supports_range_stepping
,
3268 initialize_low_arch (void)
3270 init_registers_aarch64 ();
3272 initialize_low_arch_aarch32 ();
3274 initialize_regsets_info (&aarch64_regsets_info
);