1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2018 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
41 #include "arch/aarch64.h"
42 #include "linux-aarch64-tdesc.h"
48 /* Per-process arch-specific data we want to keep. */
50 struct arch_process_info
52 /* Hardware breakpoint/watchpoint data.
53 The reason for them to be per-process rather than per-thread is
54 due to the lack of information in the gdbserver environment;
55 gdbserver is not told that whether a requested hardware
56 breakpoint/watchpoint is thread specific or not, so it has to set
57 each hw bp/wp for every thread in the current process. The
58 higher level bp/wp management in gdb will resume a thread if a hw
59 bp/wp trap is not expected for it. Since the hw bp/wp setting is
60 same for each thread, it is reasonable for the data to live here.
62 struct aarch64_debug_reg_state debug_reg_state
;
65 /* Return true if the size of register 0 is 8 byte. */
70 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
72 return register_size (regcache
->tdesc
, 0) == 8;
75 /* Implementation of linux_target_ops method "cannot_store_register". */
78 aarch64_cannot_store_register (int regno
)
80 return regno
>= AARCH64_NUM_REGS
;
83 /* Implementation of linux_target_ops method "cannot_fetch_register". */
86 aarch64_cannot_fetch_register (int regno
)
88 return regno
>= AARCH64_NUM_REGS
;
92 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
94 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
97 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
98 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
99 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
100 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
101 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
105 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
107 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
110 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
111 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
112 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
113 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
114 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
118 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
120 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
123 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
124 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
125 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
126 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
130 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
132 const struct user_fpsimd_state
*regset
133 = (const struct user_fpsimd_state
*) buf
;
136 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
137 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
138 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
139 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
142 /* Enable miscellaneous debugging output. The name is historical - it
143 was originally used to debug LinuxThreads support. */
144 extern int debug_threads
;
146 /* Implementation of linux_target_ops method "get_pc". */
149 aarch64_get_pc (struct regcache
*regcache
)
151 if (register_size (regcache
->tdesc
, 0) == 8)
152 return linux_get_pc_64bit (regcache
);
154 return linux_get_pc_32bit (regcache
);
157 /* Implementation of linux_target_ops method "set_pc". */
160 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
162 if (register_size (regcache
->tdesc
, 0) == 8)
163 linux_set_pc_64bit (regcache
, pc
);
165 linux_set_pc_32bit (regcache
, pc
);
168 #define aarch64_breakpoint_len 4
170 /* AArch64 BRK software debug mode instruction.
171 This instruction needs to match gdb/aarch64-tdep.c
172 (aarch64_default_breakpoint). */
173 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
175 /* Implementation of linux_target_ops method "breakpoint_at". */
178 aarch64_breakpoint_at (CORE_ADDR where
)
180 if (is_64bit_tdesc ())
182 gdb_byte insn
[aarch64_breakpoint_len
];
184 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
185 aarch64_breakpoint_len
);
186 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
192 return arm_breakpoint_at (where
);
196 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
200 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
202 state
->dr_addr_bp
[i
] = 0;
203 state
->dr_ctrl_bp
[i
] = 0;
204 state
->dr_ref_count_bp
[i
] = 0;
207 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
209 state
->dr_addr_wp
[i
] = 0;
210 state
->dr_ctrl_wp
[i
] = 0;
211 state
->dr_ref_count_wp
[i
] = 0;
215 /* Return the pointer to the debug register state structure in the
216 current process' arch-specific data area. */
218 struct aarch64_debug_reg_state
*
219 aarch64_get_debug_reg_state (pid_t pid
)
221 struct process_info
*proc
= find_process_pid (pid
);
223 return &proc
->priv
->arch_private
->debug_reg_state
;
226 /* Implementation of linux_target_ops method "supports_z_point_type". */
229 aarch64_supports_z_point_type (char z_type
)
235 case Z_PACKET_WRITE_WP
:
236 case Z_PACKET_READ_WP
:
237 case Z_PACKET_ACCESS_WP
:
244 /* Implementation of linux_target_ops method "insert_point".
246 It actually only records the info of the to-be-inserted bp/wp;
247 the actual insertion will happen when threads are resumed. */
250 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
251 int len
, struct raw_breakpoint
*bp
)
254 enum target_hw_bp_type targ_type
;
255 struct aarch64_debug_reg_state
*state
256 = aarch64_get_debug_reg_state (pid_of (current_thread
));
259 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
260 (unsigned long) addr
, len
);
262 /* Determine the type from the raw breakpoint type. */
263 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
265 if (targ_type
!= hw_execute
)
267 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
268 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
269 1 /* is_insert */, state
);
277 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
278 instruction. Set it to 2 to correctly encode length bit
279 mask in hardware/watchpoint control register. */
282 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
283 1 /* is_insert */, state
);
287 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
293 /* Implementation of linux_target_ops method "remove_point".
295 It actually only records the info of the to-be-removed bp/wp,
296 the actual removal will be done when threads are resumed. */
299 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
300 int len
, struct raw_breakpoint
*bp
)
303 enum target_hw_bp_type targ_type
;
304 struct aarch64_debug_reg_state
*state
305 = aarch64_get_debug_reg_state (pid_of (current_thread
));
308 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
309 (unsigned long) addr
, len
);
311 /* Determine the type from the raw breakpoint type. */
312 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
314 /* Set up state pointers. */
315 if (targ_type
!= hw_execute
)
317 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
323 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
324 instruction. Set it to 2 to correctly encode length bit
325 mask in hardware/watchpoint control register. */
328 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
329 0 /* is_insert */, state
);
333 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
339 /* Implementation of linux_target_ops method "stopped_data_address". */
342 aarch64_stopped_data_address (void)
346 struct aarch64_debug_reg_state
*state
;
348 pid
= lwpid_of (current_thread
);
350 /* Get the siginfo. */
351 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
352 return (CORE_ADDR
) 0;
354 /* Need to be a hardware breakpoint/watchpoint trap. */
355 if (siginfo
.si_signo
!= SIGTRAP
356 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
357 return (CORE_ADDR
) 0;
359 /* Check if the address matches any watched address. */
360 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
361 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
363 const unsigned int offset
364 = aarch64_watchpoint_offset (state
->dr_ctrl_wp
[i
]);
365 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
366 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
367 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
] + offset
;
368 const CORE_ADDR addr_watch_aligned
= align_down (state
->dr_addr_wp
[i
], 8);
369 const CORE_ADDR addr_orig
= state
->dr_addr_orig_wp
[i
];
371 if (state
->dr_ref_count_wp
[i
]
372 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
373 && addr_trap
>= addr_watch_aligned
374 && addr_trap
< addr_watch
+ len
)
376 /* ADDR_TRAP reports the first address of the memory range
377 accessed by the CPU, regardless of what was the memory
378 range watched. Thus, a large CPU access that straddles
379 the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
380 ADDR_TRAP that is lower than the
381 ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
383 addr: | 4 | 5 | 6 | 7 | 8 |
384 |---- range watched ----|
385 |----------- range accessed ------------|
387 In this case, ADDR_TRAP will be 4.
389 To match a watchpoint known to GDB core, we must never
390 report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
391 range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
392 positive on kernels older than 4.10. See PR
398 return (CORE_ADDR
) 0;
401 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
404 aarch64_stopped_by_watchpoint (void)
406 if (aarch64_stopped_data_address () != 0)
412 /* Fetch the thread-local storage pointer for libthread_db. */
415 ps_get_thread_area (struct ps_prochandle
*ph
,
416 lwpid_t lwpid
, int idx
, void **base
)
418 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
422 /* Implementation of linux_target_ops method "siginfo_fixup". */
425 aarch64_linux_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
, int direction
)
427 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
428 if (!is_64bit_tdesc ())
431 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
434 aarch64_siginfo_from_compat_siginfo (native
,
435 (struct compat_siginfo
*) inf
);
443 /* Implementation of linux_target_ops method "new_process". */
445 static struct arch_process_info
*
446 aarch64_linux_new_process (void)
448 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
450 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
455 /* Implementation of linux_target_ops method "delete_process". */
458 aarch64_linux_delete_process (struct arch_process_info
*info
)
463 /* Implementation of linux_target_ops method "linux_new_fork". */
466 aarch64_linux_new_fork (struct process_info
*parent
,
467 struct process_info
*child
)
469 /* These are allocated by linux_add_process. */
470 gdb_assert (parent
->priv
!= NULL
471 && parent
->priv
->arch_private
!= NULL
);
472 gdb_assert (child
->priv
!= NULL
473 && child
->priv
->arch_private
!= NULL
);
475 /* Linux kernel before 2.6.33 commit
476 72f674d203cd230426437cdcf7dd6f681dad8b0d
477 will inherit hardware debug registers from parent
478 on fork/vfork/clone. Newer Linux kernels create such tasks with
479 zeroed debug registers.
481 GDB core assumes the child inherits the watchpoints/hw
482 breakpoints of the parent, and will remove them all from the
483 forked off process. Copy the debug registers mirrors into the
484 new process so that all breakpoints and watchpoints can be
485 removed together. The debug registers mirror will become zeroed
486 in the end before detaching the forked off process, thus making
487 this compatible with older Linux kernels too. */
489 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
492 /* Implementation of linux_target_ops method "arch_setup". */
495 aarch64_arch_setup (void)
497 unsigned int machine
;
501 tid
= lwpid_of (current_thread
);
503 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
506 current_process ()->tdesc
= aarch64_linux_read_description ();
508 current_process ()->tdesc
= tdesc_arm_with_neon
;
510 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
513 static struct regset_info aarch64_regsets
[] =
515 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
516 sizeof (struct user_pt_regs
), GENERAL_REGS
,
517 aarch64_fill_gregset
, aarch64_store_gregset
},
518 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
519 sizeof (struct user_fpsimd_state
), FP_REGS
,
520 aarch64_fill_fpregset
, aarch64_store_fpregset
525 static struct regsets_info aarch64_regsets_info
=
527 aarch64_regsets
, /* regsets */
529 NULL
, /* disabled_regsets */
532 static struct regs_info regs_info_aarch64
=
534 NULL
, /* regset_bitmap */
536 &aarch64_regsets_info
,
539 /* Implementation of linux_target_ops method "regs_info". */
541 static const struct regs_info
*
542 aarch64_regs_info (void)
544 if (is_64bit_tdesc ())
545 return ®s_info_aarch64
;
547 return ®s_info_aarch32
;
550 /* Implementation of linux_target_ops method "supports_tracepoints". */
553 aarch64_supports_tracepoints (void)
555 if (current_thread
== NULL
)
559 /* We don't support tracepoints on aarch32 now. */
560 return is_64bit_tdesc ();
564 /* Implementation of linux_target_ops method "get_thread_area". */
567 aarch64_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
572 iovec
.iov_base
= ®
;
573 iovec
.iov_len
= sizeof (reg
);
575 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
583 /* Implementation of linux_target_ops method "get_syscall_trapinfo". */
586 aarch64_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
588 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
594 collect_register_by_name (regcache
, "x8", &l_sysno
);
595 *sysno
= (int) l_sysno
;
598 collect_register_by_name (regcache
, "r7", sysno
);
601 /* List of condition codes that we need. */
603 enum aarch64_condition_codes
614 enum aarch64_operand_type
620 /* Representation of an operand. At this time, it only supports register
621 and immediate types. */
623 struct aarch64_operand
625 /* Type of the operand. */
626 enum aarch64_operand_type type
;
628 /* Value of the operand according to the type. */
632 struct aarch64_register reg
;
636 /* List of registers that we are currently using, we can add more here as
637 we need to use them. */
639 /* General purpose scratch registers (64 bit). */
640 static const struct aarch64_register x0
= { 0, 1 };
641 static const struct aarch64_register x1
= { 1, 1 };
642 static const struct aarch64_register x2
= { 2, 1 };
643 static const struct aarch64_register x3
= { 3, 1 };
644 static const struct aarch64_register x4
= { 4, 1 };
646 /* General purpose scratch registers (32 bit). */
647 static const struct aarch64_register w0
= { 0, 0 };
648 static const struct aarch64_register w2
= { 2, 0 };
650 /* Intra-procedure scratch registers. */
651 static const struct aarch64_register ip0
= { 16, 1 };
653 /* Special purpose registers. */
654 static const struct aarch64_register fp
= { 29, 1 };
655 static const struct aarch64_register lr
= { 30, 1 };
656 static const struct aarch64_register sp
= { 31, 1 };
657 static const struct aarch64_register xzr
= { 31, 1 };
659 /* Dynamically allocate a new register. If we know the register
660 statically, we should make it a global as above instead of using this
663 static struct aarch64_register
664 aarch64_register (unsigned num
, int is64
)
666 return (struct aarch64_register
) { num
, is64
};
669 /* Helper function to create a register operand, for instructions with
670 different types of operands.
673 p += emit_mov (p, x0, register_operand (x1)); */
675 static struct aarch64_operand
676 register_operand (struct aarch64_register reg
)
678 struct aarch64_operand operand
;
680 operand
.type
= OPERAND_REGISTER
;
686 /* Helper function to create an immediate operand, for instructions with
687 different types of operands.
690 p += emit_mov (p, x0, immediate_operand (12)); */
692 static struct aarch64_operand
693 immediate_operand (uint32_t imm
)
695 struct aarch64_operand operand
;
697 operand
.type
= OPERAND_IMMEDIATE
;
703 /* Helper function to create an offset memory operand.
706 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
708 static struct aarch64_memory_operand
709 offset_memory_operand (int32_t offset
)
711 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
714 /* Helper function to create a pre-index memory operand.
717 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
719 static struct aarch64_memory_operand
720 preindex_memory_operand (int32_t index
)
722 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
725 /* Helper function to create a post-index memory operand.
728 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
730 static struct aarch64_memory_operand
731 postindex_memory_operand (int32_t index
)
733 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
736 /* System control registers. These special registers can be written and
737 read with the MRS and MSR instructions.
739 - NZCV: Condition flags. GDB refers to this register under the CPSR
741 - FPSR: Floating-point status register.
742 - FPCR: Floating-point control registers.
743 - TPIDR_EL0: Software thread ID register. */
745 enum aarch64_system_control_registers
747 /* op0 op1 crn crm op2 */
748 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
749 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
750 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
751 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
754 /* Write a BLR instruction into *BUF.
758 RN is the register to branch to. */
761 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
763 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
766 /* Write a RET instruction into *BUF.
770 RN is the register to branch to. */
773 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
775 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
779 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
780 struct aarch64_register rt
,
781 struct aarch64_register rt2
,
782 struct aarch64_register rn
,
783 struct aarch64_memory_operand operand
)
790 opc
= ENCODE (2, 2, 30);
792 opc
= ENCODE (0, 2, 30);
794 switch (operand
.type
)
796 case MEMORY_OPERAND_OFFSET
:
798 pre_index
= ENCODE (1, 1, 24);
799 write_back
= ENCODE (0, 1, 23);
802 case MEMORY_OPERAND_POSTINDEX
:
804 pre_index
= ENCODE (0, 1, 24);
805 write_back
= ENCODE (1, 1, 23);
808 case MEMORY_OPERAND_PREINDEX
:
810 pre_index
= ENCODE (1, 1, 24);
811 write_back
= ENCODE (1, 1, 23);
818 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
819 | ENCODE (operand
.index
>> 3, 7, 15)
820 | ENCODE (rt2
.num
, 5, 10)
821 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
824 /* Write a STP instruction into *BUF.
826 STP rt, rt2, [rn, #offset]
827 STP rt, rt2, [rn, #index]!
828 STP rt, rt2, [rn], #index
830 RT and RT2 are the registers to store.
831 RN is the base address register.
832 OFFSET is the immediate to add to the base address. It is limited to a
833 -512 .. 504 range (7 bits << 3). */
836 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
837 struct aarch64_register rt2
, struct aarch64_register rn
,
838 struct aarch64_memory_operand operand
)
840 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
843 /* Write a LDP instruction into *BUF.
845 LDP rt, rt2, [rn, #offset]
846 LDP rt, rt2, [rn, #index]!
847 LDP rt, rt2, [rn], #index
849 RT and RT2 are the registers to store.
850 RN is the base address register.
851 OFFSET is the immediate to add to the base address. It is limited to a
852 -512 .. 504 range (7 bits << 3). */
855 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
856 struct aarch64_register rt2
, struct aarch64_register rn
,
857 struct aarch64_memory_operand operand
)
859 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
862 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
864 LDP qt, qt2, [rn, #offset]
866 RT and RT2 are the Q registers to store.
867 RN is the base address register.
868 OFFSET is the immediate to add to the base address. It is limited to
869 -1024 .. 1008 range (7 bits << 4). */
872 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
873 struct aarch64_register rn
, int32_t offset
)
875 uint32_t opc
= ENCODE (2, 2, 30);
876 uint32_t pre_index
= ENCODE (1, 1, 24);
878 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
879 | ENCODE (offset
>> 4, 7, 15)
880 | ENCODE (rt2
, 5, 10)
881 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
884 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
886 STP qt, qt2, [rn, #offset]
888 RT and RT2 are the Q registers to store.
889 RN is the base address register.
890 OFFSET is the immediate to add to the base address. It is limited to
891 -1024 .. 1008 range (7 bits << 4). */
894 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
895 struct aarch64_register rn
, int32_t offset
)
897 uint32_t opc
= ENCODE (2, 2, 30);
898 uint32_t pre_index
= ENCODE (1, 1, 24);
900 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
901 | ENCODE (offset
>> 4, 7, 15)
902 | ENCODE (rt2
, 5, 10)
903 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
906 /* Write a LDRH instruction into *BUF.
908 LDRH wt, [xn, #offset]
909 LDRH wt, [xn, #index]!
910 LDRH wt, [xn], #index
912 RT is the register to store.
913 RN is the base address register.
914 OFFSET is the immediate to add to the base address. It is limited to
915 0 .. 32760 range (12 bits << 3). */
918 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
919 struct aarch64_register rn
,
920 struct aarch64_memory_operand operand
)
922 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
925 /* Write a LDRB instruction into *BUF.
927 LDRB wt, [xn, #offset]
928 LDRB wt, [xn, #index]!
929 LDRB wt, [xn], #index
931 RT is the register to store.
932 RN is the base address register.
933 OFFSET is the immediate to add to the base address. It is limited to
934 0 .. 32760 range (12 bits << 3). */
937 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
938 struct aarch64_register rn
,
939 struct aarch64_memory_operand operand
)
941 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
946 /* Write a STR instruction into *BUF.
948 STR rt, [rn, #offset]
949 STR rt, [rn, #index]!
952 RT is the register to store.
953 RN is the base address register.
954 OFFSET is the immediate to add to the base address. It is limited to
955 0 .. 32760 range (12 bits << 3). */
958 emit_str (uint32_t *buf
, struct aarch64_register rt
,
959 struct aarch64_register rn
,
960 struct aarch64_memory_operand operand
)
962 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
965 /* Helper function emitting an exclusive load or store instruction. */
968 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
969 enum aarch64_opcodes opcode
,
970 struct aarch64_register rs
,
971 struct aarch64_register rt
,
972 struct aarch64_register rt2
,
973 struct aarch64_register rn
)
975 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
976 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
977 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
980 /* Write a LAXR instruction into *BUF.
984 RT is the destination register.
985 RN is the base address register. */
988 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
989 struct aarch64_register rn
)
991 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
995 /* Write a STXR instruction into *BUF.
999 RS is the result register, it indicates if the store succeeded or not.
1000 RT is the destination register.
1001 RN is the base address register. */
1004 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1005 struct aarch64_register rt
, struct aarch64_register rn
)
1007 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1011 /* Write a STLR instruction into *BUF.
1015 RT is the register to store.
1016 RN is the base address register. */
1019 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1020 struct aarch64_register rn
)
1022 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1026 /* Helper function for data processing instructions with register sources. */
1029 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1030 struct aarch64_register rd
,
1031 struct aarch64_register rn
,
1032 struct aarch64_register rm
)
1034 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1036 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1037 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1040 /* Helper function for data processing instructions taking either a register
1044 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1045 struct aarch64_register rd
,
1046 struct aarch64_register rn
,
1047 struct aarch64_operand operand
)
1049 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1050 /* The opcode is different for register and immediate source operands. */
1051 uint32_t operand_opcode
;
1053 if (operand
.type
== OPERAND_IMMEDIATE
)
1055 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1056 operand_opcode
= ENCODE (8, 4, 25);
1058 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1059 | ENCODE (operand
.imm
, 12, 10)
1060 | ENCODE (rn
.num
, 5, 5)
1061 | ENCODE (rd
.num
, 5, 0));
1065 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1066 operand_opcode
= ENCODE (5, 4, 25);
1068 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1073 /* Write an ADD instruction into *BUF.
1078 This function handles both an immediate and register add.
1080 RD is the destination register.
1081 RN is the input register.
1082 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1083 OPERAND_REGISTER. */
1086 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1087 struct aarch64_register rn
, struct aarch64_operand operand
)
1089 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1092 /* Write a SUB instruction into *BUF.
1097 This function handles both an immediate and register sub.
1099 RD is the destination register.
1100 RN is the input register.
1101 IMM is the immediate to substract to RN. */
1104 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1105 struct aarch64_register rn
, struct aarch64_operand operand
)
1107 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1110 /* Write a MOV instruction into *BUF.
1115 This function handles both a wide immediate move and a register move,
1116 with the condition that the source register is not xzr. xzr and the
1117 stack pointer share the same encoding and this function only supports
1120 RD is the destination register.
1121 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1122 OPERAND_REGISTER. */
1125 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1126 struct aarch64_operand operand
)
1128 if (operand
.type
== OPERAND_IMMEDIATE
)
1130 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1131 /* Do not shift the immediate. */
1132 uint32_t shift
= ENCODE (0, 2, 21);
1134 return aarch64_emit_insn (buf
, MOV
| size
| shift
1135 | ENCODE (operand
.imm
, 16, 5)
1136 | ENCODE (rd
.num
, 5, 0));
1139 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1142 /* Write a MOVK instruction into *BUF.
1144 MOVK rd, #imm, lsl #shift
1146 RD is the destination register.
1147 IMM is the immediate.
1148 SHIFT is the logical shift left to apply to IMM. */
1151 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1154 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1156 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1157 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1160 /* Write instructions into *BUF in order to move ADDR into a register.
1161 ADDR can be a 64-bit value.
1163 This function will emit a series of MOV and MOVK instructions, such as:
1166 MOVK xd, #(addr >> 16), lsl #16
1167 MOVK xd, #(addr >> 32), lsl #32
1168 MOVK xd, #(addr >> 48), lsl #48 */
1171 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1175 /* The MOV (wide immediate) instruction clears to top bits of the
1177 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1179 if ((addr
>> 16) != 0)
1180 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1184 if ((addr
>> 32) != 0)
1185 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1189 if ((addr
>> 48) != 0)
1190 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1195 /* Write a SUBS instruction into *BUF.
1199 This instruction update the condition flags.
1201 RD is the destination register.
1202 RN and RM are the source registers. */
1205 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1206 struct aarch64_register rn
, struct aarch64_operand operand
)
1208 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1211 /* Write a CMP instruction into *BUF.
1215 This instruction is an alias of SUBS xzr, rn, rm.
1217 RN and RM are the registers to compare. */
1220 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1221 struct aarch64_operand operand
)
1223 return emit_subs (buf
, xzr
, rn
, operand
);
1226 /* Write a AND instruction into *BUF.
1230 RD is the destination register.
1231 RN and RM are the source registers. */
1234 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1235 struct aarch64_register rn
, struct aarch64_register rm
)
1237 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1240 /* Write a ORR instruction into *BUF.
1244 RD is the destination register.
1245 RN and RM are the source registers. */
1248 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1249 struct aarch64_register rn
, struct aarch64_register rm
)
1251 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1254 /* Write a ORN instruction into *BUF.
1258 RD is the destination register.
1259 RN and RM are the source registers. */
1262 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1263 struct aarch64_register rn
, struct aarch64_register rm
)
1265 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1268 /* Write a EOR instruction into *BUF.
1272 RD is the destination register.
1273 RN and RM are the source registers. */
1276 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1277 struct aarch64_register rn
, struct aarch64_register rm
)
1279 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1282 /* Write a MVN instruction into *BUF.
1286 This is an alias for ORN rd, xzr, rm.
1288 RD is the destination register.
1289 RM is the source register. */
1292 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1293 struct aarch64_register rm
)
1295 return emit_orn (buf
, rd
, xzr
, rm
);
1298 /* Write a LSLV instruction into *BUF.
1302 RD is the destination register.
1303 RN and RM are the source registers. */
1306 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1307 struct aarch64_register rn
, struct aarch64_register rm
)
1309 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1312 /* Write a LSRV instruction into *BUF.
1316 RD is the destination register.
1317 RN and RM are the source registers. */
1320 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1321 struct aarch64_register rn
, struct aarch64_register rm
)
1323 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1326 /* Write a ASRV instruction into *BUF.
1330 RD is the destination register.
1331 RN and RM are the source registers. */
1334 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1335 struct aarch64_register rn
, struct aarch64_register rm
)
1337 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1340 /* Write a MUL instruction into *BUF.
1344 RD is the destination register.
1345 RN and RM are the source registers. */
1348 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1349 struct aarch64_register rn
, struct aarch64_register rm
)
1351 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1354 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1358 RT is the destination register.
1359 SYSTEM_REG is special purpose register to read. */
1362 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1363 enum aarch64_system_control_registers system_reg
)
1365 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1366 | ENCODE (rt
.num
, 5, 0));
1369 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1373 SYSTEM_REG is special purpose register to write.
1374 RT is the input register. */
1377 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1378 struct aarch64_register rt
)
1380 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1381 | ENCODE (rt
.num
, 5, 0));
1384 /* Write a SEVL instruction into *BUF.
1386 This is a hint instruction telling the hardware to trigger an event. */
1389 emit_sevl (uint32_t *buf
)
1391 return aarch64_emit_insn (buf
, SEVL
);
1394 /* Write a WFE instruction into *BUF.
1396 This is a hint instruction telling the hardware to wait for an event. */
1399 emit_wfe (uint32_t *buf
)
1401 return aarch64_emit_insn (buf
, WFE
);
1404 /* Write a SBFM instruction into *BUF.
1406 SBFM rd, rn, #immr, #imms
1408 This instruction moves the bits from #immr to #imms into the
1409 destination, sign extending the result.
1411 RD is the destination register.
1412 RN is the source register.
1413 IMMR is the bit number to start at (least significant bit).
1414 IMMS is the bit number to stop at (most significant bit). */
1417 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1418 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1420 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1421 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1423 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1424 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1425 | ENCODE (rd
.num
, 5, 0));
1428 /* Write a SBFX instruction into *BUF.
1430 SBFX rd, rn, #lsb, #width
1432 This instruction moves #width bits from #lsb into the destination, sign
1433 extending the result. This is an alias for:
1435 SBFM rd, rn, #lsb, #(lsb + width - 1)
1437 RD is the destination register.
1438 RN is the source register.
1439 LSB is the bit number to start at (least significant bit).
1440 WIDTH is the number of bits to move. */
1443 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1444 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1446 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1449 /* Write a UBFM instruction into *BUF.
1451 UBFM rd, rn, #immr, #imms
1453 This instruction moves the bits from #immr to #imms into the
1454 destination, extending the result with zeros.
1456 RD is the destination register.
1457 RN is the source register.
1458 IMMR is the bit number to start at (least significant bit).
1459 IMMS is the bit number to stop at (most significant bit). */
1462 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1463 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1465 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1466 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1468 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1469 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1470 | ENCODE (rd
.num
, 5, 0));
1473 /* Write a UBFX instruction into *BUF.
1475 UBFX rd, rn, #lsb, #width
1477 This instruction moves #width bits from #lsb into the destination,
1478 extending the result with zeros. This is an alias for:
1480 UBFM rd, rn, #lsb, #(lsb + width - 1)
1482 RD is the destination register.
1483 RN is the source register.
1484 LSB is the bit number to start at (least significant bit).
1485 WIDTH is the number of bits to move. */
1488 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1489 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1491 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1494 /* Write a CSINC instruction into *BUF.
1496 CSINC rd, rn, rm, cond
1498 This instruction conditionally increments rn or rm and places the result
1499 in rd. rn is chosen is the condition is true.
1501 RD is the destination register.
1502 RN and RM are the source registers.
1503 COND is the encoded condition. */
1506 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1507 struct aarch64_register rn
, struct aarch64_register rm
,
1510 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1512 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1513 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1514 | ENCODE (rd
.num
, 5, 0));
1517 /* Write a CSET instruction into *BUF.
1521 This instruction conditionally write 1 or 0 in the destination register.
1522 1 is written if the condition is true. This is an alias for:
1524 CSINC rd, xzr, xzr, !cond
1526 Note that the condition needs to be inverted.
1528 RD is the destination register.
1529 RN and RM are the source registers.
1530 COND is the encoded condition. */
1533 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1535 /* The least significant bit of the condition needs toggling in order to
1537 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1540 /* Write LEN instructions from BUF into the inferior memory at *TO.
1542 Note instructions are always little endian on AArch64, unlike data. */
1545 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1547 size_t byte_len
= len
* sizeof (uint32_t);
1548 #if (__BYTE_ORDER == __BIG_ENDIAN)
1549 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1552 for (i
= 0; i
< len
; i
++)
1553 le_buf
[i
] = htole32 (buf
[i
]);
1555 write_inferior_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1559 write_inferior_memory (*to
, (const unsigned char *) buf
, byte_len
);
1565 /* Sub-class of struct aarch64_insn_data, store information of
1566 instruction relocation for fast tracepoint. Visitor can
1567 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1568 the relocated instructions in buffer pointed by INSN_PTR. */
1570 struct aarch64_insn_relocation_data
1572 struct aarch64_insn_data base
;
1574 /* The new address the instruction is relocated to. */
1576 /* Pointer to the buffer of relocated instruction(s). */
1580 /* Implementation of aarch64_insn_visitor method "b". */
1583 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1584 struct aarch64_insn_data
*data
)
1586 struct aarch64_insn_relocation_data
*insn_reloc
1587 = (struct aarch64_insn_relocation_data
*) data
;
1589 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1591 if (can_encode_int32 (new_offset
, 28))
1592 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1595 /* Implementation of aarch64_insn_visitor method "b_cond". */
1598 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1599 struct aarch64_insn_data
*data
)
1601 struct aarch64_insn_relocation_data
*insn_reloc
1602 = (struct aarch64_insn_relocation_data
*) data
;
1604 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1606 if (can_encode_int32 (new_offset
, 21))
1608 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1611 else if (can_encode_int32 (new_offset
, 28))
1613 /* The offset is out of range for a conditional branch
1614 instruction but not for a unconditional branch. We can use
1615 the following instructions instead:
1617 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1618 B NOT_TAKEN ; Else jump over TAKEN and continue.
1625 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1626 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1627 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1631 /* Implementation of aarch64_insn_visitor method "cb". */
1634 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1635 const unsigned rn
, int is64
,
1636 struct aarch64_insn_data
*data
)
1638 struct aarch64_insn_relocation_data
*insn_reloc
1639 = (struct aarch64_insn_relocation_data
*) data
;
1641 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1643 if (can_encode_int32 (new_offset
, 21))
1645 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1646 aarch64_register (rn
, is64
), new_offset
);
1648 else if (can_encode_int32 (new_offset
, 28))
1650 /* The offset is out of range for a compare and branch
1651 instruction but not for a unconditional branch. We can use
1652 the following instructions instead:
1654 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1655 B NOT_TAKEN ; Else jump over TAKEN and continue.
1661 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1662 aarch64_register (rn
, is64
), 8);
1663 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1664 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1668 /* Implementation of aarch64_insn_visitor method "tb". */
1671 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1672 const unsigned rt
, unsigned bit
,
1673 struct aarch64_insn_data
*data
)
1675 struct aarch64_insn_relocation_data
*insn_reloc
1676 = (struct aarch64_insn_relocation_data
*) data
;
1678 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1680 if (can_encode_int32 (new_offset
, 16))
1682 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1683 aarch64_register (rt
, 1), new_offset
);
1685 else if (can_encode_int32 (new_offset
, 28))
1687 /* The offset is out of range for a test bit and branch
1688 instruction but not for a unconditional branch. We can use
1689 the following instructions instead:
1691 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1692 B NOT_TAKEN ; Else jump over TAKEN and continue.
1698 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1699 aarch64_register (rt
, 1), 8);
1700 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1701 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1706 /* Implementation of aarch64_insn_visitor method "adr". */
1709 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1711 struct aarch64_insn_data
*data
)
1713 struct aarch64_insn_relocation_data
*insn_reloc
1714 = (struct aarch64_insn_relocation_data
*) data
;
1715 /* We know exactly the address the ADR{P,} instruction will compute.
1716 We can just write it to the destination register. */
1717 CORE_ADDR address
= data
->insn_addr
+ offset
;
1721 /* Clear the lower 12 bits of the offset to get the 4K page. */
1722 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1723 aarch64_register (rd
, 1),
1727 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1728 aarch64_register (rd
, 1), address
);
1731 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1734 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
1735 const unsigned rt
, const int is64
,
1736 struct aarch64_insn_data
*data
)
1738 struct aarch64_insn_relocation_data
*insn_reloc
1739 = (struct aarch64_insn_relocation_data
*) data
;
1740 CORE_ADDR address
= data
->insn_addr
+ offset
;
1742 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1743 aarch64_register (rt
, 1), address
);
1745 /* We know exactly what address to load from, and what register we
1748 MOV xd, #(oldloc + offset)
1749 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1752 LDR xd, [xd] ; or LDRSW xd, [xd]
1757 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
1758 aarch64_register (rt
, 1),
1759 aarch64_register (rt
, 1),
1760 offset_memory_operand (0));
1762 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
1763 aarch64_register (rt
, is64
),
1764 aarch64_register (rt
, 1),
1765 offset_memory_operand (0));
1768 /* Implementation of aarch64_insn_visitor method "others". */
1771 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
1772 struct aarch64_insn_data
*data
)
1774 struct aarch64_insn_relocation_data
*insn_reloc
1775 = (struct aarch64_insn_relocation_data
*) data
;
1777 /* The instruction is not PC relative. Just re-emit it at the new
1779 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
1782 static const struct aarch64_insn_visitor visitor
=
1784 aarch64_ftrace_insn_reloc_b
,
1785 aarch64_ftrace_insn_reloc_b_cond
,
1786 aarch64_ftrace_insn_reloc_cb
,
1787 aarch64_ftrace_insn_reloc_tb
,
1788 aarch64_ftrace_insn_reloc_adr
,
1789 aarch64_ftrace_insn_reloc_ldr_literal
,
1790 aarch64_ftrace_insn_reloc_others
,
1793 /* Implementation of linux_target_ops method
1794 "install_fast_tracepoint_jump_pad". */
1797 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1799 CORE_ADDR collector
,
1802 CORE_ADDR
*jump_entry
,
1803 CORE_ADDR
*trampoline
,
1804 ULONGEST
*trampoline_size
,
1805 unsigned char *jjump_pad_insn
,
1806 ULONGEST
*jjump_pad_insn_size
,
1807 CORE_ADDR
*adjusted_insn_addr
,
1808 CORE_ADDR
*adjusted_insn_addr_end
,
1816 CORE_ADDR buildaddr
= *jump_entry
;
1817 struct aarch64_insn_relocation_data insn_data
;
1819 /* We need to save the current state on the stack both to restore it
1820 later and to collect register values when the tracepoint is hit.
1822 The saved registers are pushed in a layout that needs to be in sync
1823 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
1824 the supply_fast_tracepoint_registers function will fill in the
1825 register cache from a pointer to saved registers on the stack we build
1828 For simplicity, we set the size of each cell on the stack to 16 bytes.
1829 This way one cell can hold any register type, from system registers
1830 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
1831 has to be 16 bytes aligned anyway.
1833 Note that the CPSR register does not exist on AArch64. Instead we
1834 can access system bits describing the process state with the
1835 MRS/MSR instructions, namely the condition flags. We save them as
1836 if they are part of a CPSR register because that's how GDB
1837 interprets these system bits. At the moment, only the condition
1838 flags are saved in CPSR (NZCV).
1840 Stack layout, each cell is 16 bytes (descending):
1842 High *-------- SIMD&FP registers from 31 down to 0. --------*
1848 *---- General purpose registers from 30 down to 0. ----*
1854 *------------- Special purpose registers. -------------*
1857 | CPSR (NZCV) | 5 cells
1860 *------------- collecting_t object --------------------*
1861 | TPIDR_EL0 | struct tracepoint * |
1862 Low *------------------------------------------------------*
1864 After this stack is set up, we issue a call to the collector, passing
1865 it the saved registers at (SP + 16). */
1867 /* Push SIMD&FP registers on the stack:
1869 SUB sp, sp, #(32 * 16)
1871 STP q30, q31, [sp, #(30 * 16)]
1876 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
1877 for (i
= 30; i
>= 0; i
-= 2)
1878 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
1880 /* Push general puspose registers on the stack. Note that we do not need
1881 to push x31 as it represents the xzr register and not the stack
1882 pointer in a STR instruction.
1884 SUB sp, sp, #(31 * 16)
1886 STR x30, [sp, #(30 * 16)]
1891 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
1892 for (i
= 30; i
>= 0; i
-= 1)
1893 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
1894 offset_memory_operand (i
* 16));
1896 /* Make space for 5 more cells.
1898 SUB sp, sp, #(5 * 16)
1901 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
1906 ADD x4, sp, #((32 + 31 + 5) * 16)
1907 STR x4, [sp, #(4 * 16)]
1910 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
1911 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
1913 /* Save PC (tracepoint address):
1918 STR x3, [sp, #(3 * 16)]
1922 p
+= emit_mov_addr (p
, x3
, tpaddr
);
1923 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
1925 /* Save CPSR (NZCV), FPSR and FPCR:
1931 STR x2, [sp, #(2 * 16)]
1932 STR x1, [sp, #(1 * 16)]
1933 STR x0, [sp, #(0 * 16)]
1936 p
+= emit_mrs (p
, x2
, NZCV
);
1937 p
+= emit_mrs (p
, x1
, FPSR
);
1938 p
+= emit_mrs (p
, x0
, FPCR
);
1939 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
1940 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
1941 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
1943 /* Push the collecting_t object. It consist of the address of the
1944 tracepoint and an ID for the current thread. We get the latter by
1945 reading the tpidr_el0 system register. It corresponds to the
1946 NT_ARM_TLS register accessible with ptrace.
1953 STP x0, x1, [sp, #-16]!
1957 p
+= emit_mov_addr (p
, x0
, tpoint
);
1958 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
1959 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
1963 The shared memory for the lock is at lockaddr. It will hold zero
1964 if no-one is holding the lock, otherwise it contains the address of
1965 the collecting_t object on the stack of the thread which acquired it.
1967 At this stage, the stack pointer points to this thread's collecting_t
1970 We use the following registers:
1971 - x0: Address of the lock.
1972 - x1: Pointer to collecting_t object.
1973 - x2: Scratch register.
1979 ; Trigger an event local to this core. So the following WFE
1980 ; instruction is ignored.
1983 ; Wait for an event. The event is triggered by either the SEVL
1984 ; or STLR instructions (store release).
1987 ; Atomically read at lockaddr. This marks the memory location as
1988 ; exclusive. This instruction also has memory constraints which
1989 ; make sure all previous data reads and writes are done before
1993 ; Try again if another thread holds the lock.
1996 ; We can lock it! Write the address of the collecting_t object.
1997 ; This instruction will fail if the memory location is not marked
1998 ; as exclusive anymore. If it succeeds, it will remove the
1999 ; exclusive mark on the memory location. This way, if another
2000 ; thread executes this instruction before us, we will fail and try
2007 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2008 p
+= emit_mov (p
, x1
, register_operand (sp
));
2012 p
+= emit_ldaxr (p
, x2
, x0
);
2013 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2014 p
+= emit_stxr (p
, w2
, x1
, x0
);
2015 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2017 /* Call collector (struct tracepoint *, unsigned char *):
2022 ; Saved registers start after the collecting_t object.
2025 ; We use an intra-procedure-call scratch register.
2026 MOV ip0, #(collector)
2029 ; And call back to C!
2034 p
+= emit_mov_addr (p
, x0
, tpoint
);
2035 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2037 p
+= emit_mov_addr (p
, ip0
, collector
);
2038 p
+= emit_blr (p
, ip0
);
2040 /* Release the lock.
2045 ; This instruction is a normal store with memory ordering
2046 ; constraints. Thanks to this we do not have to put a data
2047 ; barrier instruction to make sure all data read and writes are done
2048 ; before this instruction is executed. Furthermore, this instrucion
2049 ; will trigger an event, letting other threads know they can grab
2054 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2055 p
+= emit_stlr (p
, xzr
, x0
);
2057 /* Free collecting_t object:
2062 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2064 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2065 registers from the stack.
2067 LDR x2, [sp, #(2 * 16)]
2068 LDR x1, [sp, #(1 * 16)]
2069 LDR x0, [sp, #(0 * 16)]
2075 ADD sp, sp #(5 * 16)
2078 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2079 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2080 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2081 p
+= emit_msr (p
, NZCV
, x2
);
2082 p
+= emit_msr (p
, FPSR
, x1
);
2083 p
+= emit_msr (p
, FPCR
, x0
);
2085 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2087 /* Pop general purpose registers:
2091 LDR x30, [sp, #(30 * 16)]
2093 ADD sp, sp, #(31 * 16)
2096 for (i
= 0; i
<= 30; i
+= 1)
2097 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2098 offset_memory_operand (i
* 16));
2099 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2101 /* Pop SIMD&FP registers:
2105 LDP q30, q31, [sp, #(30 * 16)]
2107 ADD sp, sp, #(32 * 16)
2110 for (i
= 0; i
<= 30; i
+= 2)
2111 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2112 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2114 /* Write the code into the inferior memory. */
2115 append_insns (&buildaddr
, p
- buf
, buf
);
2117 /* Now emit the relocated instruction. */
2118 *adjusted_insn_addr
= buildaddr
;
2119 target_read_uint32 (tpaddr
, &insn
);
2121 insn_data
.base
.insn_addr
= tpaddr
;
2122 insn_data
.new_addr
= buildaddr
;
2123 insn_data
.insn_ptr
= buf
;
2125 aarch64_relocate_instruction (insn
, &visitor
,
2126 (struct aarch64_insn_data
*) &insn_data
);
2128 /* We may not have been able to relocate the instruction. */
2129 if (insn_data
.insn_ptr
== buf
)
2132 "E.Could not relocate instruction from %s to %s.",
2133 core_addr_to_string_nz (tpaddr
),
2134 core_addr_to_string_nz (buildaddr
));
2138 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2139 *adjusted_insn_addr_end
= buildaddr
;
2141 /* Go back to the start of the buffer. */
2144 /* Emit a branch back from the jump pad. */
2145 offset
= (tpaddr
+ orig_size
- buildaddr
);
2146 if (!can_encode_int32 (offset
, 28))
2149 "E.Jump back from jump pad too far from tracepoint "
2150 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2155 p
+= emit_b (p
, 0, offset
);
2156 append_insns (&buildaddr
, p
- buf
, buf
);
2158 /* Give the caller a branch instruction into the jump pad. */
2159 offset
= (*jump_entry
- tpaddr
);
2160 if (!can_encode_int32 (offset
, 28))
2163 "E.Jump pad too far from tracepoint "
2164 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2169 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2170 *jjump_pad_insn_size
= 4;
2172 /* Return the end address of our pad. */
2173 *jump_entry
= buildaddr
;
2178 /* Helper function writing LEN instructions from START into
2179 current_insn_ptr. */
2182 emit_ops_insns (const uint32_t *start
, int len
)
2184 CORE_ADDR buildaddr
= current_insn_ptr
;
2187 debug_printf ("Adding %d instrucions at %s\n",
2188 len
, paddress (buildaddr
));
2190 append_insns (&buildaddr
, len
, start
);
2191 current_insn_ptr
= buildaddr
;
2194 /* Pop a register from the stack. */
2197 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2199 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2202 /* Push a register on the stack. */
2205 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2207 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2210 /* Implementation of emit_ops method "emit_prologue". */
2213 aarch64_emit_prologue (void)
2218 /* This function emit a prologue for the following function prototype:
2220 enum eval_result_type f (unsigned char *regs,
2223 The first argument is a buffer of raw registers. The second
2224 argument is the result of
2225 evaluating the expression, which will be set to whatever is on top of
2226 the stack at the end.
2228 The stack set up by the prologue is as such:
2230 High *------------------------------------------------------*
2233 | x1 (ULONGEST *value) |
2234 | x0 (unsigned char *regs) |
2235 Low *------------------------------------------------------*
2237 As we are implementing a stack machine, each opcode can expand the
2238 stack so we never know how far we are from the data saved by this
2239 prologue. In order to be able refer to value and regs later, we save
2240 the current stack pointer in the frame pointer. This way, it is not
2241 clobbered when calling C functions.
2243 Finally, throughtout every operation, we are using register x0 as the
2244 top of the stack, and x1 as a scratch register. */
2246 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2247 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2248 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2250 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2253 emit_ops_insns (buf
, p
- buf
);
2256 /* Implementation of emit_ops method "emit_epilogue". */
2259 aarch64_emit_epilogue (void)
2264 /* Store the result of the expression (x0) in *value. */
2265 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2266 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2267 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2269 /* Restore the previous state. */
2270 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2271 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2273 /* Return expr_eval_no_error. */
2274 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2275 p
+= emit_ret (p
, lr
);
2277 emit_ops_insns (buf
, p
- buf
);
2280 /* Implementation of emit_ops method "emit_add". */
2283 aarch64_emit_add (void)
2288 p
+= emit_pop (p
, x1
);
2289 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2291 emit_ops_insns (buf
, p
- buf
);
2294 /* Implementation of emit_ops method "emit_sub". */
2297 aarch64_emit_sub (void)
2302 p
+= emit_pop (p
, x1
);
2303 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2305 emit_ops_insns (buf
, p
- buf
);
2308 /* Implementation of emit_ops method "emit_mul". */
2311 aarch64_emit_mul (void)
2316 p
+= emit_pop (p
, x1
);
2317 p
+= emit_mul (p
, x0
, x1
, x0
);
2319 emit_ops_insns (buf
, p
- buf
);
2322 /* Implementation of emit_ops method "emit_lsh". */
2325 aarch64_emit_lsh (void)
2330 p
+= emit_pop (p
, x1
);
2331 p
+= emit_lslv (p
, x0
, x1
, x0
);
2333 emit_ops_insns (buf
, p
- buf
);
2336 /* Implementation of emit_ops method "emit_rsh_signed". */
2339 aarch64_emit_rsh_signed (void)
2344 p
+= emit_pop (p
, x1
);
2345 p
+= emit_asrv (p
, x0
, x1
, x0
);
2347 emit_ops_insns (buf
, p
- buf
);
2350 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2353 aarch64_emit_rsh_unsigned (void)
2358 p
+= emit_pop (p
, x1
);
2359 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2361 emit_ops_insns (buf
, p
- buf
);
2364 /* Implementation of emit_ops method "emit_ext". */
2367 aarch64_emit_ext (int arg
)
2372 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2374 emit_ops_insns (buf
, p
- buf
);
2377 /* Implementation of emit_ops method "emit_log_not". */
2380 aarch64_emit_log_not (void)
2385 /* If the top of the stack is 0, replace it with 1. Else replace it with
2388 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2389 p
+= emit_cset (p
, x0
, EQ
);
2391 emit_ops_insns (buf
, p
- buf
);
2394 /* Implementation of emit_ops method "emit_bit_and". */
2397 aarch64_emit_bit_and (void)
2402 p
+= emit_pop (p
, x1
);
2403 p
+= emit_and (p
, x0
, x0
, x1
);
2405 emit_ops_insns (buf
, p
- buf
);
2408 /* Implementation of emit_ops method "emit_bit_or". */
2411 aarch64_emit_bit_or (void)
2416 p
+= emit_pop (p
, x1
);
2417 p
+= emit_orr (p
, x0
, x0
, x1
);
2419 emit_ops_insns (buf
, p
- buf
);
2422 /* Implementation of emit_ops method "emit_bit_xor". */
2425 aarch64_emit_bit_xor (void)
2430 p
+= emit_pop (p
, x1
);
2431 p
+= emit_eor (p
, x0
, x0
, x1
);
2433 emit_ops_insns (buf
, p
- buf
);
2436 /* Implementation of emit_ops method "emit_bit_not". */
2439 aarch64_emit_bit_not (void)
2444 p
+= emit_mvn (p
, x0
, x0
);
2446 emit_ops_insns (buf
, p
- buf
);
2449 /* Implementation of emit_ops method "emit_equal". */
2452 aarch64_emit_equal (void)
2457 p
+= emit_pop (p
, x1
);
2458 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2459 p
+= emit_cset (p
, x0
, EQ
);
2461 emit_ops_insns (buf
, p
- buf
);
2464 /* Implementation of emit_ops method "emit_less_signed". */
2467 aarch64_emit_less_signed (void)
2472 p
+= emit_pop (p
, x1
);
2473 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2474 p
+= emit_cset (p
, x0
, LT
);
2476 emit_ops_insns (buf
, p
- buf
);
2479 /* Implementation of emit_ops method "emit_less_unsigned". */
2482 aarch64_emit_less_unsigned (void)
2487 p
+= emit_pop (p
, x1
);
2488 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2489 p
+= emit_cset (p
, x0
, LO
);
2491 emit_ops_insns (buf
, p
- buf
);
2494 /* Implementation of emit_ops method "emit_ref". */
2497 aarch64_emit_ref (int size
)
2505 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2508 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2511 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2514 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2517 /* Unknown size, bail on compilation. */
2522 emit_ops_insns (buf
, p
- buf
);
2525 /* Implementation of emit_ops method "emit_if_goto". */
2528 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2533 /* The Z flag is set or cleared here. */
2534 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2535 /* This instruction must not change the Z flag. */
2536 p
+= emit_pop (p
, x0
);
2537 /* Branch over the next instruction if x0 == 0. */
2538 p
+= emit_bcond (p
, EQ
, 8);
2540 /* The NOP instruction will be patched with an unconditional branch. */
2542 *offset_p
= (p
- buf
) * 4;
2547 emit_ops_insns (buf
, p
- buf
);
2550 /* Implementation of emit_ops method "emit_goto". */
2553 aarch64_emit_goto (int *offset_p
, int *size_p
)
2558 /* The NOP instruction will be patched with an unconditional branch. */
2565 emit_ops_insns (buf
, p
- buf
);
2568 /* Implementation of emit_ops method "write_goto_address". */
2571 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2575 emit_b (&insn
, 0, to
- from
);
2576 append_insns (&from
, 1, &insn
);
2579 /* Implementation of emit_ops method "emit_const". */
2582 aarch64_emit_const (LONGEST num
)
2587 p
+= emit_mov_addr (p
, x0
, num
);
2589 emit_ops_insns (buf
, p
- buf
);
2592 /* Implementation of emit_ops method "emit_call". */
2595 aarch64_emit_call (CORE_ADDR fn
)
2600 p
+= emit_mov_addr (p
, ip0
, fn
);
2601 p
+= emit_blr (p
, ip0
);
2603 emit_ops_insns (buf
, p
- buf
);
2606 /* Implementation of emit_ops method "emit_reg". */
2609 aarch64_emit_reg (int reg
)
2614 /* Set x0 to unsigned char *regs. */
2615 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2616 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2617 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2619 emit_ops_insns (buf
, p
- buf
);
2621 aarch64_emit_call (get_raw_reg_func_addr ());
2624 /* Implementation of emit_ops method "emit_pop". */
2627 aarch64_emit_pop (void)
2632 p
+= emit_pop (p
, x0
);
2634 emit_ops_insns (buf
, p
- buf
);
2637 /* Implementation of emit_ops method "emit_stack_flush". */
2640 aarch64_emit_stack_flush (void)
2645 p
+= emit_push (p
, x0
);
2647 emit_ops_insns (buf
, p
- buf
);
2650 /* Implementation of emit_ops method "emit_zero_ext". */
2653 aarch64_emit_zero_ext (int arg
)
2658 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2660 emit_ops_insns (buf
, p
- buf
);
2663 /* Implementation of emit_ops method "emit_swap". */
2666 aarch64_emit_swap (void)
2671 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2672 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2673 p
+= emit_mov (p
, x0
, register_operand (x1
));
2675 emit_ops_insns (buf
, p
- buf
);
2678 /* Implementation of emit_ops method "emit_stack_adjust". */
2681 aarch64_emit_stack_adjust (int n
)
2683 /* This is not needed with our design. */
2687 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2689 emit_ops_insns (buf
, p
- buf
);
2692 /* Implementation of emit_ops method "emit_int_call_1". */
2695 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2700 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2702 emit_ops_insns (buf
, p
- buf
);
2704 aarch64_emit_call (fn
);
2707 /* Implementation of emit_ops method "emit_void_call_2". */
2710 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2715 /* Push x0 on the stack. */
2716 aarch64_emit_stack_flush ();
2718 /* Setup arguments for the function call:
2721 x1: top of the stack
2726 p
+= emit_mov (p
, x1
, register_operand (x0
));
2727 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2729 emit_ops_insns (buf
, p
- buf
);
2731 aarch64_emit_call (fn
);
2734 aarch64_emit_pop ();
2737 /* Implementation of emit_ops method "emit_eq_goto". */
2740 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
2745 p
+= emit_pop (p
, x1
);
2746 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2747 /* Branch over the next instruction if x0 != x1. */
2748 p
+= emit_bcond (p
, NE
, 8);
2749 /* The NOP instruction will be patched with an unconditional branch. */
2751 *offset_p
= (p
- buf
) * 4;
2756 emit_ops_insns (buf
, p
- buf
);
2759 /* Implementation of emit_ops method "emit_ne_goto". */
2762 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
2767 p
+= emit_pop (p
, x1
);
2768 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2769 /* Branch over the next instruction if x0 == x1. */
2770 p
+= emit_bcond (p
, EQ
, 8);
2771 /* The NOP instruction will be patched with an unconditional branch. */
2773 *offset_p
= (p
- buf
) * 4;
2778 emit_ops_insns (buf
, p
- buf
);
2781 /* Implementation of emit_ops method "emit_lt_goto". */
2784 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
2789 p
+= emit_pop (p
, x1
);
2790 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2791 /* Branch over the next instruction if x0 >= x1. */
2792 p
+= emit_bcond (p
, GE
, 8);
2793 /* The NOP instruction will be patched with an unconditional branch. */
2795 *offset_p
= (p
- buf
) * 4;
2800 emit_ops_insns (buf
, p
- buf
);
2803 /* Implementation of emit_ops method "emit_le_goto". */
2806 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
2811 p
+= emit_pop (p
, x1
);
2812 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2813 /* Branch over the next instruction if x0 > x1. */
2814 p
+= emit_bcond (p
, GT
, 8);
2815 /* The NOP instruction will be patched with an unconditional branch. */
2817 *offset_p
= (p
- buf
) * 4;
2822 emit_ops_insns (buf
, p
- buf
);
2825 /* Implementation of emit_ops method "emit_gt_goto". */
2828 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
2833 p
+= emit_pop (p
, x1
);
2834 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2835 /* Branch over the next instruction if x0 <= x1. */
2836 p
+= emit_bcond (p
, LE
, 8);
2837 /* The NOP instruction will be patched with an unconditional branch. */
2839 *offset_p
= (p
- buf
) * 4;
2844 emit_ops_insns (buf
, p
- buf
);
2847 /* Implementation of emit_ops method "emit_ge_got". */
2850 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
2855 p
+= emit_pop (p
, x1
);
2856 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2857 /* Branch over the next instruction if x0 <= x1. */
2858 p
+= emit_bcond (p
, LT
, 8);
2859 /* The NOP instruction will be patched with an unconditional branch. */
2861 *offset_p
= (p
- buf
) * 4;
2866 emit_ops_insns (buf
, p
- buf
);
2869 static struct emit_ops aarch64_emit_ops_impl
=
2871 aarch64_emit_prologue
,
2872 aarch64_emit_epilogue
,
2877 aarch64_emit_rsh_signed
,
2878 aarch64_emit_rsh_unsigned
,
2880 aarch64_emit_log_not
,
2881 aarch64_emit_bit_and
,
2882 aarch64_emit_bit_or
,
2883 aarch64_emit_bit_xor
,
2884 aarch64_emit_bit_not
,
2886 aarch64_emit_less_signed
,
2887 aarch64_emit_less_unsigned
,
2889 aarch64_emit_if_goto
,
2891 aarch64_write_goto_address
,
2896 aarch64_emit_stack_flush
,
2897 aarch64_emit_zero_ext
,
2899 aarch64_emit_stack_adjust
,
2900 aarch64_emit_int_call_1
,
2901 aarch64_emit_void_call_2
,
2902 aarch64_emit_eq_goto
,
2903 aarch64_emit_ne_goto
,
2904 aarch64_emit_lt_goto
,
2905 aarch64_emit_le_goto
,
2906 aarch64_emit_gt_goto
,
2907 aarch64_emit_ge_got
,
2910 /* Implementation of linux_target_ops method "emit_ops". */
2912 static struct emit_ops
*
2913 aarch64_emit_ops (void)
2915 return &aarch64_emit_ops_impl
;
2918 /* Implementation of linux_target_ops method
2919 "get_min_fast_tracepoint_insn_len". */
2922 aarch64_get_min_fast_tracepoint_insn_len (void)
2927 /* Implementation of linux_target_ops method "supports_range_stepping". */
2930 aarch64_supports_range_stepping (void)
2935 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2937 static const gdb_byte
*
2938 aarch64_sw_breakpoint_from_kind (int kind
, int *size
)
2940 if (is_64bit_tdesc ())
2942 *size
= aarch64_breakpoint_len
;
2943 return aarch64_breakpoint
;
2946 return arm_sw_breakpoint_from_kind (kind
, size
);
2949 /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */
2952 aarch64_breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
2954 if (is_64bit_tdesc ())
2955 return aarch64_breakpoint_len
;
2957 return arm_breakpoint_kind_from_pc (pcptr
);
2960 /* Implementation of the linux_target_ops method
2961 "breakpoint_kind_from_current_state". */
2964 aarch64_breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
2966 if (is_64bit_tdesc ())
2967 return aarch64_breakpoint_len
;
2969 return arm_breakpoint_kind_from_current_state (pcptr
);
2972 /* Support for hardware single step. */
2975 aarch64_supports_hardware_single_step (void)
2980 struct linux_target_ops the_low_target
=
2984 aarch64_cannot_fetch_register
,
2985 aarch64_cannot_store_register
,
2986 NULL
, /* fetch_register */
2989 aarch64_breakpoint_kind_from_pc
,
2990 aarch64_sw_breakpoint_from_kind
,
2991 NULL
, /* get_next_pcs */
2992 0, /* decr_pc_after_break */
2993 aarch64_breakpoint_at
,
2994 aarch64_supports_z_point_type
,
2995 aarch64_insert_point
,
2996 aarch64_remove_point
,
2997 aarch64_stopped_by_watchpoint
,
2998 aarch64_stopped_data_address
,
2999 NULL
, /* collect_ptrace_register */
3000 NULL
, /* supply_ptrace_register */
3001 aarch64_linux_siginfo_fixup
,
3002 aarch64_linux_new_process
,
3003 aarch64_linux_delete_process
,
3004 aarch64_linux_new_thread
,
3005 aarch64_linux_delete_thread
,
3006 aarch64_linux_new_fork
,
3007 aarch64_linux_prepare_to_resume
,
3008 NULL
, /* process_qsupported */
3009 aarch64_supports_tracepoints
,
3010 aarch64_get_thread_area
,
3011 aarch64_install_fast_tracepoint_jump_pad
,
3013 aarch64_get_min_fast_tracepoint_insn_len
,
3014 aarch64_supports_range_stepping
,
3015 aarch64_breakpoint_kind_from_current_state
,
3016 aarch64_supports_hardware_single_step
,
3017 aarch64_get_syscall_trapinfo
,
3021 initialize_low_arch (void)
3023 initialize_low_arch_aarch32 ();
3025 initialize_regsets_info (&aarch64_regsets_info
);
3028 initialize_low_tdesc ();