1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
31 #include "gdb_proc_service.h"
33 /* Defined in auto-generated files. */
34 void init_registers_aarch64 (void);
35 extern const struct target_desc
*tdesc_aarch64
;
41 #define AARCH64_X_REGS_NUM 31
42 #define AARCH64_V_REGS_NUM 32
43 #define AARCH64_X0_REGNO 0
44 #define AARCH64_SP_REGNO 31
45 #define AARCH64_PC_REGNO 32
46 #define AARCH64_CPSR_REGNO 33
47 #define AARCH64_V0_REGNO 34
49 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
54 /* These offsets correspond to GET/SETREGSET */
56 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
57 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
58 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
59 24*8, 25*8, 26*8, 27*8, 28*8,
64 33*8, /* cpsr 4 bytes!*/
66 /* FP register offsets correspond to GET/SETFPREGSET */
67 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
68 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
69 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
70 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
73 /* Here starts the macro definitions, data structures, and code for
74 the hardware breakpoint and hardware watchpoint support. The
75 following is the abbreviations that are used frequently in the code
82 /* Maximum number of hardware breakpoint and watchpoint registers.
83 Neither of these values may exceed the width of dr_changed_t
86 #define AARCH64_HBP_MAX_NUM 16
87 #define AARCH64_HWP_MAX_NUM 16
89 /* Alignment requirement in bytes of hardware breakpoint and
90 watchpoint address. This is the requirement for the addresses that
91 can be written to the hardware breakpoint/watchpoint value
92 registers. The kernel currently does not do any alignment on
93 addresses when receiving a writing request (via ptrace call) to
94 these debug registers, and it will reject any address that is
96 Some limited support has been provided in this gdbserver port for
97 unaligned watchpoints, so that from a gdb user point of view, an
98 unaligned watchpoint can still be set. This is achieved by
99 minimally enlarging the watched area to meet the alignment
100 requirement, and if necessary, splitting the watchpoint over
101 several hardware watchpoint registers. */
103 #define AARCH64_HBP_ALIGNMENT 4
104 #define AARCH64_HWP_ALIGNMENT 8
106 /* The maximum length of a memory region that can be watched by one
107 hardware watchpoint register. */
109 #define AARCH64_HWP_MAX_LEN_PER_REG 8
111 /* Each bit of a variable of this type is used to indicate whether a
112 hardware breakpoint or watchpoint setting has been changed since
113 the last updating. Bit N corresponds to the Nth hardware
114 breakpoint or watchpoint setting which is managed in
115 aarch64_debug_reg_state. Where N is valid between 0 and the total
116 number of the hardware breakpoint or watchpoint debug registers
117 minus 1. When the bit N is 1, it indicates the corresponding
118 breakpoint or watchpoint setting is changed, and thus the
119 corresponding hardware debug register needs to be updated via the
122 In the per-thread arch-specific data area, we define two such
123 variables for per-thread hardware breakpoint and watchpoint
124 settings respectively.
126 This type is part of the mechanism which helps reduce the number of
127 ptrace calls to the kernel, i.e. avoid asking the kernel to write
128 to the debug registers with unchanged values. */
130 typedef unsigned long long dr_changed_t
;
132 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
134 #define DR_MARK_ALL_CHANGED(x, m) \
137 gdb_assert (sizeof ((x)) * 8 >= (m)); \
138 (x) = (((dr_changed_t)1 << (m)) - 1); \
141 #define DR_MARK_N_CHANGED(x, n) \
144 (x) |= ((dr_changed_t)1 << (n)); \
147 #define DR_CLEAR_CHANGED(x) \
153 #define DR_HAS_CHANGED(x) ((x) != 0)
154 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
156 /* Structure for managing the hardware breakpoint/watchpoint resources.
157 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
158 content, and DR_REF_COUNT_* counts the numbers of references to the
159 corresponding bp/wp, by which way the limited hardware resources
160 are not wasted on duplicated bp/wp settings (though so far gdb has
161 done a good job by not sending duplicated bp/wp requests). */
163 struct aarch64_debug_reg_state
165 /* hardware breakpoint */
166 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
167 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
168 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
170 /* hardware watchpoint */
171 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
172 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
173 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
176 /* Per-process arch-specific data we want to keep. */
178 struct arch_process_info
180 /* Hardware breakpoint/watchpoint data.
181 The reason for them to be per-process rather than per-thread is
182 due to the lack of information in the gdbserver environment;
183 gdbserver is not told that whether a requested hardware
184 breakpoint/watchpoint is thread specific or not, so it has to set
185 each hw bp/wp for every thread in the current process. The
186 higher level bp/wp management in gdb will resume a thread if a hw
187 bp/wp trap is not expected for it. Since the hw bp/wp setting is
188 same for each thread, it is reasonable for the data to live here.
190 struct aarch64_debug_reg_state debug_reg_state
;
193 /* Per-thread arch-specific data we want to keep. */
197 /* When bit N is 1, it indicates the Nth hardware breakpoint or
198 watchpoint register pair needs to be updated when the thread is
199 resumed; see aarch64_linux_prepare_to_resume. */
200 dr_changed_t dr_changed_bp
;
201 dr_changed_t dr_changed_wp
;
204 /* Number of hardware breakpoints/watchpoints the target supports.
205 They are initialized with values obtained via the ptrace calls
206 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
208 static int aarch64_num_bp_regs
;
209 static int aarch64_num_wp_regs
;
211 /* Hardware breakpoint/watchpoint types.
212 The values map to their encodings in the bit 4 and bit 3 of the
213 hardware breakpoint/watchpoint control registers. */
215 enum target_point_type
217 hw_execute
= 0, /* Execute HW breakpoint */
218 hw_read
= 1, /* Read HW watchpoint */
219 hw_write
= 2, /* Common HW watchpoint */
220 hw_access
= 3, /* Access HW watchpoint */
221 point_type_unsupported
224 #define Z_PACKET_SW_BP '0'
225 #define Z_PACKET_HW_BP '1'
226 #define Z_PACKET_WRITE_WP '2'
227 #define Z_PACKET_READ_WP '3'
228 #define Z_PACKET_ACCESS_WP '4'
230 /* Map the protocol breakpoint/watchpoint type TYPE to
231 enum target_point_type. */
233 static enum target_point_type
234 Z_packet_to_point_type (char type
)
239 /* Leave the handling of the sw breakpoint with the gdb client. */
240 return point_type_unsupported
;
243 case Z_PACKET_WRITE_WP
:
245 case Z_PACKET_READ_WP
:
247 case Z_PACKET_ACCESS_WP
:
250 return point_type_unsupported
;
255 aarch64_cannot_store_register (int regno
)
257 return regno
>= AARCH64_NUM_REGS
;
261 aarch64_cannot_fetch_register (int regno
)
263 return regno
>= AARCH64_NUM_REGS
;
267 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
269 struct user_pt_regs
*regset
= buf
;
272 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
273 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
274 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
275 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
276 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
280 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
282 const struct user_pt_regs
*regset
= buf
;
285 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
286 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
287 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
288 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
289 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
293 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
295 struct user_fpsimd_state
*regset
= buf
;
298 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
299 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
303 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
305 const struct user_fpsimd_state
*regset
= buf
;
308 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
309 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
312 /* Debugging of hardware breakpoint/watchpoint support. */
313 extern int debug_hw_points
;
315 /* Enable miscellaneous debugging output. The name is historical - it
316 was originally used to debug LinuxThreads support. */
317 extern int debug_threads
;
320 aarch64_get_pc (struct regcache
*regcache
)
324 collect_register_by_name (regcache
, "pc", &pc
);
326 debug_printf ("stop pc is %08lx\n", pc
);
331 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
333 unsigned long newpc
= pc
;
334 supply_register_by_name (regcache
, "pc", &newpc
);
337 /* Correct in either endianness. */
339 #define aarch64_breakpoint_len 4
341 static const unsigned long aarch64_breakpoint
= 0x00800011;
344 aarch64_breakpoint_at (CORE_ADDR where
)
348 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
349 if (insn
== aarch64_breakpoint
)
355 /* Print the values of the cached breakpoint/watchpoint registers.
356 This is enabled via the "set debug-hw-points" monitor command. */
359 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
360 const char *func
, CORE_ADDR addr
,
361 int len
, enum target_point_type type
)
365 fprintf (stderr
, "%s", func
);
367 fprintf (stderr
, " (addr=0x%08lx, len=%d, type=%s)",
368 (unsigned long) addr
, len
,
369 type
== hw_write
? "hw-write-watchpoint"
370 : (type
== hw_read
? "hw-read-watchpoint"
371 : (type
== hw_access
? "hw-access-watchpoint"
372 : (type
== hw_execute
? "hw-breakpoint"
374 fprintf (stderr
, ":\n");
376 fprintf (stderr
, "\tBREAKPOINTs:\n");
377 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
378 fprintf (stderr
, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
379 i
, paddress (state
->dr_addr_bp
[i
]),
380 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
382 fprintf (stderr
, "\tWATCHPOINTs:\n");
383 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
384 fprintf (stderr
, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
385 i
, paddress (state
->dr_addr_wp
[i
]),
386 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
390 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
394 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
396 state
->dr_addr_bp
[i
] = 0;
397 state
->dr_ctrl_bp
[i
] = 0;
398 state
->dr_ref_count_bp
[i
] = 0;
401 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
403 state
->dr_addr_wp
[i
] = 0;
404 state
->dr_ctrl_wp
[i
] = 0;
405 state
->dr_ref_count_wp
[i
] = 0;
409 /* ptrace expects control registers to be formatted as follows:
412 +--------------------------------+----------+------+------+----+
413 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
414 +--------------------------------+----------+------+------+----+
416 The TYPE field is ignored for breakpoints. */
418 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
419 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
421 /* Utility function that returns the length in bytes of a watchpoint
422 according to the content of a hardware debug control register CTRL.
423 Note that the kernel currently only supports the following Byte
424 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
425 that for a hardware watchpoint, its valid length can only be 1
426 byte, 2 bytes, 4 bytes or 8 bytes. */
428 static inline unsigned int
429 aarch64_watchpoint_length (unsigned int ctrl
)
431 switch (DR_CONTROL_LENGTH (ctrl
))
446 /* Given the hardware breakpoint or watchpoint type TYPE and its
447 length LEN, return the expected encoding for a hardware
448 breakpoint/watchpoint control register. */
451 aarch64_point_encode_ctrl_reg (enum target_point_type type
, int len
)
458 ctrl
|= ((1 << len
) - 1) << 5;
460 ctrl
|= (2 << 1) | 1;
465 /* Addresses to be written to the hardware breakpoint and watchpoint
466 value registers need to be aligned; the alignment is 4-byte and
467 8-type respectively. Linux kernel rejects any non-aligned address
468 it receives from the related ptrace call. Furthermore, the kernel
469 currently only supports the following Byte Address Select (BAS)
470 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
471 watchpoint to be accepted by the kernel (via ptrace call), its
472 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
473 Despite these limitations, the unaligned watchpoint is supported in
476 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
479 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
481 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
482 : AARCH64_HBP_ALIGNMENT
;
484 if (addr
& (alignment
- 1))
487 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
493 /* Given the (potentially unaligned) watchpoint address in ADDR and
494 length in LEN, return the aligned address and aligned length in
495 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
496 aligned address and length will be valid to be written to the
497 hardware watchpoint value and control registers. See the comment
498 above aarch64_point_is_aligned for the information about the
499 alignment requirement. The given watchpoint may get truncated if
500 more than one hardware register is needed to cover the watched
501 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
502 address and length of the remaining part of the watchpoint (which
503 can be processed by calling this routine again to generate another
504 aligned address and length pair.
506 Essentially, unaligned watchpoint is achieved by minimally
507 enlarging the watched area to meet the alignment requirement, and
508 if necessary, splitting the watchpoint over several hardware
509 watchpoint registers. The trade-off is that there will be
510 false-positive hits for the read-type or the access-type hardware
511 watchpoints; for the write type, which is more commonly used, there
512 will be no such issues, as the higher-level breakpoint management
513 in gdb always examines the exact watched region for any content
514 change, and transparently resumes a thread from a watchpoint trap
515 if there is no change to the watched region.
517 Another limitation is that because the watched region is enlarged,
518 the watchpoint fault address returned by
519 aarch64_stopped_data_address may be outside of the original watched
520 region, especially when the triggering instruction is accessing a
521 larger region. When the fault address is not within any known
522 range, watchpoints_triggered in gdb will get confused, as the
523 higher-level watchpoint management is only aware of original
524 watched regions, and will think that some unknown watchpoint has
525 been triggered. In such a case, gdb may stop without displaying
526 any detailed information.
528 Once the kernel provides the full support for Byte Address Select
529 (BAS) in the hardware watchpoint control register, these
530 limitations can be largely relaxed with some further work. */
533 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
534 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
539 CORE_ADDR aligned_addr
;
540 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
541 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
543 /* As assumed by the algorithm. */
544 gdb_assert (alignment
== max_wp_len
);
549 /* Address to be put into the hardware watchpoint value register
551 offset
= addr
& (alignment
- 1);
552 aligned_addr
= addr
- offset
;
554 gdb_assert (offset
>= 0 && offset
< alignment
);
555 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
556 gdb_assert ((offset
+ len
) > 0);
558 if (offset
+ len
>= max_wp_len
)
560 /* Need more than one watchpoint registers; truncate it at the
561 alignment boundary. */
562 aligned_len
= max_wp_len
;
563 len
-= (max_wp_len
- offset
);
564 addr
+= (max_wp_len
- offset
);
565 gdb_assert ((addr
& (alignment
- 1)) == 0);
569 /* Find the smallest valid length that is large enough to
570 accommodate this watchpoint. */
571 static const unsigned char
572 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
573 { 1, 2, 4, 4, 8, 8, 8, 8 };
575 aligned_len
= aligned_len_array
[offset
+ len
- 1];
580 if (aligned_addr_p
!= NULL
)
581 *aligned_addr_p
= aligned_addr
;
582 if (aligned_len_p
!= NULL
)
583 *aligned_len_p
= aligned_len
;
584 if (next_addr_p
!= NULL
)
586 if (next_len_p
!= NULL
)
590 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
591 registers with data from *STATE. */
594 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
595 int tid
, int watchpoint
)
599 struct user_hwdebug_state regs
;
600 const CORE_ADDR
*addr
;
601 const unsigned int *ctrl
;
603 memset (®s
, 0, sizeof (regs
));
604 iov
.iov_base
= ®s
;
605 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
606 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
607 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
610 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
[count
- 1])
611 + sizeof (regs
.dbg_regs
[count
- 1]));
613 for (i
= 0; i
< count
; i
++)
615 regs
.dbg_regs
[i
].addr
= addr
[i
];
616 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
619 if (ptrace (PTRACE_SETREGSET
, tid
,
620 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
622 error (_("Unexpected error setting hardware debug registers"));
625 struct aarch64_dr_update_callback_param
632 /* Callback function which records the information about the change of
633 one hardware breakpoint/watchpoint setting for the thread ENTRY.
634 The information is passed in via PTR.
635 N.B. The actual updating of hardware debug registers is not
636 carried out until the moment the thread is resumed. */
639 debug_reg_change_callback (struct inferior_list_entry
*entry
, void *ptr
)
641 struct lwp_info
*lwp
= (struct lwp_info
*) entry
;
642 struct aarch64_dr_update_callback_param
*param_p
643 = (struct aarch64_dr_update_callback_param
*) ptr
;
644 int pid
= param_p
->pid
;
645 int idx
= param_p
->idx
;
646 int is_watchpoint
= param_p
->is_watchpoint
;
647 struct arch_lwp_info
*info
= lwp
->arch_private
;
648 dr_changed_t
*dr_changed_ptr
;
649 dr_changed_t dr_changed
;
653 fprintf (stderr
, "debug_reg_change_callback: \n\tOn entry:\n");
654 fprintf (stderr
, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
655 "dr_changed_wp=0x%llx\n",
656 pid
, lwpid_of (lwp
), info
->dr_changed_bp
,
657 info
->dr_changed_wp
);
660 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
661 : &info
->dr_changed_bp
;
662 dr_changed
= *dr_changed_ptr
;
664 /* Only update the threads of this process. */
665 if (pid_of (lwp
) == pid
)
668 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
669 : aarch64_num_bp_regs
)));
671 /* The following assertion is not right, as there can be changes
672 that have not been made to the hardware debug registers
673 before new changes overwrite the old ones. This can happen,
674 for instance, when the breakpoint/watchpoint hit one of the
675 threads and the user enters continue; then what happens is:
676 1) all breakpoints/watchpoints are removed for all threads;
677 2) a single step is carried out for the thread that was hit;
678 3) all of the points are inserted again for all threads;
679 4) all threads are resumed.
680 The 2nd step will only affect the one thread in which the
681 bp/wp was hit, which means only that one thread is resumed;
682 remember that the actual updating only happen in
683 aarch64_linux_prepare_to_resume, so other threads remain
684 stopped during the removal and insertion of bp/wp. Therefore
685 for those threads, the change of insertion of the bp/wp
686 overwrites that of the earlier removals. (The situation may
687 be different when bp/wp is steppable, or in the non-stop
689 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
691 /* The actual update is done later just before resuming the lwp,
692 we just mark that one register pair needs updating. */
693 DR_MARK_N_CHANGED (dr_changed
, idx
);
694 *dr_changed_ptr
= dr_changed
;
696 /* If the lwp isn't stopped, force it to momentarily pause, so
697 we can update its debug registers. */
699 linux_stop_lwp (lwp
);
704 fprintf (stderr
, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
705 "dr_changed_wp=0x%llx\n",
706 pid
, lwpid_of (lwp
), info
->dr_changed_bp
, info
->dr_changed_wp
);
712 /* Notify each thread that their IDXth breakpoint/watchpoint register
713 pair needs to be updated. The message will be recorded in each
714 thread's arch-specific data area, the actual updating will be done
715 when the thread is resumed. */
718 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
719 int is_watchpoint
, unsigned int idx
)
721 struct aarch64_dr_update_callback_param param
;
723 /* Only update the threads of this process. */
724 param
.pid
= pid_of (get_thread_lwp (current_inferior
));
726 param
.is_watchpoint
= is_watchpoint
;
729 find_inferior (&all_lwps
, debug_reg_change_callback
, (void *) ¶m
);
733 /* Return the pointer to the debug register state structure in the
734 current process' arch-specific data area. */
736 static struct aarch64_debug_reg_state
*
737 aarch64_get_debug_reg_state ()
739 struct process_info
*proc
;
741 proc
= current_process ();
742 return &proc
->private->arch_private
->debug_reg_state
;
745 /* Record the insertion of one breakpoint/watchpoint, as represented
746 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
749 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
750 enum target_point_type type
,
751 CORE_ADDR addr
, int len
)
753 int i
, idx
, num_regs
, is_watchpoint
;
754 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
755 CORE_ADDR
*dr_addr_p
;
757 /* Set up state pointers. */
758 is_watchpoint
= (type
!= hw_execute
);
759 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
762 num_regs
= aarch64_num_wp_regs
;
763 dr_addr_p
= state
->dr_addr_wp
;
764 dr_ctrl_p
= state
->dr_ctrl_wp
;
765 dr_ref_count
= state
->dr_ref_count_wp
;
769 num_regs
= aarch64_num_bp_regs
;
770 dr_addr_p
= state
->dr_addr_bp
;
771 dr_ctrl_p
= state
->dr_ctrl_bp
;
772 dr_ref_count
= state
->dr_ref_count_bp
;
775 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
777 /* Find an existing or free register in our cache. */
779 for (i
= 0; i
< num_regs
; ++i
)
781 if ((dr_ctrl_p
[i
] & 1) == 0)
783 gdb_assert (dr_ref_count
[i
] == 0);
785 /* no break; continue hunting for an exising one. */
787 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
789 gdb_assert (dr_ref_count
[i
] != 0);
799 /* Update our cache. */
800 if ((dr_ctrl_p
[idx
] & 1) == 0)
803 dr_addr_p
[idx
] = addr
;
804 dr_ctrl_p
[idx
] = ctrl
;
805 dr_ref_count
[idx
] = 1;
806 /* Notify the change. */
807 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
818 /* Record the removal of one breakpoint/watchpoint, as represented by
819 ADDR and CTRL, in the process' arch-specific data area *STATE. */
822 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
823 enum target_point_type type
,
824 CORE_ADDR addr
, int len
)
826 int i
, num_regs
, is_watchpoint
;
827 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
828 CORE_ADDR
*dr_addr_p
;
830 /* Set up state pointers. */
831 is_watchpoint
= (type
!= hw_execute
);
832 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
835 num_regs
= aarch64_num_wp_regs
;
836 dr_addr_p
= state
->dr_addr_wp
;
837 dr_ctrl_p
= state
->dr_ctrl_wp
;
838 dr_ref_count
= state
->dr_ref_count_wp
;
842 num_regs
= aarch64_num_bp_regs
;
843 dr_addr_p
= state
->dr_addr_bp
;
844 dr_ctrl_p
= state
->dr_ctrl_bp
;
845 dr_ref_count
= state
->dr_ref_count_bp
;
848 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
850 /* Find the entry that matches the ADDR and CTRL. */
851 for (i
= 0; i
< num_regs
; ++i
)
852 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
854 gdb_assert (dr_ref_count
[i
] != 0);
862 /* Clear our cache. */
863 if (--dr_ref_count
[i
] == 0)
865 /* Clear the enable bit. */
869 /* Notify the change. */
870 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
877 aarch64_handle_breakpoint (enum target_point_type type
, CORE_ADDR addr
,
878 int len
, int is_insert
)
880 struct aarch64_debug_reg_state
*state
;
882 /* The hardware breakpoint on AArch64 should always be 4-byte
884 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
887 state
= aarch64_get_debug_reg_state ();
890 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
892 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
895 /* This is essentially the same as aarch64_handle_breakpoint, apart
896 from that it is an aligned watchpoint to be handled. */
899 aarch64_handle_aligned_watchpoint (enum target_point_type type
,
900 CORE_ADDR addr
, int len
, int is_insert
)
902 struct aarch64_debug_reg_state
*state
;
904 state
= aarch64_get_debug_reg_state ();
907 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
909 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
912 /* Insert/remove unaligned watchpoint by calling
913 aarch64_align_watchpoint repeatedly until the whole watched region,
914 as represented by ADDR and LEN, has been properly aligned and ready
915 to be written to one or more hardware watchpoint registers.
916 IS_INSERT indicates whether this is an insertion or a deletion.
917 Return 0 if succeed. */
920 aarch64_handle_unaligned_watchpoint (enum target_point_type type
,
921 CORE_ADDR addr
, int len
, int is_insert
)
923 struct aarch64_debug_reg_state
*state
924 = aarch64_get_debug_reg_state ();
928 CORE_ADDR aligned_addr
;
929 int aligned_len
, ret
;
931 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
935 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
938 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
943 "handle_unaligned_watchpoint: is_insert: %d\n"
944 " aligned_addr: 0x%s, aligned_len: %d\n"
945 " next_addr: 0x%s, next_len: %d\n",
946 is_insert
, paddress (aligned_addr
), aligned_len
,
947 paddress (addr
), len
);
957 aarch64_handle_watchpoint (enum target_point_type type
, CORE_ADDR addr
,
958 int len
, int is_insert
)
960 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
961 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
);
963 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
);
966 /* Insert a hardware breakpoint/watchpoint.
967 It actually only records the info of the to-be-inserted bp/wp;
968 the actual insertion will happen when threads are resumed.
971 Return 1 if TYPE is unsupported type;
972 Return -1 if an error occurs. */
975 aarch64_insert_point (char type
, CORE_ADDR addr
, int len
)
978 enum target_point_type targ_type
;
981 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
982 (unsigned long) addr
, len
);
984 /* Determine the type from the packet. */
985 targ_type
= Z_packet_to_point_type (type
);
986 if (targ_type
== point_type_unsupported
)
989 if (targ_type
!= hw_execute
)
991 aarch64_handle_watchpoint (targ_type
, addr
, len
, 1 /* is_insert */);
994 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */);
996 if (debug_hw_points
> 1)
997 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
998 "insert_point", addr
, len
, targ_type
);
1003 /* Remove a hardware breakpoint/watchpoint.
1004 It actually only records the info of the to-be-removed bp/wp,
1005 the actual removal will be done when threads are resumed.
1007 Return 0 if succeed;
1008 Return 1 if TYPE is an unsupported type;
1009 Return -1 if an error occurs. */
1012 aarch64_remove_point (char type
, CORE_ADDR addr
, int len
)
1015 enum target_point_type targ_type
;
1017 if (debug_hw_points
)
1018 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1019 (unsigned long) addr
, len
);
1021 /* Determine the type from the packet. */
1022 targ_type
= Z_packet_to_point_type (type
);
1023 if (targ_type
== point_type_unsupported
)
1026 /* Set up state pointers. */
1027 if (targ_type
!= hw_execute
)
1029 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1032 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1034 if (debug_hw_points
> 1)
1035 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1036 "remove_point", addr
, len
, targ_type
);
1041 /* Returns the address associated with the watchpoint that hit, if
1042 any; returns 0 otherwise. */
1045 aarch64_stopped_data_address (void)
1049 struct aarch64_debug_reg_state
*state
;
1051 pid
= lwpid_of (get_thread_lwp (current_inferior
));
1053 /* Get the siginfo. */
1054 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
1055 return (CORE_ADDR
) 0;
1057 /* Need to be a hardware breakpoint/watchpoint trap. */
1058 if (siginfo
.si_signo
!= SIGTRAP
1059 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1060 return (CORE_ADDR
) 0;
1062 /* Check if the address matches any watched address. */
1063 state
= aarch64_get_debug_reg_state ();
1064 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1066 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1067 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1068 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1069 if (state
->dr_ref_count_wp
[i
]
1070 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1071 && addr_trap
>= addr_watch
1072 && addr_trap
< addr_watch
+ len
)
1076 return (CORE_ADDR
) 0;
1079 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1083 aarch64_stopped_by_watchpoint (void)
1085 if (aarch64_stopped_data_address () != 0)
1091 /* Fetch the thread-local storage pointer for libthread_db. */
1094 ps_get_thread_area (const struct ps_prochandle
*ph
,
1095 lwpid_t lwpid
, int idx
, void **base
)
1100 iovec
.iov_base
= ®
;
1101 iovec
.iov_len
= sizeof (reg
);
1103 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
1106 /* IDX is the bias from the thread pointer to the beginning of the
1107 thread descriptor. It has to be subtracted due to implementation
1108 quirks in libthread_db. */
1109 *base
= (void *) (reg
- idx
);
1114 /* Called when a new process is created. */
1116 static struct arch_process_info
*
1117 aarch64_linux_new_process (void)
1119 struct arch_process_info
*info
= xcalloc (1, sizeof (*info
));
1121 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
1126 /* Called when a new thread is detected. */
1128 static struct arch_lwp_info
*
1129 aarch64_linux_new_thread (void)
1131 struct arch_lwp_info
*info
= xcalloc (1, sizeof (*info
));
1133 /* Mark that all the hardware breakpoint/watchpoint register pairs
1134 for this thread need to be initialized (with data from
1135 aarch_process_info.debug_reg_state). */
1136 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
1137 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
1142 /* Called when resuming a thread.
1143 If the debug regs have changed, update the thread's copies. */
1146 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
1148 ptid_t ptid
= ptid_of (lwp
);
1149 struct arch_lwp_info
*info
= lwp
->arch_private
;
1151 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
1152 || DR_HAS_CHANGED (info
->dr_changed_wp
))
1154 int tid
= ptid_get_lwp (ptid
);
1155 struct process_info
*proc
= find_process_pid (ptid_get_pid (ptid
));
1156 struct aarch64_debug_reg_state
*state
1157 = &proc
->private->arch_private
->debug_reg_state
;
1159 if (debug_hw_points
)
1160 fprintf (stderr
, "prepare_to_resume thread %ld\n", lwpid_of (lwp
));
1163 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
1165 aarch64_linux_set_debug_regs (state
, tid
, 1);
1166 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
1170 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
1172 aarch64_linux_set_debug_regs (state
, tid
, 0);
1173 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
1178 /* ptrace hardware breakpoint resource info is formatted as follows:
1181 +---------------+--------------+---------------+---------------+
1182 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1183 +---------------+--------------+---------------+---------------+ */
1185 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1186 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1187 #define AARCH64_DEBUG_ARCH_V8 0x6
1190 aarch64_arch_setup (void)
1194 struct user_hwdebug_state dreg_state
;
1196 current_process ()->tdesc
= tdesc_aarch64
;
1198 pid
= lwpid_of (get_thread_lwp (current_inferior
));
1199 iov
.iov_base
= &dreg_state
;
1200 iov
.iov_len
= sizeof (dreg_state
);
1202 /* Get hardware watchpoint register info. */
1203 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_WATCH
, &iov
) == 0
1204 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1206 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1207 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
1209 warning ("Unexpected number of hardware watchpoint registers reported"
1210 " by ptrace, got %d, expected %d.",
1211 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
1212 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
1217 warning ("Unable to determine the number of hardware watchpoints"
1219 aarch64_num_wp_regs
= 0;
1222 /* Get hardware breakpoint register info. */
1223 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_BREAK
, &iov
) == 0
1224 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1226 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1227 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
1229 warning ("Unexpected number of hardware breakpoint registers reported"
1230 " by ptrace, got %d, expected %d.",
1231 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
1232 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
1237 warning ("Unable to determine the number of hardware breakpoints"
1239 aarch64_num_bp_regs
= 0;
1243 static struct regset_info aarch64_regsets
[] =
1245 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
1246 sizeof (struct user_pt_regs
), GENERAL_REGS
,
1247 aarch64_fill_gregset
, aarch64_store_gregset
},
1248 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
1249 sizeof (struct user_fpsimd_state
), FP_REGS
,
1250 aarch64_fill_fpregset
, aarch64_store_fpregset
1252 { 0, 0, 0, -1, -1, NULL
, NULL
}
1255 static struct regsets_info aarch64_regsets_info
=
1257 aarch64_regsets
, /* regsets */
1258 0, /* num_regsets */
1259 NULL
, /* disabled_regsets */
1262 static struct usrregs_info aarch64_usrregs_info
=
1268 static struct regs_info regs_info
=
1270 NULL
, /* regset_bitmap */
1271 &aarch64_usrregs_info
,
1272 &aarch64_regsets_info
,
1275 static const struct regs_info
*
1276 aarch64_regs_info (void)
1281 struct linux_target_ops the_low_target
=
1285 aarch64_cannot_fetch_register
,
1286 aarch64_cannot_store_register
,
1290 (const unsigned char *) &aarch64_breakpoint
,
1291 aarch64_breakpoint_len
,
1294 aarch64_breakpoint_at
,
1295 aarch64_insert_point
,
1296 aarch64_remove_point
,
1297 aarch64_stopped_by_watchpoint
,
1298 aarch64_stopped_data_address
,
1302 aarch64_linux_new_process
,
1303 aarch64_linux_new_thread
,
1304 aarch64_linux_prepare_to_resume
,
1308 initialize_low_arch (void)
1310 init_registers_aarch64 ();
1312 initialize_regsets_info (&aarch64_regsets_info
);