1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2018 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
41 #include "arch/aarch64.h"
42 #include "linux-aarch64-tdesc.h"
48 /* Per-process arch-specific data we want to keep. */
50 struct arch_process_info
52 /* Hardware breakpoint/watchpoint data.
53 The reason for them to be per-process rather than per-thread is
54 due to the lack of information in the gdbserver environment;
55 gdbserver is not told that whether a requested hardware
56 breakpoint/watchpoint is thread specific or not, so it has to set
57 each hw bp/wp for every thread in the current process. The
58 higher level bp/wp management in gdb will resume a thread if a hw
59 bp/wp trap is not expected for it. Since the hw bp/wp setting is
60 same for each thread, it is reasonable for the data to live here.
62 struct aarch64_debug_reg_state debug_reg_state
;
65 /* Return true if the size of register 0 is 8 byte. */
70 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
72 return register_size (regcache
->tdesc
, 0) == 8;
75 /* Implementation of linux_target_ops method "cannot_store_register". */
78 aarch64_cannot_store_register (int regno
)
80 return regno
>= AARCH64_NUM_REGS
;
83 /* Implementation of linux_target_ops method "cannot_fetch_register". */
86 aarch64_cannot_fetch_register (int regno
)
88 return regno
>= AARCH64_NUM_REGS
;
92 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
94 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
97 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
98 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
99 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
100 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
101 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
105 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
107 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
110 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
111 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
112 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
113 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
114 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
118 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
120 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
123 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
124 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
125 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
126 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
130 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
132 const struct user_fpsimd_state
*regset
133 = (const struct user_fpsimd_state
*) buf
;
136 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
137 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
138 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
139 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
142 /* Enable miscellaneous debugging output. The name is historical - it
143 was originally used to debug LinuxThreads support. */
144 extern int debug_threads
;
146 /* Implementation of linux_target_ops method "get_pc". */
149 aarch64_get_pc (struct regcache
*regcache
)
151 if (register_size (regcache
->tdesc
, 0) == 8)
152 return linux_get_pc_64bit (regcache
);
154 return linux_get_pc_32bit (regcache
);
157 /* Implementation of linux_target_ops method "set_pc". */
160 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
162 if (register_size (regcache
->tdesc
, 0) == 8)
163 linux_set_pc_64bit (regcache
, pc
);
165 linux_set_pc_32bit (regcache
, pc
);
168 #define aarch64_breakpoint_len 4
170 /* AArch64 BRK software debug mode instruction.
171 This instruction needs to match gdb/aarch64-tdep.c
172 (aarch64_default_breakpoint). */
173 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
175 /* Implementation of linux_target_ops method "breakpoint_at". */
178 aarch64_breakpoint_at (CORE_ADDR where
)
180 if (is_64bit_tdesc ())
182 gdb_byte insn
[aarch64_breakpoint_len
];
184 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
185 aarch64_breakpoint_len
);
186 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
192 return arm_breakpoint_at (where
);
196 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
200 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
202 state
->dr_addr_bp
[i
] = 0;
203 state
->dr_ctrl_bp
[i
] = 0;
204 state
->dr_ref_count_bp
[i
] = 0;
207 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
209 state
->dr_addr_wp
[i
] = 0;
210 state
->dr_ctrl_wp
[i
] = 0;
211 state
->dr_ref_count_wp
[i
] = 0;
215 /* Return the pointer to the debug register state structure in the
216 current process' arch-specific data area. */
218 struct aarch64_debug_reg_state
*
219 aarch64_get_debug_reg_state (pid_t pid
)
221 struct process_info
*proc
= find_process_pid (pid
);
223 return &proc
->priv
->arch_private
->debug_reg_state
;
226 /* Implementation of linux_target_ops method "supports_z_point_type". */
229 aarch64_supports_z_point_type (char z_type
)
235 case Z_PACKET_WRITE_WP
:
236 case Z_PACKET_READ_WP
:
237 case Z_PACKET_ACCESS_WP
:
244 /* Implementation of linux_target_ops method "insert_point".
246 It actually only records the info of the to-be-inserted bp/wp;
247 the actual insertion will happen when threads are resumed. */
250 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
251 int len
, struct raw_breakpoint
*bp
)
254 enum target_hw_bp_type targ_type
;
255 struct aarch64_debug_reg_state
*state
256 = aarch64_get_debug_reg_state (pid_of (current_thread
));
259 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
260 (unsigned long) addr
, len
);
262 /* Determine the type from the raw breakpoint type. */
263 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
265 if (targ_type
!= hw_execute
)
267 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
268 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
269 1 /* is_insert */, state
);
277 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
278 instruction. Set it to 2 to correctly encode length bit
279 mask in hardware/watchpoint control register. */
282 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
283 1 /* is_insert */, state
);
287 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
293 /* Implementation of linux_target_ops method "remove_point".
295 It actually only records the info of the to-be-removed bp/wp,
296 the actual removal will be done when threads are resumed. */
299 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
300 int len
, struct raw_breakpoint
*bp
)
303 enum target_hw_bp_type targ_type
;
304 struct aarch64_debug_reg_state
*state
305 = aarch64_get_debug_reg_state (pid_of (current_thread
));
308 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
309 (unsigned long) addr
, len
);
311 /* Determine the type from the raw breakpoint type. */
312 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
314 /* Set up state pointers. */
315 if (targ_type
!= hw_execute
)
317 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
323 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
324 instruction. Set it to 2 to correctly encode length bit
325 mask in hardware/watchpoint control register. */
328 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
329 0 /* is_insert */, state
);
333 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
339 /* Implementation of linux_target_ops method "stopped_data_address". */
342 aarch64_stopped_data_address (void)
346 struct aarch64_debug_reg_state
*state
;
348 pid
= lwpid_of (current_thread
);
350 /* Get the siginfo. */
351 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
352 return (CORE_ADDR
) 0;
354 /* Need to be a hardware breakpoint/watchpoint trap. */
355 if (siginfo
.si_signo
!= SIGTRAP
356 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
357 return (CORE_ADDR
) 0;
359 /* Check if the address matches any watched address. */
360 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
361 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
363 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
364 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
365 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
366 if (state
->dr_ref_count_wp
[i
]
367 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
368 && addr_trap
>= addr_watch
369 && addr_trap
< addr_watch
+ len
)
373 return (CORE_ADDR
) 0;
376 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
379 aarch64_stopped_by_watchpoint (void)
381 if (aarch64_stopped_data_address () != 0)
387 /* Fetch the thread-local storage pointer for libthread_db. */
390 ps_get_thread_area (struct ps_prochandle
*ph
,
391 lwpid_t lwpid
, int idx
, void **base
)
393 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
397 /* Implementation of linux_target_ops method "siginfo_fixup". */
400 aarch64_linux_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
, int direction
)
402 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
403 if (!is_64bit_tdesc ())
406 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
409 aarch64_siginfo_from_compat_siginfo (native
,
410 (struct compat_siginfo
*) inf
);
418 /* Implementation of linux_target_ops method "new_process". */
420 static struct arch_process_info
*
421 aarch64_linux_new_process (void)
423 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
425 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
430 /* Implementation of linux_target_ops method "delete_process". */
433 aarch64_linux_delete_process (struct arch_process_info
*info
)
438 /* Implementation of linux_target_ops method "linux_new_fork". */
441 aarch64_linux_new_fork (struct process_info
*parent
,
442 struct process_info
*child
)
444 /* These are allocated by linux_add_process. */
445 gdb_assert (parent
->priv
!= NULL
446 && parent
->priv
->arch_private
!= NULL
);
447 gdb_assert (child
->priv
!= NULL
448 && child
->priv
->arch_private
!= NULL
);
450 /* Linux kernel before 2.6.33 commit
451 72f674d203cd230426437cdcf7dd6f681dad8b0d
452 will inherit hardware debug registers from parent
453 on fork/vfork/clone. Newer Linux kernels create such tasks with
454 zeroed debug registers.
456 GDB core assumes the child inherits the watchpoints/hw
457 breakpoints of the parent, and will remove them all from the
458 forked off process. Copy the debug registers mirrors into the
459 new process so that all breakpoints and watchpoints can be
460 removed together. The debug registers mirror will become zeroed
461 in the end before detaching the forked off process, thus making
462 this compatible with older Linux kernels too. */
464 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
467 /* Implementation of linux_target_ops method "arch_setup". */
470 aarch64_arch_setup (void)
472 unsigned int machine
;
476 tid
= lwpid_of (current_thread
);
478 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
481 current_process ()->tdesc
= aarch64_linux_read_description ();
483 current_process ()->tdesc
= tdesc_arm_with_neon
;
485 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
488 static struct regset_info aarch64_regsets
[] =
490 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
491 sizeof (struct user_pt_regs
), GENERAL_REGS
,
492 aarch64_fill_gregset
, aarch64_store_gregset
},
493 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
494 sizeof (struct user_fpsimd_state
), FP_REGS
,
495 aarch64_fill_fpregset
, aarch64_store_fpregset
500 static struct regsets_info aarch64_regsets_info
=
502 aarch64_regsets
, /* regsets */
504 NULL
, /* disabled_regsets */
507 static struct regs_info regs_info_aarch64
=
509 NULL
, /* regset_bitmap */
511 &aarch64_regsets_info
,
514 /* Implementation of linux_target_ops method "regs_info". */
516 static const struct regs_info
*
517 aarch64_regs_info (void)
519 if (is_64bit_tdesc ())
520 return ®s_info_aarch64
;
522 return ®s_info_aarch32
;
525 /* Implementation of linux_target_ops method "supports_tracepoints". */
528 aarch64_supports_tracepoints (void)
530 if (current_thread
== NULL
)
534 /* We don't support tracepoints on aarch32 now. */
535 return is_64bit_tdesc ();
539 /* Implementation of linux_target_ops method "get_thread_area". */
542 aarch64_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
547 iovec
.iov_base
= ®
;
548 iovec
.iov_len
= sizeof (reg
);
550 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
558 /* Implementation of linux_target_ops method "get_syscall_trapinfo". */
561 aarch64_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
563 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
569 collect_register_by_name (regcache
, "x8", &l_sysno
);
570 *sysno
= (int) l_sysno
;
573 collect_register_by_name (regcache
, "r7", sysno
);
576 /* List of condition codes that we need. */
578 enum aarch64_condition_codes
589 enum aarch64_operand_type
595 /* Representation of an operand. At this time, it only supports register
596 and immediate types. */
598 struct aarch64_operand
600 /* Type of the operand. */
601 enum aarch64_operand_type type
;
603 /* Value of the operand according to the type. */
607 struct aarch64_register reg
;
611 /* List of registers that we are currently using, we can add more here as
612 we need to use them. */
614 /* General purpose scratch registers (64 bit). */
615 static const struct aarch64_register x0
= { 0, 1 };
616 static const struct aarch64_register x1
= { 1, 1 };
617 static const struct aarch64_register x2
= { 2, 1 };
618 static const struct aarch64_register x3
= { 3, 1 };
619 static const struct aarch64_register x4
= { 4, 1 };
621 /* General purpose scratch registers (32 bit). */
622 static const struct aarch64_register w0
= { 0, 0 };
623 static const struct aarch64_register w2
= { 2, 0 };
625 /* Intra-procedure scratch registers. */
626 static const struct aarch64_register ip0
= { 16, 1 };
628 /* Special purpose registers. */
629 static const struct aarch64_register fp
= { 29, 1 };
630 static const struct aarch64_register lr
= { 30, 1 };
631 static const struct aarch64_register sp
= { 31, 1 };
632 static const struct aarch64_register xzr
= { 31, 1 };
634 /* Dynamically allocate a new register. If we know the register
635 statically, we should make it a global as above instead of using this
638 static struct aarch64_register
639 aarch64_register (unsigned num
, int is64
)
641 return (struct aarch64_register
) { num
, is64
};
644 /* Helper function to create a register operand, for instructions with
645 different types of operands.
648 p += emit_mov (p, x0, register_operand (x1)); */
650 static struct aarch64_operand
651 register_operand (struct aarch64_register reg
)
653 struct aarch64_operand operand
;
655 operand
.type
= OPERAND_REGISTER
;
661 /* Helper function to create an immediate operand, for instructions with
662 different types of operands.
665 p += emit_mov (p, x0, immediate_operand (12)); */
667 static struct aarch64_operand
668 immediate_operand (uint32_t imm
)
670 struct aarch64_operand operand
;
672 operand
.type
= OPERAND_IMMEDIATE
;
678 /* Helper function to create an offset memory operand.
681 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
683 static struct aarch64_memory_operand
684 offset_memory_operand (int32_t offset
)
686 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
689 /* Helper function to create a pre-index memory operand.
692 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
694 static struct aarch64_memory_operand
695 preindex_memory_operand (int32_t index
)
697 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
700 /* Helper function to create a post-index memory operand.
703 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
705 static struct aarch64_memory_operand
706 postindex_memory_operand (int32_t index
)
708 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
711 /* System control registers. These special registers can be written and
712 read with the MRS and MSR instructions.
714 - NZCV: Condition flags. GDB refers to this register under the CPSR
716 - FPSR: Floating-point status register.
717 - FPCR: Floating-point control registers.
718 - TPIDR_EL0: Software thread ID register. */
720 enum aarch64_system_control_registers
722 /* op0 op1 crn crm op2 */
723 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
724 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
725 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
726 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
729 /* Write a BLR instruction into *BUF.
733 RN is the register to branch to. */
736 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
738 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
741 /* Write a RET instruction into *BUF.
745 RN is the register to branch to. */
748 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
750 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
754 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
755 struct aarch64_register rt
,
756 struct aarch64_register rt2
,
757 struct aarch64_register rn
,
758 struct aarch64_memory_operand operand
)
765 opc
= ENCODE (2, 2, 30);
767 opc
= ENCODE (0, 2, 30);
769 switch (operand
.type
)
771 case MEMORY_OPERAND_OFFSET
:
773 pre_index
= ENCODE (1, 1, 24);
774 write_back
= ENCODE (0, 1, 23);
777 case MEMORY_OPERAND_POSTINDEX
:
779 pre_index
= ENCODE (0, 1, 24);
780 write_back
= ENCODE (1, 1, 23);
783 case MEMORY_OPERAND_PREINDEX
:
785 pre_index
= ENCODE (1, 1, 24);
786 write_back
= ENCODE (1, 1, 23);
793 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
794 | ENCODE (operand
.index
>> 3, 7, 15)
795 | ENCODE (rt2
.num
, 5, 10)
796 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
799 /* Write a STP instruction into *BUF.
801 STP rt, rt2, [rn, #offset]
802 STP rt, rt2, [rn, #index]!
803 STP rt, rt2, [rn], #index
805 RT and RT2 are the registers to store.
806 RN is the base address register.
807 OFFSET is the immediate to add to the base address. It is limited to a
808 -512 .. 504 range (7 bits << 3). */
811 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
812 struct aarch64_register rt2
, struct aarch64_register rn
,
813 struct aarch64_memory_operand operand
)
815 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
818 /* Write a LDP instruction into *BUF.
820 LDP rt, rt2, [rn, #offset]
821 LDP rt, rt2, [rn, #index]!
822 LDP rt, rt2, [rn], #index
824 RT and RT2 are the registers to store.
825 RN is the base address register.
826 OFFSET is the immediate to add to the base address. It is limited to a
827 -512 .. 504 range (7 bits << 3). */
830 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
831 struct aarch64_register rt2
, struct aarch64_register rn
,
832 struct aarch64_memory_operand operand
)
834 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
837 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
839 LDP qt, qt2, [rn, #offset]
841 RT and RT2 are the Q registers to store.
842 RN is the base address register.
843 OFFSET is the immediate to add to the base address. It is limited to
844 -1024 .. 1008 range (7 bits << 4). */
847 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
848 struct aarch64_register rn
, int32_t offset
)
850 uint32_t opc
= ENCODE (2, 2, 30);
851 uint32_t pre_index
= ENCODE (1, 1, 24);
853 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
854 | ENCODE (offset
>> 4, 7, 15)
855 | ENCODE (rt2
, 5, 10)
856 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
859 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
861 STP qt, qt2, [rn, #offset]
863 RT and RT2 are the Q registers to store.
864 RN is the base address register.
865 OFFSET is the immediate to add to the base address. It is limited to
866 -1024 .. 1008 range (7 bits << 4). */
869 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
870 struct aarch64_register rn
, int32_t offset
)
872 uint32_t opc
= ENCODE (2, 2, 30);
873 uint32_t pre_index
= ENCODE (1, 1, 24);
875 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
876 | ENCODE (offset
>> 4, 7, 15)
877 | ENCODE (rt2
, 5, 10)
878 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
881 /* Write a LDRH instruction into *BUF.
883 LDRH wt, [xn, #offset]
884 LDRH wt, [xn, #index]!
885 LDRH wt, [xn], #index
887 RT is the register to store.
888 RN is the base address register.
889 OFFSET is the immediate to add to the base address. It is limited to
890 0 .. 32760 range (12 bits << 3). */
893 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
894 struct aarch64_register rn
,
895 struct aarch64_memory_operand operand
)
897 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
900 /* Write a LDRB instruction into *BUF.
902 LDRB wt, [xn, #offset]
903 LDRB wt, [xn, #index]!
904 LDRB wt, [xn], #index
906 RT is the register to store.
907 RN is the base address register.
908 OFFSET is the immediate to add to the base address. It is limited to
909 0 .. 32760 range (12 bits << 3). */
912 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
913 struct aarch64_register rn
,
914 struct aarch64_memory_operand operand
)
916 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
921 /* Write a STR instruction into *BUF.
923 STR rt, [rn, #offset]
924 STR rt, [rn, #index]!
927 RT is the register to store.
928 RN is the base address register.
929 OFFSET is the immediate to add to the base address. It is limited to
930 0 .. 32760 range (12 bits << 3). */
933 emit_str (uint32_t *buf
, struct aarch64_register rt
,
934 struct aarch64_register rn
,
935 struct aarch64_memory_operand operand
)
937 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
940 /* Helper function emitting an exclusive load or store instruction. */
943 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
944 enum aarch64_opcodes opcode
,
945 struct aarch64_register rs
,
946 struct aarch64_register rt
,
947 struct aarch64_register rt2
,
948 struct aarch64_register rn
)
950 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
951 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
952 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
955 /* Write a LAXR instruction into *BUF.
959 RT is the destination register.
960 RN is the base address register. */
963 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
964 struct aarch64_register rn
)
966 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
970 /* Write a STXR instruction into *BUF.
974 RS is the result register, it indicates if the store succeeded or not.
975 RT is the destination register.
976 RN is the base address register. */
979 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
980 struct aarch64_register rt
, struct aarch64_register rn
)
982 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
986 /* Write a STLR instruction into *BUF.
990 RT is the register to store.
991 RN is the base address register. */
994 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
995 struct aarch64_register rn
)
997 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1001 /* Helper function for data processing instructions with register sources. */
1004 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1005 struct aarch64_register rd
,
1006 struct aarch64_register rn
,
1007 struct aarch64_register rm
)
1009 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1011 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1012 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1015 /* Helper function for data processing instructions taking either a register
1019 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1020 struct aarch64_register rd
,
1021 struct aarch64_register rn
,
1022 struct aarch64_operand operand
)
1024 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1025 /* The opcode is different for register and immediate source operands. */
1026 uint32_t operand_opcode
;
1028 if (operand
.type
== OPERAND_IMMEDIATE
)
1030 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1031 operand_opcode
= ENCODE (8, 4, 25);
1033 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1034 | ENCODE (operand
.imm
, 12, 10)
1035 | ENCODE (rn
.num
, 5, 5)
1036 | ENCODE (rd
.num
, 5, 0));
1040 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1041 operand_opcode
= ENCODE (5, 4, 25);
1043 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1048 /* Write an ADD instruction into *BUF.
1053 This function handles both an immediate and register add.
1055 RD is the destination register.
1056 RN is the input register.
1057 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1058 OPERAND_REGISTER. */
1061 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1062 struct aarch64_register rn
, struct aarch64_operand operand
)
1064 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1067 /* Write a SUB instruction into *BUF.
1072 This function handles both an immediate and register sub.
1074 RD is the destination register.
1075 RN is the input register.
1076 IMM is the immediate to substract to RN. */
1079 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1080 struct aarch64_register rn
, struct aarch64_operand operand
)
1082 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1085 /* Write a MOV instruction into *BUF.
1090 This function handles both a wide immediate move and a register move,
1091 with the condition that the source register is not xzr. xzr and the
1092 stack pointer share the same encoding and this function only supports
1095 RD is the destination register.
1096 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1097 OPERAND_REGISTER. */
1100 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1101 struct aarch64_operand operand
)
1103 if (operand
.type
== OPERAND_IMMEDIATE
)
1105 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1106 /* Do not shift the immediate. */
1107 uint32_t shift
= ENCODE (0, 2, 21);
1109 return aarch64_emit_insn (buf
, MOV
| size
| shift
1110 | ENCODE (operand
.imm
, 16, 5)
1111 | ENCODE (rd
.num
, 5, 0));
1114 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1117 /* Write a MOVK instruction into *BUF.
1119 MOVK rd, #imm, lsl #shift
1121 RD is the destination register.
1122 IMM is the immediate.
1123 SHIFT is the logical shift left to apply to IMM. */
1126 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1129 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1131 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1132 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1135 /* Write instructions into *BUF in order to move ADDR into a register.
1136 ADDR can be a 64-bit value.
1138 This function will emit a series of MOV and MOVK instructions, such as:
1141 MOVK xd, #(addr >> 16), lsl #16
1142 MOVK xd, #(addr >> 32), lsl #32
1143 MOVK xd, #(addr >> 48), lsl #48 */
1146 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1150 /* The MOV (wide immediate) instruction clears to top bits of the
1152 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1154 if ((addr
>> 16) != 0)
1155 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1159 if ((addr
>> 32) != 0)
1160 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1164 if ((addr
>> 48) != 0)
1165 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1170 /* Write a SUBS instruction into *BUF.
1174 This instruction update the condition flags.
1176 RD is the destination register.
1177 RN and RM are the source registers. */
1180 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1181 struct aarch64_register rn
, struct aarch64_operand operand
)
1183 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1186 /* Write a CMP instruction into *BUF.
1190 This instruction is an alias of SUBS xzr, rn, rm.
1192 RN and RM are the registers to compare. */
1195 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1196 struct aarch64_operand operand
)
1198 return emit_subs (buf
, xzr
, rn
, operand
);
1201 /* Write a AND instruction into *BUF.
1205 RD is the destination register.
1206 RN and RM are the source registers. */
1209 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1210 struct aarch64_register rn
, struct aarch64_register rm
)
1212 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1215 /* Write a ORR instruction into *BUF.
1219 RD is the destination register.
1220 RN and RM are the source registers. */
1223 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1224 struct aarch64_register rn
, struct aarch64_register rm
)
1226 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1229 /* Write a ORN instruction into *BUF.
1233 RD is the destination register.
1234 RN and RM are the source registers. */
1237 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1238 struct aarch64_register rn
, struct aarch64_register rm
)
1240 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1243 /* Write a EOR instruction into *BUF.
1247 RD is the destination register.
1248 RN and RM are the source registers. */
1251 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1252 struct aarch64_register rn
, struct aarch64_register rm
)
1254 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1257 /* Write a MVN instruction into *BUF.
1261 This is an alias for ORN rd, xzr, rm.
1263 RD is the destination register.
1264 RM is the source register. */
1267 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1268 struct aarch64_register rm
)
1270 return emit_orn (buf
, rd
, xzr
, rm
);
1273 /* Write a LSLV instruction into *BUF.
1277 RD is the destination register.
1278 RN and RM are the source registers. */
1281 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1282 struct aarch64_register rn
, struct aarch64_register rm
)
1284 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1287 /* Write a LSRV instruction into *BUF.
1291 RD is the destination register.
1292 RN and RM are the source registers. */
1295 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1296 struct aarch64_register rn
, struct aarch64_register rm
)
1298 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1301 /* Write a ASRV instruction into *BUF.
1305 RD is the destination register.
1306 RN and RM are the source registers. */
1309 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1310 struct aarch64_register rn
, struct aarch64_register rm
)
1312 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1315 /* Write a MUL instruction into *BUF.
1319 RD is the destination register.
1320 RN and RM are the source registers. */
1323 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1324 struct aarch64_register rn
, struct aarch64_register rm
)
1326 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1329 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1333 RT is the destination register.
1334 SYSTEM_REG is special purpose register to read. */
1337 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1338 enum aarch64_system_control_registers system_reg
)
1340 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1341 | ENCODE (rt
.num
, 5, 0));
1344 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1348 SYSTEM_REG is special purpose register to write.
1349 RT is the input register. */
1352 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1353 struct aarch64_register rt
)
1355 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1356 | ENCODE (rt
.num
, 5, 0));
1359 /* Write a SEVL instruction into *BUF.
1361 This is a hint instruction telling the hardware to trigger an event. */
1364 emit_sevl (uint32_t *buf
)
1366 return aarch64_emit_insn (buf
, SEVL
);
1369 /* Write a WFE instruction into *BUF.
1371 This is a hint instruction telling the hardware to wait for an event. */
1374 emit_wfe (uint32_t *buf
)
1376 return aarch64_emit_insn (buf
, WFE
);
1379 /* Write a SBFM instruction into *BUF.
1381 SBFM rd, rn, #immr, #imms
1383 This instruction moves the bits from #immr to #imms into the
1384 destination, sign extending the result.
1386 RD is the destination register.
1387 RN is the source register.
1388 IMMR is the bit number to start at (least significant bit).
1389 IMMS is the bit number to stop at (most significant bit). */
1392 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1393 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1395 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1396 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1398 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1399 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1400 | ENCODE (rd
.num
, 5, 0));
1403 /* Write a SBFX instruction into *BUF.
1405 SBFX rd, rn, #lsb, #width
1407 This instruction moves #width bits from #lsb into the destination, sign
1408 extending the result. This is an alias for:
1410 SBFM rd, rn, #lsb, #(lsb + width - 1)
1412 RD is the destination register.
1413 RN is the source register.
1414 LSB is the bit number to start at (least significant bit).
1415 WIDTH is the number of bits to move. */
1418 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1419 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1421 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1424 /* Write a UBFM instruction into *BUF.
1426 UBFM rd, rn, #immr, #imms
1428 This instruction moves the bits from #immr to #imms into the
1429 destination, extending the result with zeros.
1431 RD is the destination register.
1432 RN is the source register.
1433 IMMR is the bit number to start at (least significant bit).
1434 IMMS is the bit number to stop at (most significant bit). */
1437 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1438 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1440 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1441 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1443 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1444 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1445 | ENCODE (rd
.num
, 5, 0));
1448 /* Write a UBFX instruction into *BUF.
1450 UBFX rd, rn, #lsb, #width
1452 This instruction moves #width bits from #lsb into the destination,
1453 extending the result with zeros. This is an alias for:
1455 UBFM rd, rn, #lsb, #(lsb + width - 1)
1457 RD is the destination register.
1458 RN is the source register.
1459 LSB is the bit number to start at (least significant bit).
1460 WIDTH is the number of bits to move. */
1463 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1464 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1466 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1469 /* Write a CSINC instruction into *BUF.
1471 CSINC rd, rn, rm, cond
1473 This instruction conditionally increments rn or rm and places the result
1474 in rd. rn is chosen is the condition is true.
1476 RD is the destination register.
1477 RN and RM are the source registers.
1478 COND is the encoded condition. */
1481 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1482 struct aarch64_register rn
, struct aarch64_register rm
,
1485 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1487 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1488 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1489 | ENCODE (rd
.num
, 5, 0));
1492 /* Write a CSET instruction into *BUF.
1496 This instruction conditionally write 1 or 0 in the destination register.
1497 1 is written if the condition is true. This is an alias for:
1499 CSINC rd, xzr, xzr, !cond
1501 Note that the condition needs to be inverted.
1503 RD is the destination register.
1504 RN and RM are the source registers.
1505 COND is the encoded condition. */
1508 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1510 /* The least significant bit of the condition needs toggling in order to
1512 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1515 /* Write LEN instructions from BUF into the inferior memory at *TO.
1517 Note instructions are always little endian on AArch64, unlike data. */
1520 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1522 size_t byte_len
= len
* sizeof (uint32_t);
1523 #if (__BYTE_ORDER == __BIG_ENDIAN)
1524 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1527 for (i
= 0; i
< len
; i
++)
1528 le_buf
[i
] = htole32 (buf
[i
]);
1530 write_inferior_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1534 write_inferior_memory (*to
, (const unsigned char *) buf
, byte_len
);
1540 /* Sub-class of struct aarch64_insn_data, store information of
1541 instruction relocation for fast tracepoint. Visitor can
1542 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1543 the relocated instructions in buffer pointed by INSN_PTR. */
1545 struct aarch64_insn_relocation_data
1547 struct aarch64_insn_data base
;
1549 /* The new address the instruction is relocated to. */
1551 /* Pointer to the buffer of relocated instruction(s). */
1555 /* Implementation of aarch64_insn_visitor method "b". */
1558 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1559 struct aarch64_insn_data
*data
)
1561 struct aarch64_insn_relocation_data
*insn_reloc
1562 = (struct aarch64_insn_relocation_data
*) data
;
1564 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1566 if (can_encode_int32 (new_offset
, 28))
1567 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1570 /* Implementation of aarch64_insn_visitor method "b_cond". */
1573 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1574 struct aarch64_insn_data
*data
)
1576 struct aarch64_insn_relocation_data
*insn_reloc
1577 = (struct aarch64_insn_relocation_data
*) data
;
1579 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1581 if (can_encode_int32 (new_offset
, 21))
1583 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1586 else if (can_encode_int32 (new_offset
, 28))
1588 /* The offset is out of range for a conditional branch
1589 instruction but not for a unconditional branch. We can use
1590 the following instructions instead:
1592 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1593 B NOT_TAKEN ; Else jump over TAKEN and continue.
1600 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1601 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1602 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1606 /* Implementation of aarch64_insn_visitor method "cb". */
1609 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1610 const unsigned rn
, int is64
,
1611 struct aarch64_insn_data
*data
)
1613 struct aarch64_insn_relocation_data
*insn_reloc
1614 = (struct aarch64_insn_relocation_data
*) data
;
1616 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1618 if (can_encode_int32 (new_offset
, 21))
1620 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1621 aarch64_register (rn
, is64
), new_offset
);
1623 else if (can_encode_int32 (new_offset
, 28))
1625 /* The offset is out of range for a compare and branch
1626 instruction but not for a unconditional branch. We can use
1627 the following instructions instead:
1629 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1630 B NOT_TAKEN ; Else jump over TAKEN and continue.
1636 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1637 aarch64_register (rn
, is64
), 8);
1638 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1639 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1643 /* Implementation of aarch64_insn_visitor method "tb". */
1646 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1647 const unsigned rt
, unsigned bit
,
1648 struct aarch64_insn_data
*data
)
1650 struct aarch64_insn_relocation_data
*insn_reloc
1651 = (struct aarch64_insn_relocation_data
*) data
;
1653 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1655 if (can_encode_int32 (new_offset
, 16))
1657 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1658 aarch64_register (rt
, 1), new_offset
);
1660 else if (can_encode_int32 (new_offset
, 28))
1662 /* The offset is out of range for a test bit and branch
1663 instruction but not for a unconditional branch. We can use
1664 the following instructions instead:
1666 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1667 B NOT_TAKEN ; Else jump over TAKEN and continue.
1673 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1674 aarch64_register (rt
, 1), 8);
1675 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1676 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1681 /* Implementation of aarch64_insn_visitor method "adr". */
1684 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1686 struct aarch64_insn_data
*data
)
1688 struct aarch64_insn_relocation_data
*insn_reloc
1689 = (struct aarch64_insn_relocation_data
*) data
;
1690 /* We know exactly the address the ADR{P,} instruction will compute.
1691 We can just write it to the destination register. */
1692 CORE_ADDR address
= data
->insn_addr
+ offset
;
1696 /* Clear the lower 12 bits of the offset to get the 4K page. */
1697 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1698 aarch64_register (rd
, 1),
1702 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1703 aarch64_register (rd
, 1), address
);
1706 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1709 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
1710 const unsigned rt
, const int is64
,
1711 struct aarch64_insn_data
*data
)
1713 struct aarch64_insn_relocation_data
*insn_reloc
1714 = (struct aarch64_insn_relocation_data
*) data
;
1715 CORE_ADDR address
= data
->insn_addr
+ offset
;
1717 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1718 aarch64_register (rt
, 1), address
);
1720 /* We know exactly what address to load from, and what register we
1723 MOV xd, #(oldloc + offset)
1724 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1727 LDR xd, [xd] ; or LDRSW xd, [xd]
1732 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
1733 aarch64_register (rt
, 1),
1734 aarch64_register (rt
, 1),
1735 offset_memory_operand (0));
1737 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
1738 aarch64_register (rt
, is64
),
1739 aarch64_register (rt
, 1),
1740 offset_memory_operand (0));
1743 /* Implementation of aarch64_insn_visitor method "others". */
1746 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
1747 struct aarch64_insn_data
*data
)
1749 struct aarch64_insn_relocation_data
*insn_reloc
1750 = (struct aarch64_insn_relocation_data
*) data
;
1752 /* The instruction is not PC relative. Just re-emit it at the new
1754 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
1757 static const struct aarch64_insn_visitor visitor
=
1759 aarch64_ftrace_insn_reloc_b
,
1760 aarch64_ftrace_insn_reloc_b_cond
,
1761 aarch64_ftrace_insn_reloc_cb
,
1762 aarch64_ftrace_insn_reloc_tb
,
1763 aarch64_ftrace_insn_reloc_adr
,
1764 aarch64_ftrace_insn_reloc_ldr_literal
,
1765 aarch64_ftrace_insn_reloc_others
,
1768 /* Implementation of linux_target_ops method
1769 "install_fast_tracepoint_jump_pad". */
1772 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1774 CORE_ADDR collector
,
1777 CORE_ADDR
*jump_entry
,
1778 CORE_ADDR
*trampoline
,
1779 ULONGEST
*trampoline_size
,
1780 unsigned char *jjump_pad_insn
,
1781 ULONGEST
*jjump_pad_insn_size
,
1782 CORE_ADDR
*adjusted_insn_addr
,
1783 CORE_ADDR
*adjusted_insn_addr_end
,
1791 CORE_ADDR buildaddr
= *jump_entry
;
1792 struct aarch64_insn_relocation_data insn_data
;
1794 /* We need to save the current state on the stack both to restore it
1795 later and to collect register values when the tracepoint is hit.
1797 The saved registers are pushed in a layout that needs to be in sync
1798 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
1799 the supply_fast_tracepoint_registers function will fill in the
1800 register cache from a pointer to saved registers on the stack we build
1803 For simplicity, we set the size of each cell on the stack to 16 bytes.
1804 This way one cell can hold any register type, from system registers
1805 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
1806 has to be 16 bytes aligned anyway.
1808 Note that the CPSR register does not exist on AArch64. Instead we
1809 can access system bits describing the process state with the
1810 MRS/MSR instructions, namely the condition flags. We save them as
1811 if they are part of a CPSR register because that's how GDB
1812 interprets these system bits. At the moment, only the condition
1813 flags are saved in CPSR (NZCV).
1815 Stack layout, each cell is 16 bytes (descending):
1817 High *-------- SIMD&FP registers from 31 down to 0. --------*
1823 *---- General purpose registers from 30 down to 0. ----*
1829 *------------- Special purpose registers. -------------*
1832 | CPSR (NZCV) | 5 cells
1835 *------------- collecting_t object --------------------*
1836 | TPIDR_EL0 | struct tracepoint * |
1837 Low *------------------------------------------------------*
1839 After this stack is set up, we issue a call to the collector, passing
1840 it the saved registers at (SP + 16). */
1842 /* Push SIMD&FP registers on the stack:
1844 SUB sp, sp, #(32 * 16)
1846 STP q30, q31, [sp, #(30 * 16)]
1851 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
1852 for (i
= 30; i
>= 0; i
-= 2)
1853 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
1855 /* Push general puspose registers on the stack. Note that we do not need
1856 to push x31 as it represents the xzr register and not the stack
1857 pointer in a STR instruction.
1859 SUB sp, sp, #(31 * 16)
1861 STR x30, [sp, #(30 * 16)]
1866 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
1867 for (i
= 30; i
>= 0; i
-= 1)
1868 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
1869 offset_memory_operand (i
* 16));
1871 /* Make space for 5 more cells.
1873 SUB sp, sp, #(5 * 16)
1876 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
1881 ADD x4, sp, #((32 + 31 + 5) * 16)
1882 STR x4, [sp, #(4 * 16)]
1885 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
1886 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
1888 /* Save PC (tracepoint address):
1893 STR x3, [sp, #(3 * 16)]
1897 p
+= emit_mov_addr (p
, x3
, tpaddr
);
1898 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
1900 /* Save CPSR (NZCV), FPSR and FPCR:
1906 STR x2, [sp, #(2 * 16)]
1907 STR x1, [sp, #(1 * 16)]
1908 STR x0, [sp, #(0 * 16)]
1911 p
+= emit_mrs (p
, x2
, NZCV
);
1912 p
+= emit_mrs (p
, x1
, FPSR
);
1913 p
+= emit_mrs (p
, x0
, FPCR
);
1914 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
1915 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
1916 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
1918 /* Push the collecting_t object. It consist of the address of the
1919 tracepoint and an ID for the current thread. We get the latter by
1920 reading the tpidr_el0 system register. It corresponds to the
1921 NT_ARM_TLS register accessible with ptrace.
1928 STP x0, x1, [sp, #-16]!
1932 p
+= emit_mov_addr (p
, x0
, tpoint
);
1933 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
1934 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
1938 The shared memory for the lock is at lockaddr. It will hold zero
1939 if no-one is holding the lock, otherwise it contains the address of
1940 the collecting_t object on the stack of the thread which acquired it.
1942 At this stage, the stack pointer points to this thread's collecting_t
1945 We use the following registers:
1946 - x0: Address of the lock.
1947 - x1: Pointer to collecting_t object.
1948 - x2: Scratch register.
1954 ; Trigger an event local to this core. So the following WFE
1955 ; instruction is ignored.
1958 ; Wait for an event. The event is triggered by either the SEVL
1959 ; or STLR instructions (store release).
1962 ; Atomically read at lockaddr. This marks the memory location as
1963 ; exclusive. This instruction also has memory constraints which
1964 ; make sure all previous data reads and writes are done before
1968 ; Try again if another thread holds the lock.
1971 ; We can lock it! Write the address of the collecting_t object.
1972 ; This instruction will fail if the memory location is not marked
1973 ; as exclusive anymore. If it succeeds, it will remove the
1974 ; exclusive mark on the memory location. This way, if another
1975 ; thread executes this instruction before us, we will fail and try
1982 p
+= emit_mov_addr (p
, x0
, lockaddr
);
1983 p
+= emit_mov (p
, x1
, register_operand (sp
));
1987 p
+= emit_ldaxr (p
, x2
, x0
);
1988 p
+= emit_cb (p
, 1, w2
, -2 * 4);
1989 p
+= emit_stxr (p
, w2
, x1
, x0
);
1990 p
+= emit_cb (p
, 1, x2
, -4 * 4);
1992 /* Call collector (struct tracepoint *, unsigned char *):
1997 ; Saved registers start after the collecting_t object.
2000 ; We use an intra-procedure-call scratch register.
2001 MOV ip0, #(collector)
2004 ; And call back to C!
2009 p
+= emit_mov_addr (p
, x0
, tpoint
);
2010 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2012 p
+= emit_mov_addr (p
, ip0
, collector
);
2013 p
+= emit_blr (p
, ip0
);
2015 /* Release the lock.
2020 ; This instruction is a normal store with memory ordering
2021 ; constraints. Thanks to this we do not have to put a data
2022 ; barrier instruction to make sure all data read and writes are done
2023 ; before this instruction is executed. Furthermore, this instrucion
2024 ; will trigger an event, letting other threads know they can grab
2029 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2030 p
+= emit_stlr (p
, xzr
, x0
);
2032 /* Free collecting_t object:
2037 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2039 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2040 registers from the stack.
2042 LDR x2, [sp, #(2 * 16)]
2043 LDR x1, [sp, #(1 * 16)]
2044 LDR x0, [sp, #(0 * 16)]
2050 ADD sp, sp #(5 * 16)
2053 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2054 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2055 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2056 p
+= emit_msr (p
, NZCV
, x2
);
2057 p
+= emit_msr (p
, FPSR
, x1
);
2058 p
+= emit_msr (p
, FPCR
, x0
);
2060 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2062 /* Pop general purpose registers:
2066 LDR x30, [sp, #(30 * 16)]
2068 ADD sp, sp, #(31 * 16)
2071 for (i
= 0; i
<= 30; i
+= 1)
2072 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2073 offset_memory_operand (i
* 16));
2074 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2076 /* Pop SIMD&FP registers:
2080 LDP q30, q31, [sp, #(30 * 16)]
2082 ADD sp, sp, #(32 * 16)
2085 for (i
= 0; i
<= 30; i
+= 2)
2086 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2087 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2089 /* Write the code into the inferior memory. */
2090 append_insns (&buildaddr
, p
- buf
, buf
);
2092 /* Now emit the relocated instruction. */
2093 *adjusted_insn_addr
= buildaddr
;
2094 target_read_uint32 (tpaddr
, &insn
);
2096 insn_data
.base
.insn_addr
= tpaddr
;
2097 insn_data
.new_addr
= buildaddr
;
2098 insn_data
.insn_ptr
= buf
;
2100 aarch64_relocate_instruction (insn
, &visitor
,
2101 (struct aarch64_insn_data
*) &insn_data
);
2103 /* We may not have been able to relocate the instruction. */
2104 if (insn_data
.insn_ptr
== buf
)
2107 "E.Could not relocate instruction from %s to %s.",
2108 core_addr_to_string_nz (tpaddr
),
2109 core_addr_to_string_nz (buildaddr
));
2113 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2114 *adjusted_insn_addr_end
= buildaddr
;
2116 /* Go back to the start of the buffer. */
2119 /* Emit a branch back from the jump pad. */
2120 offset
= (tpaddr
+ orig_size
- buildaddr
);
2121 if (!can_encode_int32 (offset
, 28))
2124 "E.Jump back from jump pad too far from tracepoint "
2125 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2130 p
+= emit_b (p
, 0, offset
);
2131 append_insns (&buildaddr
, p
- buf
, buf
);
2133 /* Give the caller a branch instruction into the jump pad. */
2134 offset
= (*jump_entry
- tpaddr
);
2135 if (!can_encode_int32 (offset
, 28))
2138 "E.Jump pad too far from tracepoint "
2139 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2144 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2145 *jjump_pad_insn_size
= 4;
2147 /* Return the end address of our pad. */
2148 *jump_entry
= buildaddr
;
2153 /* Helper function writing LEN instructions from START into
2154 current_insn_ptr. */
2157 emit_ops_insns (const uint32_t *start
, int len
)
2159 CORE_ADDR buildaddr
= current_insn_ptr
;
2162 debug_printf ("Adding %d instrucions at %s\n",
2163 len
, paddress (buildaddr
));
2165 append_insns (&buildaddr
, len
, start
);
2166 current_insn_ptr
= buildaddr
;
2169 /* Pop a register from the stack. */
2172 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2174 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2177 /* Push a register on the stack. */
2180 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2182 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2185 /* Implementation of emit_ops method "emit_prologue". */
2188 aarch64_emit_prologue (void)
2193 /* This function emit a prologue for the following function prototype:
2195 enum eval_result_type f (unsigned char *regs,
2198 The first argument is a buffer of raw registers. The second
2199 argument is the result of
2200 evaluating the expression, which will be set to whatever is on top of
2201 the stack at the end.
2203 The stack set up by the prologue is as such:
2205 High *------------------------------------------------------*
2208 | x1 (ULONGEST *value) |
2209 | x0 (unsigned char *regs) |
2210 Low *------------------------------------------------------*
2212 As we are implementing a stack machine, each opcode can expand the
2213 stack so we never know how far we are from the data saved by this
2214 prologue. In order to be able refer to value and regs later, we save
2215 the current stack pointer in the frame pointer. This way, it is not
2216 clobbered when calling C functions.
2218 Finally, throughtout every operation, we are using register x0 as the
2219 top of the stack, and x1 as a scratch register. */
2221 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2222 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2223 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2225 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2228 emit_ops_insns (buf
, p
- buf
);
2231 /* Implementation of emit_ops method "emit_epilogue". */
2234 aarch64_emit_epilogue (void)
2239 /* Store the result of the expression (x0) in *value. */
2240 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2241 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2242 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2244 /* Restore the previous state. */
2245 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2246 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2248 /* Return expr_eval_no_error. */
2249 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2250 p
+= emit_ret (p
, lr
);
2252 emit_ops_insns (buf
, p
- buf
);
2255 /* Implementation of emit_ops method "emit_add". */
2258 aarch64_emit_add (void)
2263 p
+= emit_pop (p
, x1
);
2264 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2266 emit_ops_insns (buf
, p
- buf
);
2269 /* Implementation of emit_ops method "emit_sub". */
2272 aarch64_emit_sub (void)
2277 p
+= emit_pop (p
, x1
);
2278 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2280 emit_ops_insns (buf
, p
- buf
);
2283 /* Implementation of emit_ops method "emit_mul". */
2286 aarch64_emit_mul (void)
2291 p
+= emit_pop (p
, x1
);
2292 p
+= emit_mul (p
, x0
, x1
, x0
);
2294 emit_ops_insns (buf
, p
- buf
);
2297 /* Implementation of emit_ops method "emit_lsh". */
2300 aarch64_emit_lsh (void)
2305 p
+= emit_pop (p
, x1
);
2306 p
+= emit_lslv (p
, x0
, x1
, x0
);
2308 emit_ops_insns (buf
, p
- buf
);
2311 /* Implementation of emit_ops method "emit_rsh_signed". */
2314 aarch64_emit_rsh_signed (void)
2319 p
+= emit_pop (p
, x1
);
2320 p
+= emit_asrv (p
, x0
, x1
, x0
);
2322 emit_ops_insns (buf
, p
- buf
);
2325 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2328 aarch64_emit_rsh_unsigned (void)
2333 p
+= emit_pop (p
, x1
);
2334 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2336 emit_ops_insns (buf
, p
- buf
);
2339 /* Implementation of emit_ops method "emit_ext". */
2342 aarch64_emit_ext (int arg
)
2347 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2349 emit_ops_insns (buf
, p
- buf
);
2352 /* Implementation of emit_ops method "emit_log_not". */
2355 aarch64_emit_log_not (void)
2360 /* If the top of the stack is 0, replace it with 1. Else replace it with
2363 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2364 p
+= emit_cset (p
, x0
, EQ
);
2366 emit_ops_insns (buf
, p
- buf
);
2369 /* Implementation of emit_ops method "emit_bit_and". */
2372 aarch64_emit_bit_and (void)
2377 p
+= emit_pop (p
, x1
);
2378 p
+= emit_and (p
, x0
, x0
, x1
);
2380 emit_ops_insns (buf
, p
- buf
);
2383 /* Implementation of emit_ops method "emit_bit_or". */
2386 aarch64_emit_bit_or (void)
2391 p
+= emit_pop (p
, x1
);
2392 p
+= emit_orr (p
, x0
, x0
, x1
);
2394 emit_ops_insns (buf
, p
- buf
);
2397 /* Implementation of emit_ops method "emit_bit_xor". */
2400 aarch64_emit_bit_xor (void)
2405 p
+= emit_pop (p
, x1
);
2406 p
+= emit_eor (p
, x0
, x0
, x1
);
2408 emit_ops_insns (buf
, p
- buf
);
2411 /* Implementation of emit_ops method "emit_bit_not". */
2414 aarch64_emit_bit_not (void)
2419 p
+= emit_mvn (p
, x0
, x0
);
2421 emit_ops_insns (buf
, p
- buf
);
2424 /* Implementation of emit_ops method "emit_equal". */
2427 aarch64_emit_equal (void)
2432 p
+= emit_pop (p
, x1
);
2433 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2434 p
+= emit_cset (p
, x0
, EQ
);
2436 emit_ops_insns (buf
, p
- buf
);
2439 /* Implementation of emit_ops method "emit_less_signed". */
2442 aarch64_emit_less_signed (void)
2447 p
+= emit_pop (p
, x1
);
2448 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2449 p
+= emit_cset (p
, x0
, LT
);
2451 emit_ops_insns (buf
, p
- buf
);
2454 /* Implementation of emit_ops method "emit_less_unsigned". */
2457 aarch64_emit_less_unsigned (void)
2462 p
+= emit_pop (p
, x1
);
2463 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2464 p
+= emit_cset (p
, x0
, LO
);
2466 emit_ops_insns (buf
, p
- buf
);
2469 /* Implementation of emit_ops method "emit_ref". */
2472 aarch64_emit_ref (int size
)
2480 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2483 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2486 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2489 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2492 /* Unknown size, bail on compilation. */
2497 emit_ops_insns (buf
, p
- buf
);
2500 /* Implementation of emit_ops method "emit_if_goto". */
2503 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2508 /* The Z flag is set or cleared here. */
2509 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2510 /* This instruction must not change the Z flag. */
2511 p
+= emit_pop (p
, x0
);
2512 /* Branch over the next instruction if x0 == 0. */
2513 p
+= emit_bcond (p
, EQ
, 8);
2515 /* The NOP instruction will be patched with an unconditional branch. */
2517 *offset_p
= (p
- buf
) * 4;
2522 emit_ops_insns (buf
, p
- buf
);
2525 /* Implementation of emit_ops method "emit_goto". */
2528 aarch64_emit_goto (int *offset_p
, int *size_p
)
2533 /* The NOP instruction will be patched with an unconditional branch. */
2540 emit_ops_insns (buf
, p
- buf
);
2543 /* Implementation of emit_ops method "write_goto_address". */
2546 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2550 emit_b (&insn
, 0, to
- from
);
2551 append_insns (&from
, 1, &insn
);
2554 /* Implementation of emit_ops method "emit_const". */
2557 aarch64_emit_const (LONGEST num
)
2562 p
+= emit_mov_addr (p
, x0
, num
);
2564 emit_ops_insns (buf
, p
- buf
);
2567 /* Implementation of emit_ops method "emit_call". */
2570 aarch64_emit_call (CORE_ADDR fn
)
2575 p
+= emit_mov_addr (p
, ip0
, fn
);
2576 p
+= emit_blr (p
, ip0
);
2578 emit_ops_insns (buf
, p
- buf
);
2581 /* Implementation of emit_ops method "emit_reg". */
2584 aarch64_emit_reg (int reg
)
2589 /* Set x0 to unsigned char *regs. */
2590 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2591 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2592 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2594 emit_ops_insns (buf
, p
- buf
);
2596 aarch64_emit_call (get_raw_reg_func_addr ());
2599 /* Implementation of emit_ops method "emit_pop". */
2602 aarch64_emit_pop (void)
2607 p
+= emit_pop (p
, x0
);
2609 emit_ops_insns (buf
, p
- buf
);
2612 /* Implementation of emit_ops method "emit_stack_flush". */
2615 aarch64_emit_stack_flush (void)
2620 p
+= emit_push (p
, x0
);
2622 emit_ops_insns (buf
, p
- buf
);
2625 /* Implementation of emit_ops method "emit_zero_ext". */
2628 aarch64_emit_zero_ext (int arg
)
2633 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2635 emit_ops_insns (buf
, p
- buf
);
2638 /* Implementation of emit_ops method "emit_swap". */
2641 aarch64_emit_swap (void)
2646 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2647 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2648 p
+= emit_mov (p
, x0
, register_operand (x1
));
2650 emit_ops_insns (buf
, p
- buf
);
2653 /* Implementation of emit_ops method "emit_stack_adjust". */
2656 aarch64_emit_stack_adjust (int n
)
2658 /* This is not needed with our design. */
2662 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2664 emit_ops_insns (buf
, p
- buf
);
2667 /* Implementation of emit_ops method "emit_int_call_1". */
2670 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2675 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2677 emit_ops_insns (buf
, p
- buf
);
2679 aarch64_emit_call (fn
);
2682 /* Implementation of emit_ops method "emit_void_call_2". */
2685 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2690 /* Push x0 on the stack. */
2691 aarch64_emit_stack_flush ();
2693 /* Setup arguments for the function call:
2696 x1: top of the stack
2701 p
+= emit_mov (p
, x1
, register_operand (x0
));
2702 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2704 emit_ops_insns (buf
, p
- buf
);
2706 aarch64_emit_call (fn
);
2709 aarch64_emit_pop ();
2712 /* Implementation of emit_ops method "emit_eq_goto". */
2715 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
2720 p
+= emit_pop (p
, x1
);
2721 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2722 /* Branch over the next instruction if x0 != x1. */
2723 p
+= emit_bcond (p
, NE
, 8);
2724 /* The NOP instruction will be patched with an unconditional branch. */
2726 *offset_p
= (p
- buf
) * 4;
2731 emit_ops_insns (buf
, p
- buf
);
2734 /* Implementation of emit_ops method "emit_ne_goto". */
2737 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
2742 p
+= emit_pop (p
, x1
);
2743 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2744 /* Branch over the next instruction if x0 == x1. */
2745 p
+= emit_bcond (p
, EQ
, 8);
2746 /* The NOP instruction will be patched with an unconditional branch. */
2748 *offset_p
= (p
- buf
) * 4;
2753 emit_ops_insns (buf
, p
- buf
);
2756 /* Implementation of emit_ops method "emit_lt_goto". */
2759 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
2764 p
+= emit_pop (p
, x1
);
2765 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2766 /* Branch over the next instruction if x0 >= x1. */
2767 p
+= emit_bcond (p
, GE
, 8);
2768 /* The NOP instruction will be patched with an unconditional branch. */
2770 *offset_p
= (p
- buf
) * 4;
2775 emit_ops_insns (buf
, p
- buf
);
2778 /* Implementation of emit_ops method "emit_le_goto". */
2781 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
2786 p
+= emit_pop (p
, x1
);
2787 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2788 /* Branch over the next instruction if x0 > x1. */
2789 p
+= emit_bcond (p
, GT
, 8);
2790 /* The NOP instruction will be patched with an unconditional branch. */
2792 *offset_p
= (p
- buf
) * 4;
2797 emit_ops_insns (buf
, p
- buf
);
2800 /* Implementation of emit_ops method "emit_gt_goto". */
2803 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
2808 p
+= emit_pop (p
, x1
);
2809 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2810 /* Branch over the next instruction if x0 <= x1. */
2811 p
+= emit_bcond (p
, LE
, 8);
2812 /* The NOP instruction will be patched with an unconditional branch. */
2814 *offset_p
= (p
- buf
) * 4;
2819 emit_ops_insns (buf
, p
- buf
);
2822 /* Implementation of emit_ops method "emit_ge_got". */
2825 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
2830 p
+= emit_pop (p
, x1
);
2831 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2832 /* Branch over the next instruction if x0 <= x1. */
2833 p
+= emit_bcond (p
, LT
, 8);
2834 /* The NOP instruction will be patched with an unconditional branch. */
2836 *offset_p
= (p
- buf
) * 4;
2841 emit_ops_insns (buf
, p
- buf
);
2844 static struct emit_ops aarch64_emit_ops_impl
=
2846 aarch64_emit_prologue
,
2847 aarch64_emit_epilogue
,
2852 aarch64_emit_rsh_signed
,
2853 aarch64_emit_rsh_unsigned
,
2855 aarch64_emit_log_not
,
2856 aarch64_emit_bit_and
,
2857 aarch64_emit_bit_or
,
2858 aarch64_emit_bit_xor
,
2859 aarch64_emit_bit_not
,
2861 aarch64_emit_less_signed
,
2862 aarch64_emit_less_unsigned
,
2864 aarch64_emit_if_goto
,
2866 aarch64_write_goto_address
,
2871 aarch64_emit_stack_flush
,
2872 aarch64_emit_zero_ext
,
2874 aarch64_emit_stack_adjust
,
2875 aarch64_emit_int_call_1
,
2876 aarch64_emit_void_call_2
,
2877 aarch64_emit_eq_goto
,
2878 aarch64_emit_ne_goto
,
2879 aarch64_emit_lt_goto
,
2880 aarch64_emit_le_goto
,
2881 aarch64_emit_gt_goto
,
2882 aarch64_emit_ge_got
,
2885 /* Implementation of linux_target_ops method "emit_ops". */
2887 static struct emit_ops
*
2888 aarch64_emit_ops (void)
2890 return &aarch64_emit_ops_impl
;
2893 /* Implementation of linux_target_ops method
2894 "get_min_fast_tracepoint_insn_len". */
2897 aarch64_get_min_fast_tracepoint_insn_len (void)
2902 /* Implementation of linux_target_ops method "supports_range_stepping". */
2905 aarch64_supports_range_stepping (void)
2910 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2912 static const gdb_byte
*
2913 aarch64_sw_breakpoint_from_kind (int kind
, int *size
)
2915 if (is_64bit_tdesc ())
2917 *size
= aarch64_breakpoint_len
;
2918 return aarch64_breakpoint
;
2921 return arm_sw_breakpoint_from_kind (kind
, size
);
2924 /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */
2927 aarch64_breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
2929 if (is_64bit_tdesc ())
2930 return aarch64_breakpoint_len
;
2932 return arm_breakpoint_kind_from_pc (pcptr
);
2935 /* Implementation of the linux_target_ops method
2936 "breakpoint_kind_from_current_state". */
2939 aarch64_breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
2941 if (is_64bit_tdesc ())
2942 return aarch64_breakpoint_len
;
2944 return arm_breakpoint_kind_from_current_state (pcptr
);
2947 /* Support for hardware single step. */
2950 aarch64_supports_hardware_single_step (void)
2955 struct linux_target_ops the_low_target
=
2959 aarch64_cannot_fetch_register
,
2960 aarch64_cannot_store_register
,
2961 NULL
, /* fetch_register */
2964 aarch64_breakpoint_kind_from_pc
,
2965 aarch64_sw_breakpoint_from_kind
,
2966 NULL
, /* get_next_pcs */
2967 0, /* decr_pc_after_break */
2968 aarch64_breakpoint_at
,
2969 aarch64_supports_z_point_type
,
2970 aarch64_insert_point
,
2971 aarch64_remove_point
,
2972 aarch64_stopped_by_watchpoint
,
2973 aarch64_stopped_data_address
,
2974 NULL
, /* collect_ptrace_register */
2975 NULL
, /* supply_ptrace_register */
2976 aarch64_linux_siginfo_fixup
,
2977 aarch64_linux_new_process
,
2978 aarch64_linux_delete_process
,
2979 aarch64_linux_new_thread
,
2980 aarch64_linux_delete_thread
,
2981 aarch64_linux_new_fork
,
2982 aarch64_linux_prepare_to_resume
,
2983 NULL
, /* process_qsupported */
2984 aarch64_supports_tracepoints
,
2985 aarch64_get_thread_area
,
2986 aarch64_install_fast_tracepoint_jump_pad
,
2988 aarch64_get_min_fast_tracepoint_insn_len
,
2989 aarch64_supports_range_stepping
,
2990 aarch64_breakpoint_kind_from_current_state
,
2991 aarch64_supports_hardware_single_step
,
2992 aarch64_get_syscall_trapinfo
,
2996 initialize_low_arch (void)
2998 initialize_low_arch_aarch32 ();
3000 initialize_regsets_info (&aarch64_regsets_info
);
3003 initialize_low_tdesc ();