gdb/gdbserver/linux-crisv32-low.c

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Defined in auto-generated file reg-crisv32.c.  */
  24 void init_registers_crisv32 (void);
  25 extern const struct target_desc *tdesc_crisv32;
  26
  27 /* CRISv32 */
  28 #define cris_num_regs 49
  29
  30 #ifndef PTRACE_GET_THREAD_AREA
  31 #define PTRACE_GET_THREAD_AREA 25
  32 #endif
  33
  34 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  35    without any significant gain).  */
  36
  37 /* Locations need to match <include/asm/arch/ptrace.h>.  */
  38 static int cris_regmap[] = {
  39   1*4, 2*4, 3*4, 4*4,
  40   5*4, 6*4, 7*4, 8*4,
  41   9*4, 10*4, 11*4, 12*4,
  42   13*4, 14*4, 24*4, 15*4,
  43
  44   -1, -1, -1, 16*4,
  45   -1, 22*4, 23*4, 17*4,
  46   -1, -1, 21*4, 20*4,
  47   -1, 19*4, -1, 18*4,
  48
  49   25*4,
  50
  51   26*4, -1,   -1,   29*4,
  52   30*4, 31*4, 32*4, 33*4,
  53   34*4, 35*4, 36*4, 37*4,
  54   38*4, 39*4, 40*4, -1
  55
  56 };
  57
  58 extern int debug_threads;
  59
  60 static CORE_ADDR
  61 cris_get_pc (struct regcache *regcache)
  62 {
  63   unsigned long pc;
  64   collect_register_by_name (regcache, "pc", &pc);
  65   if (debug_threads)
  66     debug_printf ("stop pc is %08lx\n", pc);
  67   return pc;
  68 }
  69
  70 static void
  71 cris_set_pc (struct regcache *regcache, CORE_ADDR pc)
  72 {
  73   unsigned long newpc = pc;
  74   supply_register_by_name (regcache, "pc", &newpc);
  75 }
  76
  77 static const unsigned short cris_breakpoint = 0xe938;
  78 #define cris_breakpoint_len 2
  79
  80 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
  81
  82 static const gdb_byte *
  83 cris_sw_breakpoint_from_kind (int kind, int *size)
  84 {
  85   *size = cris_breakpoint_len;
  86   return (const gdb_byte *) &cris_breakpoint;
  87 }
  88
  89 static int
  90 cris_breakpoint_at (CORE_ADDR where)
  91 {
  92   unsigned short insn;
  93
  94   (*the_target->read_memory) (where, (unsigned char *) &insn,
  95                               cris_breakpoint_len);
  96   if (insn == cris_breakpoint)
  97     return 1;
  98
  99   /* If necessary, recognize more trap instructions here.  GDB only uses the
 100      one.  */
 101   return 0;
 102 }
 103
 104 /* We only place breakpoints in empty marker functions, and thread locking
 105    is outside of the function.  So rather than importing software single-step,
 106    we can just run until exit.  */
 107
 108 /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
 109    for CRISv32.  Without it, td_ta_event_getmsg in thread_db_create_event
 110    will fail when debugging multi-threaded applications.  */
 111
 112 static CORE_ADDR
 113 cris_reinsert_addr (void)
 114 {
 115   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 116   unsigned long pc;
 117   collect_register_by_name (regcache, "srp", &pc);
 118   return pc;
 119 }
 120
 121 static void
 122 cris_write_data_breakpoint (struct regcache *regcache,
 123                             int bp, unsigned long start, unsigned long end)
 124 {
 125   switch (bp)
 126     {
 127     case 0:
 128       supply_register_by_name (regcache, "s3", &start);
 129       supply_register_by_name (regcache, "s4", &end);
 130       break;
 131     case 1:
 132       supply_register_by_name (regcache, "s5", &start);
 133       supply_register_by_name (regcache, "s6", &end);
 134       break;
 135     case 2:
 136       supply_register_by_name (regcache, "s7", &start);
 137       supply_register_by_name (regcache, "s8", &end);
 138       break;
 139     case 3:
 140       supply_register_by_name (regcache, "s9", &start);
 141       supply_register_by_name (regcache, "s10", &end);
 142       break;
 143     case 4:
 144       supply_register_by_name (regcache, "s11", &start);
 145       supply_register_by_name (regcache, "s12", &end);
 146       break;
 147     case 5:
 148       supply_register_by_name (regcache, "s13", &start);
 149       supply_register_by_name (regcache, "s14", &end);
 150       break;
 151     }
 152 }
 153
 154 static int
 155 cris_supports_z_point_type (char z_type)
 156 {
 157   switch (z_type)
 158     {
 159     case Z_PACKET_WRITE_WP:
 160     case Z_PACKET_READ_WP:
 161     case Z_PACKET_ACCESS_WP:
 162       return 1;
 163     default:
 164       return 0;
 165     }
 166 }
 167
 168 static int
 169 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 170                    int len, struct raw_breakpoint *bp)
 171 {
 172   int bp;
 173   unsigned long bp_ctrl;
 174   unsigned long start, end;
 175   unsigned long ccs;
 176   struct regcache *regcache;
 177
 178   regcache = get_thread_regcache (current_thread, 1);
 179
 180   /* Read watchpoints are set as access watchpoints, because of GDB's
 181      inability to deal with pure read watchpoints.  */
 182   if (type == raw_bkpt_type_read_wp)
 183     type = raw_bkpt_type_access_wp;
 184
 185   /* Get the configuration register.  */
 186   collect_register_by_name (regcache, "s0", &bp_ctrl);
 187
 188   /* The watchpoint allocation scheme is the simplest possible.
 189      For example, if a region is watched for read and
 190      a write watch is requested, a new watchpoint will
 191      be used.  Also, if a watch for a region that is already
 192      covered by one or more existing watchpoints, a new
 193      watchpoint will be used.  */
 194
 195   /* First, find a free data watchpoint.  */
 196   for (bp = 0; bp < 6; bp++)
 197     {
 198       /* Each data watchpoint's control registers occupy 2 bits
 199          (hence the 3), starting at bit 2 for D0 (hence the 2)
 200          with 4 bits between for each watchpoint (yes, the 4).  */
 201       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 202         break;
 203     }
 204
 205   if (bp > 5)
 206     {
 207       /* We're out of watchpoints.  */
 208       return -1;
 209     }
 210
 211   /* Configure the control register first.  */
 212   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 213     {
 214       /* Trigger on read.  */
 215       bp_ctrl |= (1 << (2 + bp * 4));
 216     }
 217   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 218     {
 219       /* Trigger on write.  */
 220       bp_ctrl |= (2 << (2 + bp * 4));
 221     }
 222
 223   /* Setup the configuration register.  */
 224   supply_register_by_name (regcache, "s0", &bp_ctrl);
 225
 226   /* Setup the range.  */
 227   start = addr;
 228   end = addr + len - 1;
 229
 230   /* Configure the watchpoint register.  */
 231   cris_write_data_breakpoint (regcache, bp, start, end);
 232
 233   collect_register_by_name (regcache, "ccs", &ccs);
 234   /* Set the S1 flag to enable watchpoints.  */
 235   ccs |= (1 << 19);
 236   supply_register_by_name (regcache, "ccs", &ccs);
 237
 238   return 0;
 239 }
 240
 241 static int
 242 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 243                    struct raw_breakpoint *bp)
 244 {
 245   int bp;
 246   unsigned long bp_ctrl;
 247   unsigned long start, end;
 248   struct regcache *regcache;
 249   unsigned long bp_d_regs[12];
 250
 251   regcache = get_thread_regcache (current_thread, 1);
 252
 253   /* Read watchpoints are set as access watchpoints, because of GDB's
 254      inability to deal with pure read watchpoints.  */
 255   if (type == raw_bkpt_type_read_wp)
 256     type = raw_bkpt_type_access_wp;
 257
 258   /* Get the configuration register.  */
 259   collect_register_by_name (regcache, "s0", &bp_ctrl);
 260
 261   /* Try to find a watchpoint that is configured for the
 262      specified range, then check that read/write also matches.  */
 263
 264   /* Ugly pointer arithmetic, since I cannot rely on a
 265      single switch (addr) as there may be several watchpoints with
 266      the same start address for example.  */
 267
 268   /* Get all range registers to simplify search.  */
 269   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 270   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 271   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 272   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 273   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 274   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 275   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 276   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 277   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 278   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 279   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 280   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 281
 282   for (bp = 0; bp < 6; bp++)
 283     {
 284       if (bp_d_regs[bp * 2] == addr
 285           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 286         /* Matching range.  */
 287         int bitpos = 2 + bp * 4;
 288         int rw_bits;
 289
 290         /* Read/write bits for this BP.  */
 291         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 292
 293         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 294             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 295             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 296           {
 297             /* Read/write matched.  */
 298             break;
 299           }
 300       }
 301     }
 302
 303   if (bp > 5)
 304     {
 305       /* No watchpoint matched.  */
 306       return -1;
 307     }
 308
 309   /* Found a matching watchpoint.  Now, deconfigure it by
 310      both disabling read/write in bp_ctrl and zeroing its
 311      start/end addresses.  */
 312   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 313   /* Setup the configuration register.  */
 314   supply_register_by_name (regcache, "s0", &bp_ctrl);
 315
 316   start = end = 0;
 317   /* Configure the watchpoint register.  */
 318   cris_write_data_breakpoint (regcache, bp, start, end);
 319
 320   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 321   return 0;
 322 }
 323
 324 static int
 325 cris_stopped_by_watchpoint (void)
 326 {
 327   unsigned long exs;
 328   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 329
 330   collect_register_by_name (regcache, "exs", &exs);
 331
 332   return (((exs & 0xff00) >> 8) == 0xc);
 333 }
 334
 335 static CORE_ADDR
 336 cris_stopped_data_address (void)
 337 {
 338   unsigned long eda;
 339   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 340
 341   collect_register_by_name (regcache, "eda", &eda);
 342
 343   /* FIXME: Possibly adjust to match watched range.  */
 344   return eda;
 345 }
 346
 347 ps_err_e
 348 ps_get_thread_area (const struct ps_prochandle *ph,
 349                     lwpid_t lwpid, int idx, void **base)
 350 {
 351   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 352     return PS_ERR;
 353
 354   /* IDX is the bias from the thread pointer to the beginning of the
 355      thread descriptor.  It has to be subtracted due to implementation
 356      quirks in libthread_db.  */
 357   *base = (void *) ((char *) *base - idx);
 358   return PS_OK;
 359 }
 360
 361 static void
 362 cris_fill_gregset (struct regcache *regcache, void *buf)
 363 {
 364   int i;
 365
 366   for (i = 0; i < cris_num_regs; i++)
 367     {
 368       if (cris_regmap[i] != -1)
 369         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 370     }
 371 }
 372
 373 static void
 374 cris_store_gregset (struct regcache *regcache, const void *buf)
 375 {
 376   int i;
 377
 378   for (i = 0; i < cris_num_regs; i++)
 379     {
 380       if (cris_regmap[i] != -1)
 381         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 382     }
 383 }
 384
 385 static void
 386 cris_arch_setup (void)
 387 {
 388   current_process ()->tdesc = tdesc_crisv32;
 389 }
 390
 391 static struct regset_info cris_regsets[] = {
 392   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 393     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 394   { 0, 0, 0, -1, -1, NULL, NULL }
 395 };
 396
 397
 398 static struct regsets_info cris_regsets_info =
 399   {
 400     cris_regsets, /* regsets */
 401     0, /* num_regsets */
 402     NULL, /* disabled_regsets */
 403   };
 404
 405 static struct usrregs_info cris_usrregs_info =
 406   {
 407     cris_num_regs,
 408     cris_regmap,
 409   };
 410
 411 static struct regs_info regs_info =
 412   {
 413     NULL, /* regset_bitmap */
 414     &cris_usrregs_info,
 415     &cris_regsets_info
 416   };
 417
 418 static const struct regs_info *
 419 cris_regs_info (void)
 420 {
 421   return &regs_info;
 422 }
 423
 424 struct linux_target_ops the_low_target = {
 425   cris_arch_setup,
 426   cris_regs_info,
 427   NULL,
 428   NULL,
 429   NULL, /* fetch_register */
 430   cris_get_pc,
 431   cris_set_pc,
 432   NULL, /* breakpoint_kind_from_pc */
 433   cris_sw_breakpoint_from_kind,
 434   cris_reinsert_addr,
 435   0,
 436   cris_breakpoint_at,
 437   cris_supports_z_point_type,
 438   cris_insert_point,
 439   cris_remove_point,
 440   cris_stopped_by_watchpoint,
 441   cris_stopped_data_address,
 442 };
 443
 444 void
 445 initialize_low_arch (void)
 446 {
 447   init_registers_crisv32 ();
 448
 449   initialize_regsets_info (&cris_regsets_info);
 450 }