gdb/gdbserver/linux-mips-low.c

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2014 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include <sys/ptrace.h>
  23 #include <endian.h>
  24
  25 #include "mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Defined in auto-generated file mips-linux.c.  */
  29 void init_registers_mips_linux (void);
  30 extern const struct target_desc *tdesc_mips_linux;
  31
  32 /* Defined in auto-generated file mips-dsp-linux.c.  */
  33 void init_registers_mips_dsp_linux (void);
  34 extern const struct target_desc *tdesc_mips_dsp_linux;
  35
  36 /* Defined in auto-generated file mips64-linux.c.  */
  37 void init_registers_mips64_linux (void);
  38 extern const struct target_desc *tdesc_mips64_linux;
  39
  40 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  41 void init_registers_mips64_dsp_linux (void);
  42 extern const struct target_desc *tdesc_mips64_dsp_linux;
  43
  44 #ifdef __mips64
  45 #define tdesc_mips_linux tdesc_mips64_linux
  46 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  47 #endif
  48
  49 #ifndef PTRACE_GET_THREAD_AREA
  50 #define PTRACE_GET_THREAD_AREA 25
  51 #endif
  52
  53 #ifdef HAVE_SYS_REG_H
  54 #include <sys/reg.h>
  55 #endif
  56
  57 #define mips_num_regs 73
  58 #define mips_dsp_num_regs 80
  59
  60 #include <asm/ptrace.h>
  61
  62 #ifndef DSP_BASE
  63 #define DSP_BASE 71
  64 #define DSP_CONTROL 77
  65 #endif
  66
  67 union mips_register
  68 {
  69   unsigned char buf[8];
  70
  71   /* Deliberately signed, for proper sign extension.  */
  72   int reg32;
  73   long long reg64;
  74 };
  75
  76 /* Return the ptrace ``address'' of register REGNO. */
  77
  78 #define mips_base_regs                                                  \
  79   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
  80   8,  9,  10, 11, 12, 13, 14, 15,                                       \
  81   16, 17, 18, 19, 20, 21, 22, 23,                                       \
  82   24, 25, 26, 27, 28, 29, 30, 31,                                       \
  83                                                                         \
  84   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
  85                                                                         \
  86   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
  87   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
  88   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
  89   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
  90   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
  91   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
  92   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
  93   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
  94   FPC_CSR, FPC_EIR
  95
  96 #define mips_dsp_regs                                                   \
  97   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
  98   DSP_BASE + 4,  DSP_BASE + 5,                                          \
  99   DSP_CONTROL
 100
 101 static int mips_regmap[mips_num_regs] = {
 102   mips_base_regs,
 103   0
 104 };
 105
 106 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 107   mips_base_regs,
 108   mips_dsp_regs,
 109   0
 110 };
 111
 112 /* DSP registers are not in any regset and can only be accessed
 113    individually.  */
 114
 115 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 116   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 117 };
 118
 119 static int have_dsp = -1;
 120
 121 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 122    user register set accordingly.  */
 123
 124 static const struct target_desc *
 125 mips_read_description (void)
 126 {
 127   if (have_dsp < 0)
 128     {
 129       int pid = lwpid_of (current_inferior);
 130
 131       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 132       switch (errno)
 133         {
 134         case 0:
 135           have_dsp = 1;
 136           break;
 137         case EIO:
 138           have_dsp = 0;
 139           break;
 140         default:
 141           perror_with_name ("ptrace");
 142           break;
 143         }
 144     }
 145
 146   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 147 }
 148
 149 static void
 150 mips_arch_setup (void)
 151 {
 152   current_process ()->tdesc = mips_read_description ();
 153 }
 154
 155 static struct usrregs_info *
 156 get_usrregs_info (void)
 157 {
 158   const struct regs_info *regs_info = the_low_target.regs_info ();
 159
 160   return regs_info->usrregs;
 161 }
 162
 163 /* Per-process arch-specific data we want to keep.  */
 164
 165 struct arch_process_info
 166 {
 167   /* -1 if the kernel and/or CPU do not support watch registers.
 168       1 if watch_readback is valid and we can read style, num_valid
 169         and the masks.
 170       0 if we need to read the watch_readback.  */
 171
 172   int watch_readback_valid;
 173
 174   /* Cached watch register read values.  */
 175
 176   struct pt_watch_regs watch_readback;
 177
 178   /* Current watchpoint requests for this process.  */
 179
 180   struct mips_watchpoint *current_watches;
 181
 182   /* The current set of watch register values for writing the
 183      registers.  */
 184
 185   struct pt_watch_regs watch_mirror;
 186 };
 187
 188 /* Per-thread arch-specific data we want to keep.  */
 189
 190 struct arch_lwp_info
 191 {
 192   /* Non-zero if our copy differs from what's recorded in the thread.  */
 193   int watch_registers_changed;
 194 };
 195
 196 /* From mips-linux-nat.c.  */
 197
 198 /* Pseudo registers can not be read.  ptrace does not provide a way to
 199    read (or set) PS_REGNUM, and there's no point in reading or setting
 200    ZERO_REGNUM.  We also can not set BADVADDR, CAUSE, or FCRIR via
 201    ptrace().  */
 202
 203 static int
 204 mips_cannot_fetch_register (int regno)
 205 {
 206   const struct target_desc *tdesc;
 207
 208   if (get_usrregs_info ()->regmap[regno] == -1)
 209     return 1;
 210
 211   tdesc = current_process ()->tdesc;
 212
 213   if (find_regno (tdesc, "r0") == regno)
 214     return 1;
 215
 216   return 0;
 217 }
 218
 219 static int
 220 mips_cannot_store_register (int regno)
 221 {
 222   const struct target_desc *tdesc;
 223
 224   if (get_usrregs_info ()->regmap[regno] == -1)
 225     return 1;
 226
 227   tdesc = current_process ()->tdesc;
 228
 229   if (find_regno (tdesc, "r0") == regno)
 230     return 1;
 231
 232   if (find_regno (tdesc, "cause") == regno)
 233     return 1;
 234
 235   if (find_regno (tdesc, "badvaddr") == regno)
 236     return 1;
 237
 238   if (find_regno (tdesc, "fir") == regno)
 239     return 1;
 240
 241   return 0;
 242 }
 243
 244 static CORE_ADDR
 245 mips_get_pc (struct regcache *regcache)
 246 {
 247   union mips_register pc;
 248   collect_register_by_name (regcache, "pc", pc.buf);
 249   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 250 }
 251
 252 static void
 253 mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
 254 {
 255   union mips_register newpc;
 256   if (register_size (regcache->tdesc, 0) == 4)
 257     newpc.reg32 = pc;
 258   else
 259     newpc.reg64 = pc;
 260
 261   supply_register_by_name (regcache, "pc", newpc.buf);
 262 }
 263
 264 /* Correct in either endianness.  */
 265 static const unsigned int mips_breakpoint = 0x0005000d;
 266 #define mips_breakpoint_len 4
 267
 268 /* We only place breakpoints in empty marker functions, and thread locking
 269    is outside of the function.  So rather than importing software single-step,
 270    we can just run until exit.  */
 271 static CORE_ADDR
 272 mips_reinsert_addr (void)
 273 {
 274   struct regcache *regcache = get_thread_regcache (current_inferior, 1);
 275   union mips_register ra;
 276   collect_register_by_name (regcache, "r31", ra.buf);
 277   return register_size (regcache->tdesc, 0) == 4 ? ra.reg32 : ra.reg64;
 278 }
 279
 280 static int
 281 mips_breakpoint_at (CORE_ADDR where)
 282 {
 283   unsigned int insn;
 284
 285   (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
 286   if (insn == mips_breakpoint)
 287     return 1;
 288
 289   /* If necessary, recognize more trap instructions here.  GDB only uses the
 290      one.  */
 291   return 0;
 292 }
 293
 294 /* Mark the watch registers of lwp, represented by ENTRY, as changed,
 295    if the lwp's process id is *PID_P.  */
 296
 297 static int
 298 update_watch_registers_callback (struct inferior_list_entry *entry,
 299                                  void *pid_p)
 300 {
 301   struct thread_info *thread = (struct thread_info *) entry;
 302   struct lwp_info *lwp = get_thread_lwp (thread);
 303   int pid = *(int *) pid_p;
 304
 305   /* Only update the threads of this process.  */
 306   if (pid_of (thread) == pid)
 307     {
 308       /* The actual update is done later just before resuming the lwp,
 309          we just mark that the registers need updating.  */
 310       lwp->arch_private->watch_registers_changed = 1;
 311
 312       /* If the lwp isn't stopped, force it to momentarily pause, so
 313          we can update its watch registers.  */
 314       if (!lwp->stopped)
 315         linux_stop_lwp (lwp);
 316     }
 317
 318   return 0;
 319 }
 320
 321 /* This is the implementation of linux_target_ops method
 322    new_process.  */
 323
 324 static struct arch_process_info *
 325 mips_linux_new_process (void)
 326 {
 327   struct arch_process_info *info = xcalloc (1, sizeof (*info));
 328
 329   return info;
 330 }
 331
 332 /* This is the implementation of linux_target_ops method new_thread.
 333    Mark the watch registers as changed, so the threads' copies will
 334    be updated.  */
 335
 336 static struct arch_lwp_info *
 337 mips_linux_new_thread (void)
 338 {
 339   struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
 340
 341   info->watch_registers_changed = 1;
 342
 343   return info;
 344 }
 345
 346 /* This is the implementation of linux_target_ops method
 347    prepare_to_resume.  If the watch regs have changed, update the
 348    thread's copies.  */
 349
 350 static void
 351 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 352 {
 353   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 354   struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
 355   struct arch_process_info *private = proc->private->arch_private;
 356
 357   if (lwp->arch_private->watch_registers_changed)
 358     {
 359       /* Only update the watch registers if we have set or unset a
 360          watchpoint already.  */
 361       if (mips_linux_watch_get_num_valid (&private->watch_mirror) > 0)
 362         {
 363           /* Write the mirrored watch register values.  */
 364           int tid = ptid_get_lwp (ptid);
 365
 366           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 367                             &private->watch_mirror))
 368             perror_with_name ("Couldn't write watch register");
 369         }
 370
 371       lwp->arch_private->watch_registers_changed = 0;
 372     }
 373 }
 374
 375 /* Translate breakpoint type TYPE in rsp to 'enum target_hw_bp_type'.  */
 376
 377 static enum target_hw_bp_type
 378 rsp_bp_type_to_target_hw_bp_type (char type)
 379 {
 380   switch (type)
 381     {
 382     case '2':
 383       return hw_write;
 384     case '3':
 385       return hw_read;
 386     case '4':
 387       return hw_access;
 388     }
 389
 390   gdb_assert_not_reached ("unhandled RSP breakpoint type");
 391 }
 392
 393 /* This is the implementation of linux_target_ops method
 394    insert_point.  */
 395
 396 static int
 397 mips_insert_point (char type, CORE_ADDR addr, int len)
 398 {
 399   struct process_info *proc = current_process ();
 400   struct arch_process_info *private = proc->private->arch_private;
 401   struct pt_watch_regs regs;
 402   struct mips_watchpoint *new_watch;
 403   struct mips_watchpoint **pw;
 404   int pid;
 405   long lwpid;
 406   enum target_hw_bp_type watch_type;
 407   uint32_t irw;
 408
 409   /* Breakpoint/watchpoint types:
 410        '0' - software-breakpoint (not supported)
 411        '1' - hardware-breakpoint (not supported)
 412        '2' - write watchpoint (supported)
 413        '3' - read watchpoint (supported)
 414        '4' - access watchpoint (supported).  */
 415
 416   if (type < '2' || type > '4')
 417     {
 418       /* Unsupported.  */
 419       return 1;
 420     }
 421
 422   lwpid = lwpid_of (current_inferior);
 423   if (!mips_linux_read_watch_registers (lwpid,
 424                                         &private->watch_readback,
 425                                         &private->watch_readback_valid,
 426                                         0))
 427     return -1;
 428
 429   if (len <= 0)
 430     return -1;
 431
 432   regs = private->watch_readback;
 433   /* Add the current watches.  */
 434   mips_linux_watch_populate_regs (private->current_watches, &regs);
 435
 436   /* Now try to add the new watch.  */
 437   watch_type = rsp_bp_type_to_target_hw_bp_type (type);
 438   irw = mips_linux_watch_type_to_irw (watch_type);
 439   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 440     return -1;
 441
 442   /* It fit.  Stick it on the end of the list.  */
 443   new_watch = xmalloc (sizeof (struct mips_watchpoint));
 444   new_watch->addr = addr;
 445   new_watch->len = len;
 446   new_watch->type = watch_type;
 447   new_watch->next = NULL;
 448
 449   pw = &private->current_watches;
 450   while (*pw != NULL)
 451     pw = &(*pw)->next;
 452   *pw = new_watch;
 453
 454   private->watch_mirror = regs;
 455
 456   /* Only update the threads of this process.  */
 457   pid = pid_of (proc);
 458   find_inferior (&all_threads, update_watch_registers_callback, &pid);
 459
 460   return 0;
 461 }
 462
 463 /* This is the implementation of linux_target_ops method
 464    remove_point.  */
 465
 466 static int
 467 mips_remove_point (char type, CORE_ADDR addr, int len)
 468 {
 469   struct process_info *proc = current_process ();
 470   struct arch_process_info *private = proc->private->arch_private;
 471
 472   int deleted_one;
 473   int pid;
 474   enum target_hw_bp_type watch_type;
 475
 476   struct mips_watchpoint **pw;
 477   struct mips_watchpoint *w;
 478
 479   /* Breakpoint/watchpoint types:
 480        '0' - software-breakpoint (not supported)
 481        '1' - hardware-breakpoint (not supported)
 482        '2' - write watchpoint (supported)
 483        '3' - read watchpoint (supported)
 484        '4' - access watchpoint (supported).  */
 485
 486   if (type < '2' || type > '4')
 487     {
 488       /* Unsupported.  */
 489       return 1;
 490     }
 491
 492   /* Search for a known watch that matches.  Then unlink and free it.  */
 493   watch_type = rsp_bp_type_to_target_hw_bp_type (type);
 494   deleted_one = 0;
 495   pw = &private->current_watches;
 496   while ((w = *pw))
 497     {
 498       if (w->addr == addr && w->len == len && w->type == watch_type)
 499         {
 500           *pw = w->next;
 501           free (w);
 502           deleted_one = 1;
 503           break;
 504         }
 505       pw = &(w->next);
 506     }
 507
 508   if (!deleted_one)
 509     return -1;  /* We don't know about it, fail doing nothing.  */
 510
 511   /* At this point watch_readback is known to be valid because we
 512      could not have added the watch without reading it.  */
 513   gdb_assert (private->watch_readback_valid == 1);
 514
 515   private->watch_mirror = private->watch_readback;
 516   mips_linux_watch_populate_regs (private->current_watches,
 517                                   &private->watch_mirror);
 518
 519   /* Only update the threads of this process.  */
 520   pid = pid_of (proc);
 521   find_inferior (&all_threads, update_watch_registers_callback, &pid);
 522   return 0;
 523 }
 524
 525 /* This is the implementation of linux_target_ops method
 526    stopped_by_watchpoint.  The watchhi R and W bits indicate
 527    the watch register triggered. */
 528
 529 static int
 530 mips_stopped_by_watchpoint (void)
 531 {
 532   struct process_info *proc = current_process ();
 533   struct arch_process_info *private = proc->private->arch_private;
 534   int n;
 535   int num_valid;
 536   long lwpid = lwpid_of (current_inferior);
 537
 538   if (!mips_linux_read_watch_registers (lwpid,
 539                                         &private->watch_readback,
 540                                         &private->watch_readback_valid,
 541                                         1))
 542     return 0;
 543
 544   num_valid = mips_linux_watch_get_num_valid (&private->watch_readback);
 545
 546   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 547     if (mips_linux_watch_get_watchhi (&private->watch_readback, n)
 548         & (R_MASK | W_MASK))
 549       return 1;
 550
 551   return 0;
 552 }
 553
 554 /* This is the implementation of linux_target_ops method
 555    stopped_data_address.  */
 556
 557 static CORE_ADDR
 558 mips_stopped_data_address (void)
 559 {
 560   struct process_info *proc = current_process ();
 561   struct arch_process_info *private = proc->private->arch_private;
 562   int n;
 563   int num_valid;
 564   long lwpid = lwpid_of (current_inferior);
 565
 566   /* On MIPS we don't know the low order 3 bits of the data address.
 567      GDB does not support remote targets that can't report the
 568      watchpoint address.  So, make our best guess; return the starting
 569      address of a watchpoint request which overlaps the one that
 570      triggered.  */
 571
 572   if (!mips_linux_read_watch_registers (lwpid,
 573                                         &private->watch_readback,
 574                                         &private->watch_readback_valid,
 575                                         0))
 576     return 0;
 577
 578   num_valid = mips_linux_watch_get_num_valid (&private->watch_readback);
 579
 580   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 581     if (mips_linux_watch_get_watchhi (&private->watch_readback, n)
 582         & (R_MASK | W_MASK))
 583       {
 584         CORE_ADDR t_low, t_hi;
 585         int t_irw;
 586         struct mips_watchpoint *watch;
 587
 588         t_low = mips_linux_watch_get_watchlo (&private->watch_readback, n);
 589         t_irw = t_low & IRW_MASK;
 590         t_hi = (mips_linux_watch_get_watchhi (&private->watch_readback, n)
 591                 | IRW_MASK);
 592         t_low &= ~(CORE_ADDR)t_hi;
 593
 594         for (watch = private->current_watches;
 595              watch != NULL;
 596              watch = watch->next)
 597           {
 598             CORE_ADDR addr = watch->addr;
 599             CORE_ADDR last_byte = addr + watch->len - 1;
 600
 601             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 602               {
 603                 /* Different type.  */
 604                 continue;
 605               }
 606             /* Check for overlap of even a single byte.  */
 607             if (last_byte >= t_low && addr <= t_low + t_hi)
 608               return addr;
 609           }
 610       }
 611
 612   /* Shouldn't happen.  */
 613   return 0;
 614 }
 615
 616 /* Fetch the thread-local storage pointer for libthread_db.  */
 617
 618 ps_err_e
 619 ps_get_thread_area (const struct ps_prochandle *ph,
 620                     lwpid_t lwpid, int idx, void **base)
 621 {
 622   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 623     return PS_ERR;
 624
 625   /* IDX is the bias from the thread pointer to the beginning of the
 626      thread descriptor.  It has to be subtracted due to implementation
 627      quirks in libthread_db.  */
 628   *base = (void *) ((char *)*base - idx);
 629
 630   return PS_OK;
 631 }
 632
 633 #ifdef HAVE_PTRACE_GETREGS
 634
 635 static void
 636 mips_collect_register (struct regcache *regcache,
 637                        int use_64bit, int regno, union mips_register *reg)
 638 {
 639   union mips_register tmp_reg;
 640
 641   if (use_64bit)
 642     {
 643       collect_register (regcache, regno, &tmp_reg.reg64);
 644       *reg = tmp_reg;
 645     }
 646   else
 647     {
 648       collect_register (regcache, regno, &tmp_reg.reg32);
 649       reg->reg64 = tmp_reg.reg32;
 650     }
 651 }
 652
 653 static void
 654 mips_supply_register (struct regcache *regcache,
 655                       int use_64bit, int regno, const union mips_register *reg)
 656 {
 657   int offset = 0;
 658
 659   /* For big-endian 32-bit targets, ignore the high four bytes of each
 660      eight-byte slot.  */
 661   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 662     offset = 4;
 663
 664   supply_register (regcache, regno, reg->buf + offset);
 665 }
 666
 667 static void
 668 mips_collect_register_32bit (struct regcache *regcache,
 669                              int use_64bit, int regno, unsigned char *buf)
 670 {
 671   union mips_register tmp_reg;
 672   int reg32;
 673
 674   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 675   reg32 = tmp_reg.reg64;
 676   memcpy (buf, &reg32, 4);
 677 }
 678
 679 static void
 680 mips_supply_register_32bit (struct regcache *regcache,
 681                             int use_64bit, int regno, const unsigned char *buf)
 682 {
 683   union mips_register tmp_reg;
 684   int reg32;
 685
 686   memcpy (&reg32, buf, 4);
 687   tmp_reg.reg64 = reg32;
 688   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 689 }
 690
 691 static void
 692 mips_fill_gregset (struct regcache *regcache, void *buf)
 693 {
 694   union mips_register *regset = buf;
 695   int i, use_64bit;
 696   const struct target_desc *tdesc = regcache->tdesc;
 697
 698   use_64bit = (register_size (tdesc, 0) == 8);
 699
 700   for (i = 1; i < 32; i++)
 701     mips_collect_register (regcache, use_64bit, i, regset + i);
 702
 703   mips_collect_register (regcache, use_64bit,
 704                          find_regno (tdesc, "lo"), regset + 32);
 705   mips_collect_register (regcache, use_64bit,
 706                          find_regno (tdesc, "hi"), regset + 33);
 707   mips_collect_register (regcache, use_64bit,
 708                          find_regno (tdesc, "pc"), regset + 34);
 709   mips_collect_register (regcache, use_64bit,
 710                          find_regno (tdesc, "badvaddr"), regset + 35);
 711   mips_collect_register (regcache, use_64bit,
 712                          find_regno (tdesc, "status"), regset + 36);
 713   mips_collect_register (regcache, use_64bit,
 714                          find_regno (tdesc, "cause"), regset + 37);
 715
 716   mips_collect_register (regcache, use_64bit,
 717                          find_regno (tdesc, "restart"), regset + 0);
 718 }
 719
 720 static void
 721 mips_store_gregset (struct regcache *regcache, const void *buf)
 722 {
 723   const union mips_register *regset = buf;
 724   int i, use_64bit;
 725
 726   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 727
 728   for (i = 0; i < 32; i++)
 729     mips_supply_register (regcache, use_64bit, i, regset + i);
 730
 731   mips_supply_register (regcache, use_64bit,
 732                         find_regno (regcache->tdesc, "lo"), regset + 32);
 733   mips_supply_register (regcache, use_64bit,
 734                         find_regno (regcache->tdesc, "hi"), regset + 33);
 735   mips_supply_register (regcache, use_64bit,
 736                         find_regno (regcache->tdesc, "pc"), regset + 34);
 737   mips_supply_register (regcache, use_64bit,
 738                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 739   mips_supply_register (regcache, use_64bit,
 740                         find_regno (regcache->tdesc, "status"), regset + 36);
 741   mips_supply_register (regcache, use_64bit,
 742                         find_regno (regcache->tdesc, "cause"), regset + 37);
 743
 744   mips_supply_register (regcache, use_64bit,
 745                         find_regno (regcache->tdesc, "restart"), regset + 0);
 746 }
 747
 748 static void
 749 mips_fill_fpregset (struct regcache *regcache, void *buf)
 750 {
 751   union mips_register *regset = buf;
 752   int i, use_64bit, first_fp, big_endian;
 753
 754   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 755   first_fp = find_regno (regcache->tdesc, "f0");
 756   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 757
 758   /* See GDB for a discussion of this peculiar layout.  */
 759   for (i = 0; i < 32; i++)
 760     if (use_64bit)
 761       collect_register (regcache, first_fp + i, regset[i].buf);
 762     else
 763       collect_register (regcache, first_fp + i,
 764                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 765
 766   mips_collect_register_32bit (regcache, use_64bit,
 767                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 768   mips_collect_register_32bit (regcache, use_64bit,
 769                                find_regno (regcache->tdesc, "fir"),
 770                                regset[32].buf + 4);
 771 }
 772
 773 static void
 774 mips_store_fpregset (struct regcache *regcache, const void *buf)
 775 {
 776   const union mips_register *regset = buf;
 777   int i, use_64bit, first_fp, big_endian;
 778
 779   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 780   first_fp = find_regno (regcache->tdesc, "f0");
 781   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 782
 783   /* See GDB for a discussion of this peculiar layout.  */
 784   for (i = 0; i < 32; i++)
 785     if (use_64bit)
 786       supply_register (regcache, first_fp + i, regset[i].buf);
 787     else
 788       supply_register (regcache, first_fp + i,
 789                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 790
 791   mips_supply_register_32bit (regcache, use_64bit,
 792                               find_regno (regcache->tdesc, "fcsr"),
 793                               regset[32].buf);
 794   mips_supply_register_32bit (regcache, use_64bit,
 795                               find_regno (regcache->tdesc, "fir"),
 796                               regset[32].buf + 4);
 797 }
 798 #endif /* HAVE_PTRACE_GETREGS */
 799
 800 static struct regset_info mips_regsets[] = {
 801 #ifdef HAVE_PTRACE_GETREGS
 802   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 803     mips_fill_gregset, mips_store_gregset },
 804   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 805     mips_fill_fpregset, mips_store_fpregset },
 806 #endif /* HAVE_PTRACE_GETREGS */
 807   { 0, 0, 0, -1, -1, NULL, NULL }
 808 };
 809
 810 static struct regsets_info mips_regsets_info =
 811   {
 812     mips_regsets, /* regsets */
 813     0, /* num_regsets */
 814     NULL, /* disabled_regsets */
 815   };
 816
 817 static struct usrregs_info mips_dsp_usrregs_info =
 818   {
 819     mips_dsp_num_regs,
 820     mips_dsp_regmap,
 821   };
 822
 823 static struct usrregs_info mips_usrregs_info =
 824   {
 825     mips_num_regs,
 826     mips_regmap,
 827   };
 828
 829 static struct regs_info dsp_regs_info =
 830   {
 831     mips_dsp_regset_bitmap,
 832     &mips_dsp_usrregs_info,
 833     &mips_regsets_info
 834   };
 835
 836 static struct regs_info regs_info =
 837   {
 838     NULL, /* regset_bitmap */
 839     &mips_usrregs_info,
 840     &mips_regsets_info
 841   };
 842
 843 static const struct regs_info *
 844 mips_regs_info (void)
 845 {
 846   if (have_dsp)
 847     return &dsp_regs_info;
 848   else
 849     return &regs_info;
 850 }
 851
 852 struct linux_target_ops the_low_target = {
 853   mips_arch_setup,
 854   mips_regs_info,
 855   mips_cannot_fetch_register,
 856   mips_cannot_store_register,
 857   NULL, /* fetch_register */
 858   mips_get_pc,
 859   mips_set_pc,
 860   (const unsigned char *) &mips_breakpoint,
 861   mips_breakpoint_len,
 862   mips_reinsert_addr,
 863   0,
 864   mips_breakpoint_at,
 865   mips_insert_point,
 866   mips_remove_point,
 867   mips_stopped_by_watchpoint,
 868   mips_stopped_data_address,
 869   NULL,
 870   NULL,
 871   NULL, /* siginfo_fixup */
 872   mips_linux_new_process,
 873   mips_linux_new_thread,
 874   mips_linux_prepare_to_resume
 875 };
 876
 877 void
 878 initialize_low_arch (void)
 879 {
 880   /* Initialize the Linux target descriptions.  */
 881   init_registers_mips_linux ();
 882   init_registers_mips_dsp_linux ();
 883   init_registers_mips64_linux ();
 884   init_registers_mips64_dsp_linux ();
 885
 886   initialize_regsets_info (&mips_regsets_info);
 887 }