1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
24 #include <asm/ptrace.h>
26 #include "arch/ppc-linux-common.h"
27 #include "arch/ppc-linux-tdesc.h"
28 #include "nat/ppc-linux.h"
29 #include "linux-ppc-tdesc-init.h"
31 #include "tracepoint.h"
33 #define PPC_FIELD(value, from, len) \
34 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
35 #define PPC_SEXT(v, bs) \
36 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
37 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
38 - ((CORE_ADDR) 1 << ((bs) - 1)))
39 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
40 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
41 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
42 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
44 static unsigned long ppc_hwcap
;
47 #define ppc_num_regs 73
50 /* We use a constant for FPSCR instead of PT_FPSCR, because
51 many shipped PPC64 kernels had the wrong value in ptrace.h. */
52 static int ppc_regmap
[] =
53 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
54 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
55 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
56 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
57 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
58 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
59 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
60 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
61 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
62 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
63 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
64 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
65 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
66 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
67 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
68 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
69 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
70 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
71 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
73 /* Currently, don't check/send MQ. */
74 static int ppc_regmap
[] =
75 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
76 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
77 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
78 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
79 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
80 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
81 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
82 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
83 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
84 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
85 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
86 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
87 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
88 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
89 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
90 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
91 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
92 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
93 PT_ORIG_R3
* 4, PT_TRAP
* 4
96 static int ppc_regmap_e500
[] =
97 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
98 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
99 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
100 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
101 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
102 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
103 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
104 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
113 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
114 PT_CTR
* 4, PT_XER
* 4, -1,
115 PT_ORIG_R3
* 4, PT_TRAP
* 4
120 ppc_cannot_store_register (int regno
)
122 const struct target_desc
*tdesc
= current_process ()->tdesc
;
124 #ifndef __powerpc64__
125 /* Some kernels do not allow us to store fpscr. */
126 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
127 && regno
== find_regno (tdesc
, "fpscr"))
131 /* Some kernels do not allow us to store orig_r3 or trap. */
132 if (regno
== find_regno (tdesc
, "orig_r3")
133 || regno
== find_regno (tdesc
, "trap"))
140 ppc_cannot_fetch_register (int regno
)
146 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
148 memset (buf
, 0, sizeof (long));
150 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
152 /* Little-endian values always sit at the left end of the buffer. */
153 collect_register (regcache
, regno
, buf
);
155 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
157 /* Big-endian values sit at the right end of the buffer. In case of
158 registers whose sizes are smaller than sizeof (long), we must use a
159 padding to access them correctly. */
160 int size
= register_size (regcache
->tdesc
, regno
);
162 if (size
< sizeof (long))
163 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
165 collect_register (regcache
, regno
, buf
);
168 perror_with_name ("Unexpected byte order");
172 ppc_supply_ptrace_register (struct regcache
*regcache
,
173 int regno
, const char *buf
)
175 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
177 /* Little-endian values always sit at the left end of the buffer. */
178 supply_register (regcache
, regno
, buf
);
180 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
182 /* Big-endian values sit at the right end of the buffer. In case of
183 registers whose sizes are smaller than sizeof (long), we must use a
184 padding to access them correctly. */
185 int size
= register_size (regcache
->tdesc
, regno
);
187 if (size
< sizeof (long))
188 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
190 supply_register (regcache
, regno
, buf
);
193 perror_with_name ("Unexpected byte order");
197 #define INSTR_SC 0x44000002
198 #define NR_spu_run 0x0116
200 /* If the PPU thread is currently stopped on a spu_run system call,
201 return to FD and ADDR the file handle and NPC parameter address
202 used with the system call. Return non-zero if successful. */
204 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
210 if (register_size (regcache
->tdesc
, 0) == 4)
212 unsigned int pc
, r0
, r3
, r4
;
213 collect_register_by_name (regcache
, "pc", &pc
);
214 collect_register_by_name (regcache
, "r0", &r0
);
215 collect_register_by_name (regcache
, "orig_r3", &r3
);
216 collect_register_by_name (regcache
, "r4", &r4
);
217 curr_pc
= (CORE_ADDR
) pc
;
220 *addr
= (CORE_ADDR
) r4
;
224 unsigned long pc
, r0
, r3
, r4
;
225 collect_register_by_name (regcache
, "pc", &pc
);
226 collect_register_by_name (regcache
, "r0", &r0
);
227 collect_register_by_name (regcache
, "orig_r3", &r3
);
228 collect_register_by_name (regcache
, "r4", &r4
);
229 curr_pc
= (CORE_ADDR
) pc
;
232 *addr
= (CORE_ADDR
) r4
;
235 /* Fetch instruction preceding current NIP. */
236 if ((*the_target
->read_memory
) (curr_pc
- 4,
237 (unsigned char *) &curr_insn
, 4) != 0)
239 /* It should be a "sc" instruction. */
240 if (curr_insn
!= INSTR_SC
)
242 /* System call number should be NR_spu_run. */
243 if (curr_r0
!= NR_spu_run
)
250 ppc_get_pc (struct regcache
*regcache
)
255 if (parse_spufs_run (regcache
, &fd
, &addr
))
258 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
259 return ((CORE_ADDR
)1 << 63)
260 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
262 else if (register_size (regcache
->tdesc
, 0) == 4)
265 collect_register_by_name (regcache
, "pc", &pc
);
266 return (CORE_ADDR
) pc
;
271 collect_register_by_name (regcache
, "pc", &pc
);
272 return (CORE_ADDR
) pc
;
277 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
282 if (parse_spufs_run (regcache
, &fd
, &addr
))
284 unsigned int newpc
= pc
;
285 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
287 else if (register_size (regcache
->tdesc
, 0) == 4)
289 unsigned int newpc
= pc
;
290 supply_register_by_name (regcache
, "pc", &newpc
);
294 unsigned long newpc
= pc
;
295 supply_register_by_name (regcache
, "pc", &newpc
);
301 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
303 const struct target_desc
*tdesc
= current_process ()->tdesc
;
304 int wordsize
= register_size (tdesc
, 0);
305 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
308 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
312 unsigned int *data_p
= (unsigned int *)data
;
313 if (data_p
[0] == type
)
321 unsigned long *data_p
= (unsigned long *)data
;
322 if (data_p
[0] == type
)
329 offset
+= 2 * wordsize
;
336 #ifndef __powerpc64__
337 static int ppc_regmap_adjusted
;
341 /* Correct in either endianness.
342 This instruction is "twge r2, r2", which GDB uses as a software
344 static const unsigned int ppc_breakpoint
= 0x7d821008;
345 #define ppc_breakpoint_len 4
347 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
349 static const gdb_byte
*
350 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
352 *size
= ppc_breakpoint_len
;
353 return (const gdb_byte
*) &ppc_breakpoint
;
357 ppc_breakpoint_at (CORE_ADDR where
)
361 if (where
& ((CORE_ADDR
)1 << 63))
364 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
365 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
366 NULL
, where
& 0xffffffff, 4);
372 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
373 if (insn
== ppc_breakpoint
)
375 /* If necessary, recognize more trap instructions here. GDB only uses
382 /* Implement supports_z_point_type target-ops.
383 Returns true if type Z_TYPE breakpoint is supported.
385 Handling software breakpoint at server side, so tracepoints
386 and breakpoints can be inserted at the same location. */
389 ppc_supports_z_point_type (char z_type
)
396 case Z_PACKET_WRITE_WP
:
397 case Z_PACKET_ACCESS_WP
:
403 /* Implement insert_point target-ops.
404 Returns 0 on success, -1 on failure and 1 on unsupported. */
407 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
408 int size
, struct raw_breakpoint
*bp
)
412 case raw_bkpt_type_sw
:
413 return insert_memory_breakpoint (bp
);
415 case raw_bkpt_type_hw
:
416 case raw_bkpt_type_write_wp
:
417 case raw_bkpt_type_access_wp
:
424 /* Implement remove_point target-ops.
425 Returns 0 on success, -1 on failure and 1 on unsupported. */
428 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
429 int size
, struct raw_breakpoint
*bp
)
433 case raw_bkpt_type_sw
:
434 return remove_memory_breakpoint (bp
);
436 case raw_bkpt_type_hw
:
437 case raw_bkpt_type_write_wp
:
438 case raw_bkpt_type_access_wp
:
445 /* Provide only a fill function for the general register set. ps_lgetregs
446 will use this for NPTL support. */
448 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
452 for (i
= 0; i
< 32; i
++)
453 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
455 for (i
= 64; i
< 70; i
++)
456 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
458 for (i
= 71; i
< 73; i
++)
459 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
462 #define SIZEOF_VSXREGS 32*8
465 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
468 char *regset
= (char *) buf
;
470 if (!(ppc_hwcap
& PPC_FEATURE_HAS_VSX
))
473 base
= find_regno (regcache
->tdesc
, "vs0h");
474 for (i
= 0; i
< 32; i
++)
475 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
479 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
482 const char *regset
= (const char *) buf
;
484 if (!(ppc_hwcap
& PPC_FEATURE_HAS_VSX
))
487 base
= find_regno (regcache
->tdesc
, "vs0h");
488 for (i
= 0; i
< 32; i
++)
489 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
492 #define SIZEOF_VRREGS 33*16+4
495 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
498 char *regset
= (char *) buf
;
500 if (!(ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
))
503 base
= find_regno (regcache
->tdesc
, "vr0");
504 for (i
= 0; i
< 32; i
++)
505 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
507 collect_register_by_name (regcache
, "vscr", ®set
[32 * 16 + 12]);
508 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
512 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
515 const char *regset
= (const char *) buf
;
517 if (!(ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
))
520 base
= find_regno (regcache
->tdesc
, "vr0");
521 for (i
= 0; i
< 32; i
++)
522 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
524 supply_register_by_name (regcache
, "vscr", ®set
[32 * 16 + 12]);
525 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
528 struct gdb_evrregset_t
530 unsigned long evr
[32];
531 unsigned long long acc
;
532 unsigned long spefscr
;
536 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
539 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
541 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
))
544 ev0
= find_regno (regcache
->tdesc
, "ev0h");
545 for (i
= 0; i
< 32; i
++)
546 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
548 collect_register_by_name (regcache
, "acc", ®set
->acc
);
549 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
553 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
556 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
558 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
))
561 ev0
= find_regno (regcache
->tdesc
, "ev0h");
562 for (i
= 0; i
< 32; i
++)
563 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
565 supply_register_by_name (regcache
, "acc", ®set
->acc
);
566 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
569 /* Support for hardware single step. */
572 ppc_supports_hardware_single_step (void)
577 static struct regset_info ppc_regsets
[] = {
578 /* List the extra register sets before GENERAL_REGS. That way we will
579 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
580 general registers. Some kernels support these, but not the newer
581 PPC_PTRACE_GETREGS. */
582 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, SIZEOF_VSXREGS
, EXTENDED_REGS
,
583 ppc_fill_vsxregset
, ppc_store_vsxregset
},
584 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, SIZEOF_VRREGS
, EXTENDED_REGS
,
585 ppc_fill_vrregset
, ppc_store_vrregset
},
586 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 32 * 4 + 8 + 4, EXTENDED_REGS
,
587 ppc_fill_evrregset
, ppc_store_evrregset
},
588 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
592 static struct usrregs_info ppc_usrregs_info
=
598 static struct regsets_info ppc_regsets_info
=
600 ppc_regsets
, /* regsets */
602 NULL
, /* disabled_regsets */
605 static struct regs_info regs_info
=
607 NULL
, /* regset_bitmap */
612 static const struct regs_info
*
619 ppc_arch_setup (void)
621 const struct target_desc
*tdesc
;
622 struct ppc_linux_features features
= ppc_linux_no_features
;
623 int tid
= lwpid_of (current_thread
);
625 features
.wordsize
= ppc_linux_target_wordsize (tid
);
627 if (features
.wordsize
== 4)
628 tdesc
= tdesc_powerpc_32l
;
630 tdesc
= tdesc_powerpc_64l
;
632 current_process ()->tdesc
= tdesc
;
634 /* The value of current_process ()->tdesc needs to be set for this
636 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
638 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
640 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
643 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
644 features
.altivec
= true;
646 if (ppc_hwcap
& PPC_FEATURE_CELL
)
647 features
.cell
= true;
649 tdesc
= ppc_linux_match_description (features
);
651 /* On 32-bit machines, check for SPE registers.
652 Set the low target's regmap field as appropriately. */
653 #ifndef __powerpc64__
654 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
655 tdesc
= tdesc_powerpc_e500l
;
657 if (!ppc_regmap_adjusted
)
659 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
660 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
662 /* If the FPSCR is 64-bit wide, we need to fetch the whole
663 64-bit slot and not just its second word. The PT_FPSCR
664 supplied in a 32-bit GDB compilation doesn't reflect
666 if (register_size (tdesc
, 70) == 8)
667 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
669 ppc_regmap_adjusted
= 1;
673 current_process ()->tdesc
= tdesc
;
676 /* Implementation of linux_target_ops method "supports_tracepoints". */
679 ppc_supports_tracepoints (void)
684 /* Get the thread area address. This is used to recognize which
685 thread is which when tracing with the in-process agent library. We
686 don't read anything from the address, and treat it as opaque; it's
687 the address itself that we assume is unique per-thread. */
690 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
692 struct lwp_info
*lwp
= find_lwp_pid (pid_to_ptid (lwpid
));
693 struct thread_info
*thr
= get_lwp_thread (lwp
);
694 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
698 if (register_size (regcache
->tdesc
, 0) == 8)
699 collect_register_by_name (regcache
, "r13", &tp
);
702 collect_register_by_name (regcache
, "r2", &tp
);
711 /* Older glibc doesn't provide this. */
714 #define EF_PPC64_ABI 3
717 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
721 is_elfv2_inferior (void)
723 /* To be used as fallback if we're unable to determine the right result -
724 assume inferior uses the same ABI as gdbserver. */
726 const int def_res
= 1;
728 const int def_res
= 0;
733 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
736 /* Assume ELF header is at the beginning of the page where program headers
737 are located. If it doesn't look like one, bail. */
739 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
740 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
743 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
748 /* Generate a ds-form instruction in BUF and return the number of bytes written
751 | OPCD | RST | RA | DS |XO| */
753 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
755 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
759 gdb_assert ((opcd
& ~0x3f) == 0);
760 gdb_assert ((rst
& ~0x1f) == 0);
761 gdb_assert ((ra
& ~0x1f) == 0);
762 gdb_assert ((xo
& ~0x3) == 0);
764 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
765 *buf
= (opcd
<< 26) | insn
;
769 /* Followings are frequently used ds-form instructions. */
771 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
772 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
773 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
774 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
776 /* Generate a d-form instruction in BUF.
779 | OPCD | RST | RA | D | */
782 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
786 gdb_assert ((opcd
& ~0x3f) == 0);
787 gdb_assert ((rst
& ~0x1f) == 0);
788 gdb_assert ((ra
& ~0x1f) == 0);
790 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
791 *buf
= (opcd
<< 26) | insn
;
795 /* Followings are frequently used d-form instructions. */
797 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
798 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
799 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
800 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
801 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
802 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
803 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
804 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
805 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
807 /* Generate a xfx-form instruction in BUF and return the number of bytes
811 | OPCD | RST | RI | XO |/| */
814 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
817 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
819 gdb_assert ((opcd
& ~0x3f) == 0);
820 gdb_assert ((rst
& ~0x1f) == 0);
821 gdb_assert ((xo
& ~0x3ff) == 0);
823 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
824 *buf
= (opcd
<< 26) | insn
;
828 /* Followings are frequently used xfx-form instructions. */
830 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
831 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
832 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
833 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
834 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
836 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
839 /* Generate a x-form instruction in BUF and return the number of bytes written.
842 | OPCD | RST | RA | RB | XO |RC| */
845 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
849 gdb_assert ((opcd
& ~0x3f) == 0);
850 gdb_assert ((rst
& ~0x1f) == 0);
851 gdb_assert ((ra
& ~0x1f) == 0);
852 gdb_assert ((rb
& ~0x1f) == 0);
853 gdb_assert ((xo
& ~0x3ff) == 0);
854 gdb_assert ((rc
& ~1) == 0);
856 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
857 *buf
= (opcd
<< 26) | insn
;
861 /* Followings are frequently used x-form instructions. */
863 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
864 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
865 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
866 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
867 /* Assume bf = cr7. */
868 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
871 /* Generate a md-form instruction in BUF and return the number of bytes written.
873 0 6 11 16 21 27 30 31 32
874 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
877 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
881 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
882 unsigned int sh0_4
= sh
& 0x1f;
883 unsigned int sh5
= (sh
>> 5) & 1;
885 gdb_assert ((opcd
& ~0x3f) == 0);
886 gdb_assert ((rs
& ~0x1f) == 0);
887 gdb_assert ((ra
& ~0x1f) == 0);
888 gdb_assert ((sh
& ~0x3f) == 0);
889 gdb_assert ((mb
& ~0x3f) == 0);
890 gdb_assert ((xo
& ~0x7) == 0);
891 gdb_assert ((rc
& ~0x1) == 0);
893 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
894 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
895 *buf
= (opcd
<< 26) | insn
;
899 /* The following are frequently used md-form instructions. */
901 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
902 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
903 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
904 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
906 /* Generate a i-form instruction in BUF and return the number of bytes written.
909 | OPCD | LI |AA|LK| */
912 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
916 gdb_assert ((opcd
& ~0x3f) == 0);
918 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
919 *buf
= (opcd
<< 26) | insn
;
923 /* The following are frequently used i-form instructions. */
925 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
926 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
928 /* Generate a b-form instruction in BUF and return the number of bytes written.
931 | OPCD | BO | BI | BD |AA|LK| */
934 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
939 gdb_assert ((opcd
& ~0x3f) == 0);
940 gdb_assert ((bo
& ~0x1f) == 0);
941 gdb_assert ((bi
& ~0x1f) == 0);
943 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
944 *buf
= (opcd
<< 26) | insn
;
948 /* The following are frequently used b-form instructions. */
949 /* Assume bi = cr7. */
950 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
952 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
953 respectively. They are primary used for save/restore GPRs in jump-pad,
954 not used for bytecode compiling. */
957 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
958 GEN_LD (buf, rt, ra, si) : \
959 GEN_LWZ (buf, rt, ra, si))
960 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
961 GEN_STD (buf, rt, ra, si) : \
962 GEN_STW (buf, rt, ra, si))
964 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
965 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
968 /* Generate a sequence of instructions to load IMM in the register REG.
969 Write the instructions in BUF and return the number of bytes written. */
972 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
976 if ((imm
+ 32768) < 65536)
978 /* li reg, imm[15:0] */
979 p
+= GEN_LI (p
, reg
, imm
);
981 else if ((imm
>> 32) == 0)
983 /* lis reg, imm[31:16]
984 ori reg, reg, imm[15:0]
985 rldicl reg, reg, 0, 32 */
986 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
987 if ((imm
& 0xffff) != 0)
988 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
989 /* Clear upper 32-bit if sign-bit is set. */
990 if (imm
& (1u << 31) && is_64
)
991 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
996 /* lis reg, <imm[63:48]>
997 ori reg, reg, <imm[48:32]>
998 rldicr reg, reg, 32, 31
999 oris reg, reg, <imm[31:16]>
1000 ori reg, reg, <imm[15:0]> */
1001 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1002 if (((imm
>> 32) & 0xffff) != 0)
1003 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1004 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1005 if (((imm
>> 16) & 0xffff) != 0)
1006 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1007 if ((imm
& 0xffff) != 0)
1008 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1014 /* Generate a sequence for atomically exchange at location LOCK.
1015 This code sequence clobbers r6, r7, r8. LOCK is the location for
1016 the atomic-xchg, OLD_VALUE is expected old value stored in the
1017 location, and R_NEW is a register for the new value. */
1020 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1023 const int r_lock
= 6;
1024 const int r_old
= 7;
1025 const int r_tmp
= 8;
1029 1: lwarx TMP, 0, LOCK
1035 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1036 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1038 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1039 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1040 p
+= GEN_BNE (p
, -8);
1041 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1042 p
+= GEN_BNE (p
, -16);
1047 /* Generate a sequence of instructions for calling a function
1048 at address of FN. Return the number of bytes are written in BUF. */
1051 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1055 /* Must be called by r12 for caller to calculate TOC address. */
1056 p
+= gen_limm (p
, 12, fn
, is_64
);
1059 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1060 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1061 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1063 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1064 *p
++ = 0x4e800421; /* bctrl */
1069 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1070 of instruction. This function is used to adjust pc-relative instructions
1074 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1079 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1080 op6
= PPC_OP6 (insn
);
1082 if (op6
== 18 && (insn
& 2) == 0)
1084 /* branch && AA = 0 */
1085 rel
= PPC_LI (insn
);
1086 newrel
= (oldloc
- *to
) + rel
;
1088 /* Out of range. Cannot relocate instruction. */
1089 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1092 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1094 else if (op6
== 16 && (insn
& 2) == 0)
1096 /* conditional branch && AA = 0 */
1098 /* If the new relocation is too big for even a 26-bit unconditional
1099 branch, there is nothing we can do. Just abort.
1101 Otherwise, if it can be fit in 16-bit conditional branch, just
1102 copy the instruction and relocate the address.
1104 If the it's big for conditional-branch (16-bit), try to invert the
1105 condition and jump with 26-bit branch. For example,
1116 After this transform, we are actually jump from *TO+4 instead of *TO,
1117 so check the relocation again because it will be 1-insn farther then
1118 before if *TO is after OLDLOC.
1121 For BDNZT (or so) is transformed from
1133 See also "BO field encodings". */
1135 rel
= PPC_BD (insn
);
1136 newrel
= (oldloc
- *to
) + rel
;
1138 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1139 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1140 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1144 /* Out of range. Cannot relocate instruction. */
1145 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1148 if ((PPC_BO (insn
) & 0x14) == 0x4)
1150 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1153 /* Jump over the unconditional branch. */
1154 insn
= (insn
& ~0xfffc) | 0x8;
1155 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1158 /* Build a unconditional branch and copy LK bit. */
1159 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1160 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1165 else if ((PPC_BO (insn
) & 0x14) == 0)
1167 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1168 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1172 /* Out of range. Cannot relocate instruction. */
1173 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1176 /* Copy BI field. */
1177 bf_insn
|= (insn
& 0x1f0000);
1179 /* Invert condition. */
1180 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1181 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1183 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1185 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1188 /* Build a unconditional branch and copy LK bit. */
1189 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1190 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1195 else /* (BO & 0x14) == 0x14, branch always. */
1197 /* Out of range. Cannot relocate instruction. */
1198 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1201 /* Build a unconditional branch and copy LK bit. */
1202 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1203 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1210 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1214 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1215 See target.h for details. */
1218 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1219 CORE_ADDR collector
,
1222 CORE_ADDR
*jump_entry
,
1223 CORE_ADDR
*trampoline
,
1224 ULONGEST
*trampoline_size
,
1225 unsigned char *jjump_pad_insn
,
1226 ULONGEST
*jjump_pad_insn_size
,
1227 CORE_ADDR
*adjusted_insn_addr
,
1228 CORE_ADDR
*adjusted_insn_addr_end
,
1234 CORE_ADDR buildaddr
= *jump_entry
;
1235 const CORE_ADDR entryaddr
= *jump_entry
;
1236 int rsz
, min_frame
, frame_size
, tp_reg
;
1237 #ifdef __powerpc64__
1238 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1239 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1240 int is_opd
= is_64
&& !is_elfv2_inferior ();
1242 int is_64
= 0, is_opd
= 0;
1245 #ifdef __powerpc64__
1248 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1251 frame_size
= (40 * rsz
) + min_frame
;
1259 frame_size
= (40 * rsz
) + min_frame
;
1261 #ifdef __powerpc64__
1265 /* Stack frame layout for this jump pad,
1267 High thread_area (r13/r2) |
1268 tpoint - collecting_t obj
1278 R0 - collected registers
1284 The code flow of this jump pad,
1289 4. Call gdb_collector
1290 5. Restore GPR and SPR
1292 7. Build a jump for back to the program
1293 8. Copy/relocate original instruction
1294 9. Build a jump for replacing orignal instruction. */
1296 /* Adjust stack pointer. */
1298 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1300 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1302 /* Store GPRs. Save R1 later, because it had just been modified, but
1303 we want the original value. */
1304 for (j
= 2; j
< 32; j
++)
1305 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1306 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1307 /* Set r0 to the original value of r1 before adjusting stack frame,
1308 and then save it. */
1309 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1310 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1312 /* Save CR, XER, LR, and CTR. */
1313 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1314 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1315 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1316 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1317 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1318 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1319 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1320 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1322 /* Save PC<tpaddr> */
1323 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1324 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1327 /* Setup arguments to collector. */
1328 /* Set r4 to collected registers. */
1329 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1330 /* Set r3 to TPOINT. */
1331 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1333 /* Prepare collecting_t object for lock. */
1334 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1335 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1336 /* Set R5 to collecting object. */
1337 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1339 p
+= GEN_LWSYNC (p
);
1340 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1341 p
+= GEN_LWSYNC (p
);
1343 /* Call to collector. */
1344 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1346 /* Simply write 0 to release the lock. */
1347 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1348 p
+= gen_limm (p
, 4, 0, is_64
);
1349 p
+= GEN_LWSYNC (p
);
1350 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1352 /* Restore stack and registers. */
1353 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1354 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1355 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1356 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1357 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1358 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1359 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1360 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1363 for (j
= 2; j
< 32; j
++)
1364 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1365 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1367 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1369 /* Flush instructions to inferior memory. */
1370 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1372 /* Now, insert the original instruction to execute in the jump pad. */
1373 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1374 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1375 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1377 /* Verify the relocation size. If should be 4 for normal copy,
1378 8 or 12 for some conditional branch. */
1379 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1380 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1382 sprintf (err
, "E.Unexpected instruction length = %d"
1383 "when relocate instruction.",
1384 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1388 buildaddr
= *adjusted_insn_addr_end
;
1390 /* Finally, write a jump back to the program. */
1391 offset
= (tpaddr
+ 4) - buildaddr
;
1392 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1394 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1395 "(offset 0x%x > 26-bit).", offset
);
1399 p
+= GEN_B (p
, offset
);
1400 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1401 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1403 /* The jump pad is now built. Wire in a jump to our jump pad. This
1404 is always done last (by our caller actually), so that we can
1405 install fast tracepoints with threads running. This relies on
1406 the agent's atomic write support. */
1407 offset
= entryaddr
- tpaddr
;
1408 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1410 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1411 "(offset 0x%x > 26-bit).", offset
);
1415 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1416 *jjump_pad_insn_size
= 4;
1421 /* Returns the minimum instruction length for installing a tracepoint. */
1424 ppc_get_min_fast_tracepoint_insn_len (void)
1429 /* Emits a given buffer into the target at current_insn_ptr. Length
1430 is in units of 32-bit words. */
1433 emit_insns (uint32_t *buf
, int n
)
1435 n
= n
* sizeof (uint32_t);
1436 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1437 current_insn_ptr
+= n
;
1440 #define __EMIT_ASM(NAME, INSNS) \
1443 extern uint32_t start_bcax_ ## NAME []; \
1444 extern uint32_t end_bcax_ ## NAME []; \
1445 emit_insns (start_bcax_ ## NAME, \
1446 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1447 __asm__ (".section .text.__ppcbcax\n\t" \
1448 "start_bcax_" #NAME ":\n\t" \
1450 "end_bcax_" #NAME ":\n\t" \
1454 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1455 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1459 Bytecode execution stack frame - 32-bit
1461 | LR save area (SP + 4)
1462 SP' -> +- Back chain (SP + 0)
1463 | Save r31 for access saved arguments
1464 | Save r30 for bytecode stack pointer
1465 | Save r4 for incoming argument *value
1466 | Save r3 for incoming argument regs
1467 r30 -> +- Bytecode execution stack
1469 | 64-byte (8 doublewords) at initial.
1470 | Expand stack as needed.
1473 | Some padding for minimum stack frame and 16-byte alignment.
1475 SP +- Back-chain (SP')
1481 r30 is the stack-pointer for bytecode machine.
1482 It should point to next-empty, so we can use LDU for pop.
1483 r3 is used for cache of the high part of TOP value.
1484 It was the first argument, pointer to regs.
1485 r4 is used for cache of the low part of TOP value.
1486 It was the second argument, pointer to the result.
1487 We should set *result = TOP after leaving this function.
1490 * To restore stack at epilogue
1492 * To check stack is big enough for bytecode execution.
1494 * To return execution result.
1499 /* Regardless of endian, register 3 is always high part, 4 is low part.
1500 These defines are used when the register pair is stored/loaded.
1501 Likewise, to simplify code, have a similiar define for 5:6. */
1503 #if __BYTE_ORDER == __LITTLE_ENDIAN
1504 #define TOP_FIRST "4"
1505 #define TOP_SECOND "3"
1506 #define TMP_FIRST "6"
1507 #define TMP_SECOND "5"
1509 #define TOP_FIRST "3"
1510 #define TOP_SECOND "4"
1511 #define TMP_FIRST "5"
1512 #define TMP_SECOND "6"
1515 /* Emit prologue in inferior memory. See above comments. */
1518 ppc_emit_prologue (void)
1520 EMIT_ASM (/* Save return address. */
1523 /* Adjust SP. 96 is the initial frame size. */
1525 /* Save r30 and incoming arguments. */
1526 "stw 31, 96-4(1) \n"
1527 "stw 30, 96-8(1) \n"
1528 "stw 4, 96-12(1) \n"
1529 "stw 3, 96-16(1) \n"
1530 /* Point r31 to original r1 for access arguments. */
1532 /* Set r30 to pointing stack-top. */
1534 /* Initial r3/TOP to 0. */
1539 /* Emit epilogue in inferior memory. See above comments. */
1542 ppc_emit_epilogue (void)
1544 EMIT_ASM (/* *result = TOP */
1546 "stw " TOP_FIRST
", 0(5) \n"
1547 "stw " TOP_SECOND
", 4(5) \n"
1548 /* Restore registers. */
1555 /* Return 0 for no-error. */
1561 /* TOP = stack[--sp] + TOP */
1566 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1567 "lwz " TMP_SECOND
", 4(30)\n"
1572 /* TOP = stack[--sp] - TOP */
1577 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1578 "lwz " TMP_SECOND
", 4(30) \n"
1580 "subfe 3, 3, 5 \n");
1583 /* TOP = stack[--sp] * TOP */
1588 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1589 "lwz " TMP_SECOND
", 4(30) \n"
1598 /* TOP = stack[--sp] << TOP */
1603 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1604 "lwz " TMP_SECOND
", 4(30) \n"
1605 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1606 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1607 "slw 5, 5, 4\n" /* Shift high part left */
1608 "slw 4, 6, 4\n" /* Shift low part left */
1609 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1610 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1612 "or 3, 7, 3\n"); /* Assemble high part */
1615 /* Top = stack[--sp] >> TOP
1616 (Arithmetic shift right) */
1619 ppc_emit_rsh_signed (void)
1621 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1622 "lwz " TMP_SECOND
", 4(30) \n"
1623 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1624 "sraw 3, 5, 4\n" /* Shift high part right */
1626 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1627 "sraw 4, 5, 7\n" /* Shift high to low */
1630 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1631 "srw 4, 6, 4\n" /* Shift low part right */
1632 "slw 5, 5, 7\n" /* Shift high to low */
1633 "or 4, 4, 5\n" /* Assemble low part */
1637 /* Top = stack[--sp] >> TOP
1638 (Logical shift right) */
1641 ppc_emit_rsh_unsigned (void)
1643 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1644 "lwz " TMP_SECOND
", 4(30) \n"
1645 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1646 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1647 "srw 6, 6, 4\n" /* Shift low part right */
1648 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1649 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1651 "srw 3, 5, 4\n" /* Shift high part right */
1652 "or 4, 6, 7\n"); /* Assemble low part */
1655 /* Emit code for signed-extension specified by ARG. */
1658 ppc_emit_ext (int arg
)
1663 EMIT_ASM ("extsb 4, 4\n"
1667 EMIT_ASM ("extsh 4, 4\n"
1671 EMIT_ASM ("srawi 3, 4, 31");
1678 /* Emit code for zero-extension specified by ARG. */
1681 ppc_emit_zero_ext (int arg
)
1686 EMIT_ASM ("clrlwi 4,4,24\n"
1690 EMIT_ASM ("clrlwi 4,4,16\n"
1694 EMIT_ASM ("li 3, 0");
1702 i.e., TOP = (TOP == 0) ? 1 : 0; */
1705 ppc_emit_log_not (void)
1707 EMIT_ASM ("or 4, 3, 4 \n"
1713 /* TOP = stack[--sp] & TOP */
1716 ppc_emit_bit_and (void)
1718 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1719 "lwz " TMP_SECOND
", 4(30) \n"
1724 /* TOP = stack[--sp] | TOP */
1727 ppc_emit_bit_or (void)
1729 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1730 "lwz " TMP_SECOND
", 4(30) \n"
1735 /* TOP = stack[--sp] ^ TOP */
1738 ppc_emit_bit_xor (void)
1740 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1741 "lwz " TMP_SECOND
", 4(30) \n"
1747 i.e., TOP = ~(TOP | TOP) */
1750 ppc_emit_bit_not (void)
1752 EMIT_ASM ("nor 3, 3, 3 \n"
1756 /* TOP = stack[--sp] == TOP */
1759 ppc_emit_equal (void)
1761 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1762 "lwz " TMP_SECOND
", 4(30) \n"
1771 /* TOP = stack[--sp] < TOP
1772 (Signed comparison) */
1775 ppc_emit_less_signed (void)
1777 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1778 "lwz " TMP_SECOND
", 4(30) \n"
1781 /* CR6 bit 0 = low less and high equal */
1782 "crand 6*4+0, 6*4+0, 7*4+2\n"
1783 /* CR7 bit 0 = (low less and high equal) or high less */
1784 "cror 7*4+0, 7*4+0, 6*4+0\n"
1786 "rlwinm 4, 4, 29, 31, 31 \n"
1790 /* TOP = stack[--sp] < TOP
1791 (Unsigned comparison) */
1794 ppc_emit_less_unsigned (void)
1796 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1797 "lwz " TMP_SECOND
", 4(30) \n"
1800 /* CR6 bit 0 = low less and high equal */
1801 "crand 6*4+0, 6*4+0, 7*4+2\n"
1802 /* CR7 bit 0 = (low less and high equal) or high less */
1803 "cror 7*4+0, 7*4+0, 6*4+0\n"
1805 "rlwinm 4, 4, 29, 31, 31 \n"
1809 /* Access the memory address in TOP in size of SIZE.
1810 Zero-extend the read value. */
1813 ppc_emit_ref (int size
)
1818 EMIT_ASM ("lbz 4, 0(4)\n"
1822 EMIT_ASM ("lhz 4, 0(4)\n"
1826 EMIT_ASM ("lwz 4, 0(4)\n"
1830 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1831 EMIT_ASM ("lwz 3, 4(4)\n"
1834 EMIT_ASM ("lwz 3, 0(4)\n"
1843 ppc_emit_const (LONGEST num
)
1848 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
1849 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
1851 emit_insns (buf
, p
- buf
);
1852 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1855 /* Set TOP to the value of register REG by calling get_raw_reg function
1856 with two argument, collected buffer and register number. */
1859 ppc_emit_reg (int reg
)
1864 /* fctx->regs is passed in r3 and then saved in -16(31). */
1865 p
+= GEN_LWZ (p
, 3, 31, -16);
1866 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
1867 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
1869 emit_insns (buf
, p
- buf
);
1870 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1872 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1874 EMIT_ASM ("mr 5, 4\n"
1880 /* TOP = stack[--sp] */
1885 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
1886 "lwz " TOP_SECOND
", 4(30) \n");
1889 /* stack[sp++] = TOP
1891 Because we may use up bytecode stack, expand 8 doublewords more
1895 ppc_emit_stack_flush (void)
1897 /* Make sure bytecode stack is big enough before push.
1898 Otherwise, expand 64-byte more. */
1900 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
1901 " stw " TOP_SECOND
", 4(30)\n"
1902 " addi 5, 30, -(8 + 8) \n"
1905 " stwu 31, -64(1) \n"
1906 "1:addi 30, 30, -8 \n");
1909 /* Swap TOP and stack[sp-1] */
1912 ppc_emit_swap (void)
1914 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
1915 "lwz " TMP_SECOND
", 12(30) \n"
1916 "stw " TOP_FIRST
", 8(30) \n"
1917 "stw " TOP_SECOND
", 12(30) \n"
1922 /* Discard N elements in the stack. Also used for ppc64. */
1925 ppc_emit_stack_adjust (int n
)
1937 p
+= GEN_ADDI (p
, 30, 30, n
);
1939 emit_insns (buf
, p
- buf
);
1940 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1943 /* Call function FN. */
1946 ppc_emit_call (CORE_ADDR fn
)
1951 p
+= gen_call (p
, fn
, 0, 0);
1953 emit_insns (buf
, p
- buf
);
1954 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1957 /* FN's prototype is `LONGEST(*fn)(int)'.
1962 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1967 /* Setup argument. arg1 is a 16-bit value. */
1968 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
1969 p
+= gen_call (p
, fn
, 0, 0);
1971 emit_insns (buf
, p
- buf
);
1972 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1974 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1976 EMIT_ASM ("mr 5, 4\n"
1982 /* FN's prototype is `void(*fn)(int,LONGEST)'.
1985 TOP should be preserved/restored before/after the call. */
1988 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
1993 /* Save TOP. 0(30) is next-empty. */
1994 p
+= GEN_STW (p
, 3, 30, 0);
1995 p
+= GEN_STW (p
, 4, 30, 4);
1997 /* Setup argument. arg1 is a 16-bit value. */
1998 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2000 p
+= GEN_MR (p
, 5, 4);
2001 p
+= GEN_MR (p
, 6, 3);
2005 p
+= GEN_MR (p
, 5, 3);
2006 p
+= GEN_MR (p
, 6, 4);
2008 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2009 p
+= gen_call (p
, fn
, 0, 0);
2012 p
+= GEN_LWZ (p
, 3, 30, 0);
2013 p
+= GEN_LWZ (p
, 4, 30, 4);
2015 emit_insns (buf
, p
- buf
);
2016 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2019 /* Note in the following goto ops:
2021 When emitting goto, the target address is later relocated by
2022 write_goto_address. OFFSET_P is the offset of the branch instruction
2023 in the code sequence, and SIZE_P is how to relocate the instruction,
2024 recognized by ppc_write_goto_address. In current implementation,
2025 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2028 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2031 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2033 EMIT_ASM ("or. 3, 3, 4 \n"
2034 "lwzu " TOP_FIRST
", 8(30) \n"
2035 "lwz " TOP_SECOND
", 4(30) \n"
2044 /* Unconditional goto. Also used for ppc64. */
2047 ppc_emit_goto (int *offset_p
, int *size_p
)
2049 EMIT_ASM ("1:b 1b");
2057 /* Goto if stack[--sp] == TOP */
2060 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2062 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2063 "lwz " TMP_SECOND
", 4(30) \n"
2067 "lwzu " TOP_FIRST
", 8(30) \n"
2068 "lwz " TOP_SECOND
", 4(30) \n"
2077 /* Goto if stack[--sp] != TOP */
2080 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2082 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2083 "lwz " TMP_SECOND
", 4(30) \n"
2087 "lwzu " TOP_FIRST
", 8(30) \n"
2088 "lwz " TOP_SECOND
", 4(30) \n"
2097 /* Goto if stack[--sp] < TOP */
2100 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2102 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2103 "lwz " TMP_SECOND
", 4(30) \n"
2106 /* CR6 bit 0 = low less and high equal */
2107 "crand 6*4+0, 6*4+0, 7*4+2\n"
2108 /* CR7 bit 0 = (low less and high equal) or high less */
2109 "cror 7*4+0, 7*4+0, 6*4+0\n"
2110 "lwzu " TOP_FIRST
", 8(30) \n"
2111 "lwz " TOP_SECOND
", 4(30)\n"
2120 /* Goto if stack[--sp] <= TOP */
2123 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2125 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2126 "lwz " TMP_SECOND
", 4(30) \n"
2129 /* CR6 bit 0 = low less/equal and high equal */
2130 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2131 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2132 "cror 7*4+0, 7*4+0, 6*4+0\n"
2133 "lwzu " TOP_FIRST
", 8(30) \n"
2134 "lwz " TOP_SECOND
", 4(30)\n"
2143 /* Goto if stack[--sp] > TOP */
2146 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2148 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2149 "lwz " TMP_SECOND
", 4(30) \n"
2152 /* CR6 bit 0 = low greater and high equal */
2153 "crand 6*4+0, 6*4+1, 7*4+2\n"
2154 /* CR7 bit 0 = (low greater and high equal) or high greater */
2155 "cror 7*4+0, 7*4+1, 6*4+0\n"
2156 "lwzu " TOP_FIRST
", 8(30) \n"
2157 "lwz " TOP_SECOND
", 4(30)\n"
2166 /* Goto if stack[--sp] >= TOP */
2169 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2171 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2172 "lwz " TMP_SECOND
", 4(30) \n"
2175 /* CR6 bit 0 = low ge and high equal */
2176 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2177 /* CR7 bit 0 = (low ge and high equal) or high greater */
2178 "cror 7*4+0, 7*4+1, 6*4+0\n"
2179 "lwzu " TOP_FIRST
", 8(30)\n"
2180 "lwz " TOP_SECOND
", 4(30)\n"
2189 /* Relocate previous emitted branch instruction. FROM is the address
2190 of the branch instruction, TO is the goto target address, and SIZE
2191 if the value we set by *SIZE_P before. Currently, it is either
2192 24 or 14 of branch and conditional-branch instruction.
2193 Also used for ppc64. */
2196 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2198 long rel
= to
- from
;
2202 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2203 opcd
= (insn
>> 26) & 0x3f;
2209 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2211 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2215 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2217 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2224 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2227 /* Table of emit ops for 32-bit. */
2229 static struct emit_ops ppc_emit_ops_impl
=
2237 ppc_emit_rsh_signed
,
2238 ppc_emit_rsh_unsigned
,
2246 ppc_emit_less_signed
,
2247 ppc_emit_less_unsigned
,
2251 ppc_write_goto_address
,
2256 ppc_emit_stack_flush
,
2259 ppc_emit_stack_adjust
,
2260 ppc_emit_int_call_1
,
2261 ppc_emit_void_call_2
,
2270 #ifdef __powerpc64__
2274 Bytecode execution stack frame - 64-bit
2276 | LR save area (SP + 16)
2277 | CR save area (SP + 8)
2278 SP' -> +- Back chain (SP + 0)
2279 | Save r31 for access saved arguments
2280 | Save r30 for bytecode stack pointer
2281 | Save r4 for incoming argument *value
2282 | Save r3 for incoming argument regs
2283 r30 -> +- Bytecode execution stack
2285 | 64-byte (8 doublewords) at initial.
2286 | Expand stack as needed.
2289 | Some padding for minimum stack frame.
2291 SP +- Back-chain (SP')
2294 = 112 + (4 * 8) + 64
2297 r30 is the stack-pointer for bytecode machine.
2298 It should point to next-empty, so we can use LDU for pop.
2299 r3 is used for cache of TOP value.
2300 It was the first argument, pointer to regs.
2301 r4 is the second argument, pointer to the result.
2302 We should set *result = TOP after leaving this function.
2305 * To restore stack at epilogue
2307 * To check stack is big enough for bytecode execution.
2308 => r30 - 8 > SP + 112
2309 * To return execution result.
2314 /* Emit prologue in inferior memory. See above comments. */
2317 ppc64v1_emit_prologue (void)
2319 /* On ELFv1, function pointers really point to function descriptor,
2320 so emit one here. We don't care about contents of words 1 and 2,
2321 so let them just overlap out code. */
2322 uint64_t opd
= current_insn_ptr
+ 8;
2325 /* Mind the strict aliasing rules. */
2326 memcpy (buf
, &opd
, sizeof buf
);
2328 EMIT_ASM (/* Save return address. */
2331 /* Save r30 and incoming arguments. */
2336 /* Point r31 to current r1 for access arguments. */
2338 /* Adjust SP. 208 is the initial frame size. */
2339 "stdu 1, -208(1) \n"
2340 /* Set r30 to pointing stack-top. */
2341 "addi 30, 1, 168 \n"
2342 /* Initial r3/TOP to 0. */
2346 /* Emit prologue in inferior memory. See above comments. */
2349 ppc64v2_emit_prologue (void)
2351 EMIT_ASM (/* Save return address. */
2354 /* Save r30 and incoming arguments. */
2359 /* Point r31 to current r1 for access arguments. */
2361 /* Adjust SP. 208 is the initial frame size. */
2362 "stdu 1, -208(1) \n"
2363 /* Set r30 to pointing stack-top. */
2364 "addi 30, 1, 168 \n"
2365 /* Initial r3/TOP to 0. */
2369 /* Emit epilogue in inferior memory. See above comments. */
2372 ppc64_emit_epilogue (void)
2374 EMIT_ASM (/* Restore SP. */
2379 /* Restore registers. */
2384 /* Return 0 for no-error. */
2390 /* TOP = stack[--sp] + TOP */
2393 ppc64_emit_add (void)
2395 EMIT_ASM ("ldu 4, 8(30) \n"
2399 /* TOP = stack[--sp] - TOP */
2402 ppc64_emit_sub (void)
2404 EMIT_ASM ("ldu 4, 8(30) \n"
2408 /* TOP = stack[--sp] * TOP */
2411 ppc64_emit_mul (void)
2413 EMIT_ASM ("ldu 4, 8(30) \n"
2414 "mulld 3, 4, 3 \n");
2417 /* TOP = stack[--sp] << TOP */
2420 ppc64_emit_lsh (void)
2422 EMIT_ASM ("ldu 4, 8(30) \n"
2426 /* Top = stack[--sp] >> TOP
2427 (Arithmetic shift right) */
2430 ppc64_emit_rsh_signed (void)
2432 EMIT_ASM ("ldu 4, 8(30) \n"
2436 /* Top = stack[--sp] >> TOP
2437 (Logical shift right) */
2440 ppc64_emit_rsh_unsigned (void)
2442 EMIT_ASM ("ldu 4, 8(30) \n"
2446 /* Emit code for signed-extension specified by ARG. */
2449 ppc64_emit_ext (int arg
)
2454 EMIT_ASM ("extsb 3, 3");
2457 EMIT_ASM ("extsh 3, 3");
2460 EMIT_ASM ("extsw 3, 3");
2467 /* Emit code for zero-extension specified by ARG. */
2470 ppc64_emit_zero_ext (int arg
)
2475 EMIT_ASM ("rldicl 3,3,0,56");
2478 EMIT_ASM ("rldicl 3,3,0,48");
2481 EMIT_ASM ("rldicl 3,3,0,32");
2489 i.e., TOP = (TOP == 0) ? 1 : 0; */
2492 ppc64_emit_log_not (void)
2494 EMIT_ASM ("cntlzd 3, 3 \n"
2498 /* TOP = stack[--sp] & TOP */
2501 ppc64_emit_bit_and (void)
2503 EMIT_ASM ("ldu 4, 8(30) \n"
2507 /* TOP = stack[--sp] | TOP */
2510 ppc64_emit_bit_or (void)
2512 EMIT_ASM ("ldu 4, 8(30) \n"
2516 /* TOP = stack[--sp] ^ TOP */
2519 ppc64_emit_bit_xor (void)
2521 EMIT_ASM ("ldu 4, 8(30) \n"
2526 i.e., TOP = ~(TOP | TOP) */
2529 ppc64_emit_bit_not (void)
2531 EMIT_ASM ("nor 3, 3, 3 \n");
2534 /* TOP = stack[--sp] == TOP */
2537 ppc64_emit_equal (void)
2539 EMIT_ASM ("ldu 4, 8(30) \n"
2545 /* TOP = stack[--sp] < TOP
2546 (Signed comparison) */
2549 ppc64_emit_less_signed (void)
2551 EMIT_ASM ("ldu 4, 8(30) \n"
2554 "rlwinm 3, 3, 29, 31, 31 \n");
2557 /* TOP = stack[--sp] < TOP
2558 (Unsigned comparison) */
2561 ppc64_emit_less_unsigned (void)
2563 EMIT_ASM ("ldu 4, 8(30) \n"
2566 "rlwinm 3, 3, 29, 31, 31 \n");
2569 /* Access the memory address in TOP in size of SIZE.
2570 Zero-extend the read value. */
2573 ppc64_emit_ref (int size
)
2578 EMIT_ASM ("lbz 3, 0(3)");
2581 EMIT_ASM ("lhz 3, 0(3)");
2584 EMIT_ASM ("lwz 3, 0(3)");
2587 EMIT_ASM ("ld 3, 0(3)");
2595 ppc64_emit_const (LONGEST num
)
2600 p
+= gen_limm (p
, 3, num
, 1);
2602 emit_insns (buf
, p
- buf
);
2603 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2606 /* Set TOP to the value of register REG by calling get_raw_reg function
2607 with two argument, collected buffer and register number. */
2610 ppc64v1_emit_reg (int reg
)
2615 /* fctx->regs is passed in r3 and then saved in 176(1). */
2616 p
+= GEN_LD (p
, 3, 31, -32);
2617 p
+= GEN_LI (p
, 4, reg
);
2618 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2619 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2620 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2622 emit_insns (buf
, p
- buf
);
2623 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2626 /* Likewise, for ELFv2. */
2629 ppc64v2_emit_reg (int reg
)
2634 /* fctx->regs is passed in r3 and then saved in 176(1). */
2635 p
+= GEN_LD (p
, 3, 31, -32);
2636 p
+= GEN_LI (p
, 4, reg
);
2637 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2638 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2639 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2641 emit_insns (buf
, p
- buf
);
2642 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2645 /* TOP = stack[--sp] */
2648 ppc64_emit_pop (void)
2650 EMIT_ASM ("ldu 3, 8(30)");
2653 /* stack[sp++] = TOP
2655 Because we may use up bytecode stack, expand 8 doublewords more
2659 ppc64_emit_stack_flush (void)
2661 /* Make sure bytecode stack is big enough before push.
2662 Otherwise, expand 64-byte more. */
2664 EMIT_ASM (" std 3, 0(30) \n"
2665 " addi 4, 30, -(112 + 8) \n"
2668 " stdu 31, -64(1) \n"
2669 "1:addi 30, 30, -8 \n");
2672 /* Swap TOP and stack[sp-1] */
2675 ppc64_emit_swap (void)
2677 EMIT_ASM ("ld 4, 8(30) \n"
2682 /* Call function FN - ELFv1. */
2685 ppc64v1_emit_call (CORE_ADDR fn
)
2690 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2691 p
+= gen_call (p
, fn
, 1, 1);
2692 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2694 emit_insns (buf
, p
- buf
);
2695 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2698 /* Call function FN - ELFv2. */
2701 ppc64v2_emit_call (CORE_ADDR fn
)
2706 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2707 p
+= gen_call (p
, fn
, 1, 0);
2708 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2710 emit_insns (buf
, p
- buf
);
2711 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2714 /* FN's prototype is `LONGEST(*fn)(int)'.
2719 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2724 /* Setup argument. arg1 is a 16-bit value. */
2725 p
+= gen_limm (p
, 3, arg1
, 1);
2726 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2727 p
+= gen_call (p
, fn
, 1, 1);
2728 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2730 emit_insns (buf
, p
- buf
);
2731 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2734 /* Likewise for ELFv2. */
2737 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2742 /* Setup argument. arg1 is a 16-bit value. */
2743 p
+= gen_limm (p
, 3, arg1
, 1);
2744 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2745 p
+= gen_call (p
, fn
, 1, 0);
2746 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2748 emit_insns (buf
, p
- buf
);
2749 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2752 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2755 TOP should be preserved/restored before/after the call. */
2758 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2763 /* Save TOP. 0(30) is next-empty. */
2764 p
+= GEN_STD (p
, 3, 30, 0);
2766 /* Setup argument. arg1 is a 16-bit value. */
2767 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2768 p
+= gen_limm (p
, 3, arg1
, 1);
2769 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2770 p
+= gen_call (p
, fn
, 1, 1);
2771 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2774 p
+= GEN_LD (p
, 3, 30, 0);
2776 emit_insns (buf
, p
- buf
);
2777 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2780 /* Likewise for ELFv2. */
2783 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2788 /* Save TOP. 0(30) is next-empty. */
2789 p
+= GEN_STD (p
, 3, 30, 0);
2791 /* Setup argument. arg1 is a 16-bit value. */
2792 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2793 p
+= gen_limm (p
, 3, arg1
, 1);
2794 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2795 p
+= gen_call (p
, fn
, 1, 0);
2796 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2799 p
+= GEN_LD (p
, 3, 30, 0);
2801 emit_insns (buf
, p
- buf
);
2802 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2805 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2808 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
2810 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2820 /* Goto if stack[--sp] == TOP */
2823 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
2825 EMIT_ASM ("ldu 4, 8(30) \n"
2836 /* Goto if stack[--sp] != TOP */
2839 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
2841 EMIT_ASM ("ldu 4, 8(30) \n"
2852 /* Goto if stack[--sp] < TOP */
2855 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
2857 EMIT_ASM ("ldu 4, 8(30) \n"
2868 /* Goto if stack[--sp] <= TOP */
2871 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
2873 EMIT_ASM ("ldu 4, 8(30) \n"
2884 /* Goto if stack[--sp] > TOP */
2887 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
2889 EMIT_ASM ("ldu 4, 8(30) \n"
2900 /* Goto if stack[--sp] >= TOP */
2903 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
2905 EMIT_ASM ("ldu 4, 8(30) \n"
2916 /* Table of emit ops for 64-bit ELFv1. */
2918 static struct emit_ops ppc64v1_emit_ops_impl
=
2920 ppc64v1_emit_prologue
,
2921 ppc64_emit_epilogue
,
2926 ppc64_emit_rsh_signed
,
2927 ppc64_emit_rsh_unsigned
,
2935 ppc64_emit_less_signed
,
2936 ppc64_emit_less_unsigned
,
2940 ppc_write_goto_address
,
2945 ppc64_emit_stack_flush
,
2946 ppc64_emit_zero_ext
,
2948 ppc_emit_stack_adjust
,
2949 ppc64v1_emit_int_call_1
,
2950 ppc64v1_emit_void_call_2
,
2959 /* Table of emit ops for 64-bit ELFv2. */
2961 static struct emit_ops ppc64v2_emit_ops_impl
=
2963 ppc64v2_emit_prologue
,
2964 ppc64_emit_epilogue
,
2969 ppc64_emit_rsh_signed
,
2970 ppc64_emit_rsh_unsigned
,
2978 ppc64_emit_less_signed
,
2979 ppc64_emit_less_unsigned
,
2983 ppc_write_goto_address
,
2988 ppc64_emit_stack_flush
,
2989 ppc64_emit_zero_ext
,
2991 ppc_emit_stack_adjust
,
2992 ppc64v2_emit_int_call_1
,
2993 ppc64v2_emit_void_call_2
,
3004 /* Implementation of linux_target_ops method "emit_ops". */
3006 static struct emit_ops
*
3009 #ifdef __powerpc64__
3010 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3012 if (register_size (regcache
->tdesc
, 0) == 8)
3014 if (is_elfv2_inferior ())
3015 return &ppc64v2_emit_ops_impl
;
3017 return &ppc64v1_emit_ops_impl
;
3020 return &ppc_emit_ops_impl
;
3023 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3026 ppc_get_ipa_tdesc_idx (void)
3028 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3029 const struct target_desc
*tdesc
= regcache
->tdesc
;
3031 #ifdef __powerpc64__
3032 if (tdesc
== tdesc_powerpc_64l
)
3033 return PPC_TDESC_BASE
;
3034 if (tdesc
== tdesc_powerpc_altivec64l
)
3035 return PPC_TDESC_ALTIVEC
;
3036 if (tdesc
== tdesc_powerpc_cell64l
)
3037 return PPC_TDESC_CELL
;
3038 if (tdesc
== tdesc_powerpc_vsx64l
)
3039 return PPC_TDESC_VSX
;
3040 if (tdesc
== tdesc_powerpc_isa205_64l
)
3041 return PPC_TDESC_ISA205
;
3042 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3043 return PPC_TDESC_ISA205_ALTIVEC
;
3044 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3045 return PPC_TDESC_ISA205_VSX
;
3048 if (tdesc
== tdesc_powerpc_32l
)
3049 return PPC_TDESC_BASE
;
3050 if (tdesc
== tdesc_powerpc_altivec32l
)
3051 return PPC_TDESC_ALTIVEC
;
3052 if (tdesc
== tdesc_powerpc_cell32l
)
3053 return PPC_TDESC_CELL
;
3054 if (tdesc
== tdesc_powerpc_vsx32l
)
3055 return PPC_TDESC_VSX
;
3056 if (tdesc
== tdesc_powerpc_isa205_32l
)
3057 return PPC_TDESC_ISA205
;
3058 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3059 return PPC_TDESC_ISA205_ALTIVEC
;
3060 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3061 return PPC_TDESC_ISA205_VSX
;
3062 if (tdesc
== tdesc_powerpc_e500l
)
3063 return PPC_TDESC_E500
;
3068 struct linux_target_ops the_low_target
= {
3071 ppc_cannot_fetch_register
,
3072 ppc_cannot_store_register
,
3073 NULL
, /* fetch_register */
3076 NULL
, /* breakpoint_kind_from_pc */
3077 ppc_sw_breakpoint_from_kind
,
3081 ppc_supports_z_point_type
,
3086 ppc_collect_ptrace_register
,
3087 ppc_supply_ptrace_register
,
3088 NULL
, /* siginfo_fixup */
3089 NULL
, /* new_process */
3090 NULL
, /* delete_process */
3091 NULL
, /* new_thread */
3092 NULL
, /* delete_thread */
3093 NULL
, /* new_fork */
3094 NULL
, /* prepare_to_resume */
3095 NULL
, /* process_qsupported */
3096 ppc_supports_tracepoints
,
3097 ppc_get_thread_area
,
3098 ppc_install_fast_tracepoint_jump_pad
,
3100 ppc_get_min_fast_tracepoint_insn_len
,
3101 NULL
, /* supports_range_stepping */
3102 NULL
, /* breakpoint_kind_from_current_state */
3103 ppc_supports_hardware_single_step
,
3104 NULL
, /* get_syscall_trapinfo */
3105 ppc_get_ipa_tdesc_idx
,
3109 initialize_low_arch (void)
3111 /* Initialize the Linux target descriptions. */
3113 init_registers_powerpc_32l ();
3114 init_registers_powerpc_altivec32l ();
3115 init_registers_powerpc_cell32l ();
3116 init_registers_powerpc_vsx32l ();
3117 init_registers_powerpc_isa205_32l ();
3118 init_registers_powerpc_isa205_altivec32l ();
3119 init_registers_powerpc_isa205_vsx32l ();
3120 init_registers_powerpc_e500l ();
3122 init_registers_powerpc_64l ();
3123 init_registers_powerpc_altivec64l ();
3124 init_registers_powerpc_cell64l ();
3125 init_registers_powerpc_vsx64l ();
3126 init_registers_powerpc_isa205_64l ();
3127 init_registers_powerpc_isa205_altivec64l ();
3128 init_registers_powerpc_isa205_vsx64l ();
3131 initialize_regsets_info (&ppc_regsets_info
);