1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Holds the AT_HWCAP auxv entry. */
49 static unsigned long ppc_hwcap
;
51 /* Holds the AT_HWCAP2 auxv entry. */
53 static unsigned long ppc_hwcap2
;
56 #define ppc_num_regs 73
59 /* We use a constant for FPSCR instead of PT_FPSCR, because
60 many shipped PPC64 kernels had the wrong value in ptrace.h. */
61 static int ppc_regmap
[] =
62 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
63 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
64 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
65 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
66 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
67 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
68 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
69 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
70 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
71 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
72 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
73 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
74 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
75 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
76 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
77 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
78 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
79 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
80 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
82 /* Currently, don't check/send MQ. */
83 static int ppc_regmap
[] =
84 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
85 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
86 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
87 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
88 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
89 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
90 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
91 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
92 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
93 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
94 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
95 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
96 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
97 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
98 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
99 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
100 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
101 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
102 PT_ORIG_R3
* 4, PT_TRAP
* 4
105 static int ppc_regmap_e500
[] =
106 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
107 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
108 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
109 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
110 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
111 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
112 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
113 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
122 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
123 PT_CTR
* 4, PT_XER
* 4, -1,
124 PT_ORIG_R3
* 4, PT_TRAP
* 4
128 /* Check whether the kernel provides a register set with number
129 REGSET_ID of size REGSETSIZE for process/thread TID. */
132 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
134 void *buf
= alloca (regsetsize
);
138 iov
.iov_len
= regsetsize
;
140 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
147 ppc_cannot_store_register (int regno
)
149 const struct target_desc
*tdesc
= current_process ()->tdesc
;
151 #ifndef __powerpc64__
152 /* Some kernels do not allow us to store fpscr. */
153 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
154 && regno
== find_regno (tdesc
, "fpscr"))
158 /* Some kernels do not allow us to store orig_r3 or trap. */
159 if (regno
== find_regno (tdesc
, "orig_r3")
160 || regno
== find_regno (tdesc
, "trap"))
167 ppc_cannot_fetch_register (int regno
)
173 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
175 memset (buf
, 0, sizeof (long));
177 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
179 /* Little-endian values always sit at the left end of the buffer. */
180 collect_register (regcache
, regno
, buf
);
182 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
184 /* Big-endian values sit at the right end of the buffer. In case of
185 registers whose sizes are smaller than sizeof (long), we must use a
186 padding to access them correctly. */
187 int size
= register_size (regcache
->tdesc
, regno
);
189 if (size
< sizeof (long))
190 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
192 collect_register (regcache
, regno
, buf
);
195 perror_with_name ("Unexpected byte order");
199 ppc_supply_ptrace_register (struct regcache
*regcache
,
200 int regno
, const char *buf
)
202 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
204 /* Little-endian values always sit at the left end of the buffer. */
205 supply_register (regcache
, regno
, buf
);
207 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
209 /* Big-endian values sit at the right end of the buffer. In case of
210 registers whose sizes are smaller than sizeof (long), we must use a
211 padding to access them correctly. */
212 int size
= register_size (regcache
->tdesc
, regno
);
214 if (size
< sizeof (long))
215 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
217 supply_register (regcache
, regno
, buf
);
220 perror_with_name ("Unexpected byte order");
224 #define INSTR_SC 0x44000002
225 #define NR_spu_run 0x0116
227 /* If the PPU thread is currently stopped on a spu_run system call,
228 return to FD and ADDR the file handle and NPC parameter address
229 used with the system call. Return non-zero if successful. */
231 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
237 if (register_size (regcache
->tdesc
, 0) == 4)
239 unsigned int pc
, r0
, r3
, r4
;
240 collect_register_by_name (regcache
, "pc", &pc
);
241 collect_register_by_name (regcache
, "r0", &r0
);
242 collect_register_by_name (regcache
, "orig_r3", &r3
);
243 collect_register_by_name (regcache
, "r4", &r4
);
244 curr_pc
= (CORE_ADDR
) pc
;
247 *addr
= (CORE_ADDR
) r4
;
251 unsigned long pc
, r0
, r3
, r4
;
252 collect_register_by_name (regcache
, "pc", &pc
);
253 collect_register_by_name (regcache
, "r0", &r0
);
254 collect_register_by_name (regcache
, "orig_r3", &r3
);
255 collect_register_by_name (regcache
, "r4", &r4
);
256 curr_pc
= (CORE_ADDR
) pc
;
259 *addr
= (CORE_ADDR
) r4
;
262 /* Fetch instruction preceding current NIP. */
263 if ((*the_target
->read_memory
) (curr_pc
- 4,
264 (unsigned char *) &curr_insn
, 4) != 0)
266 /* It should be a "sc" instruction. */
267 if (curr_insn
!= INSTR_SC
)
269 /* System call number should be NR_spu_run. */
270 if (curr_r0
!= NR_spu_run
)
277 ppc_get_pc (struct regcache
*regcache
)
282 if (parse_spufs_run (regcache
, &fd
, &addr
))
285 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
286 return ((CORE_ADDR
)1 << 63)
287 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
289 else if (register_size (regcache
->tdesc
, 0) == 4)
292 collect_register_by_name (regcache
, "pc", &pc
);
293 return (CORE_ADDR
) pc
;
298 collect_register_by_name (regcache
, "pc", &pc
);
299 return (CORE_ADDR
) pc
;
304 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
309 if (parse_spufs_run (regcache
, &fd
, &addr
))
311 unsigned int newpc
= pc
;
312 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
314 else if (register_size (regcache
->tdesc
, 0) == 4)
316 unsigned int newpc
= pc
;
317 supply_register_by_name (regcache
, "pc", &newpc
);
321 unsigned long newpc
= pc
;
322 supply_register_by_name (regcache
, "pc", &newpc
);
326 #ifndef __powerpc64__
327 static int ppc_regmap_adjusted
;
331 /* Correct in either endianness.
332 This instruction is "twge r2, r2", which GDB uses as a software
334 static const unsigned int ppc_breakpoint
= 0x7d821008;
335 #define ppc_breakpoint_len 4
337 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
339 static const gdb_byte
*
340 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
342 *size
= ppc_breakpoint_len
;
343 return (const gdb_byte
*) &ppc_breakpoint
;
347 ppc_breakpoint_at (CORE_ADDR where
)
351 if (where
& ((CORE_ADDR
)1 << 63))
354 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
355 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
356 NULL
, where
& 0xffffffff, 4);
362 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
363 if (insn
== ppc_breakpoint
)
365 /* If necessary, recognize more trap instructions here. GDB only uses
372 /* Implement supports_z_point_type target-ops.
373 Returns true if type Z_TYPE breakpoint is supported.
375 Handling software breakpoint at server side, so tracepoints
376 and breakpoints can be inserted at the same location. */
379 ppc_supports_z_point_type (char z_type
)
386 case Z_PACKET_WRITE_WP
:
387 case Z_PACKET_ACCESS_WP
:
393 /* Implement insert_point target-ops.
394 Returns 0 on success, -1 on failure and 1 on unsupported. */
397 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
398 int size
, struct raw_breakpoint
*bp
)
402 case raw_bkpt_type_sw
:
403 return insert_memory_breakpoint (bp
);
405 case raw_bkpt_type_hw
:
406 case raw_bkpt_type_write_wp
:
407 case raw_bkpt_type_access_wp
:
414 /* Implement remove_point target-ops.
415 Returns 0 on success, -1 on failure and 1 on unsupported. */
418 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
419 int size
, struct raw_breakpoint
*bp
)
423 case raw_bkpt_type_sw
:
424 return remove_memory_breakpoint (bp
);
426 case raw_bkpt_type_hw
:
427 case raw_bkpt_type_write_wp
:
428 case raw_bkpt_type_access_wp
:
435 /* Provide only a fill function for the general register set. ps_lgetregs
436 will use this for NPTL support. */
438 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
442 for (i
= 0; i
< 32; i
++)
443 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
445 for (i
= 64; i
< 70; i
++)
446 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
448 for (i
= 71; i
< 73; i
++)
449 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
452 /* Program Priority Register regset fill function. */
455 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
457 char *ppr
= (char *) buf
;
459 collect_register_by_name (regcache
, "ppr", ppr
);
462 /* Program Priority Register regset store function. */
465 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
467 const char *ppr
= (const char *) buf
;
469 supply_register_by_name (regcache
, "ppr", ppr
);
472 /* Data Stream Control Register regset fill function. */
475 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
477 char *dscr
= (char *) buf
;
479 collect_register_by_name (regcache
, "dscr", dscr
);
482 /* Data Stream Control Register regset store function. */
485 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
487 const char *dscr
= (const char *) buf
;
489 supply_register_by_name (regcache
, "dscr", dscr
);
492 /* Target Address Register regset fill function. */
495 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
497 char *tar
= (char *) buf
;
499 collect_register_by_name (regcache
, "tar", tar
);
502 /* Target Address Register regset store function. */
505 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
507 const char *tar
= (const char *) buf
;
509 supply_register_by_name (regcache
, "tar", tar
);
512 /* Event-Based Branching regset store function. Unless the inferior
513 has a perf event open, ptrace can return in error when reading and
514 writing to the regset, with ENODATA. For reading, the registers
515 will correctly show as unavailable. For writing, gdbserver
516 currently only caches any register writes from P and G packets and
517 the stub always tries to write all the regsets when resuming the
518 inferior, which would result in frequent warnings. For this
519 reason, we don't define a fill function. This also means that the
520 client-side regcache will be dirty if the user tries to write to
521 the EBB registers. G packets that the client sends to write to
522 unrelated registers will also include data for EBB registers, even
523 if they are unavailable. */
526 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
528 const char *regset
= (const char *) buf
;
530 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
531 .dat file is BESCR, EBBHR, EBBRR. */
532 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
533 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
534 supply_register_by_name (regcache
, "bescr", ®set
[16]);
537 /* Performance Monitoring Unit regset fill function. */
540 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
542 char *regset
= (char *) buf
;
544 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
545 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
546 collect_register_by_name (regcache
, "siar", ®set
[0]);
547 collect_register_by_name (regcache
, "sdar", ®set
[8]);
548 collect_register_by_name (regcache
, "sier", ®set
[16]);
549 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
550 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
553 /* Performance Monitoring Unit regset store function. */
556 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
558 const char *regset
= (const char *) buf
;
560 supply_register_by_name (regcache
, "siar", ®set
[0]);
561 supply_register_by_name (regcache
, "sdar", ®set
[8]);
562 supply_register_by_name (regcache
, "sier", ®set
[16]);
563 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
564 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
567 /* Hardware Transactional Memory special-purpose register regset fill
571 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
574 char *regset
= (char *) buf
;
576 base
= find_regno (regcache
->tdesc
, "tfhar");
577 for (i
= 0; i
< 3; i
++)
578 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
581 /* Hardware Transactional Memory special-purpose register regset store
585 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
588 const char *regset
= (const char *) buf
;
590 base
= find_regno (regcache
->tdesc
, "tfhar");
591 for (i
= 0; i
< 3; i
++)
592 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
595 /* For the same reasons as the EBB regset, none of the HTM
596 checkpointed regsets have a fill function. These registers are
597 only available if the inferior is in a transaction. */
599 /* Hardware Transactional Memory checkpointed general-purpose regset
603 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
605 int i
, base
, size
, endian_offset
;
606 const char *regset
= (const char *) buf
;
608 base
= find_regno (regcache
->tdesc
, "cr0");
609 size
= register_size (regcache
->tdesc
, base
);
611 gdb_assert (size
== 4 || size
== 8);
613 for (i
= 0; i
< 32; i
++)
614 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
618 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
621 supply_register_by_name (regcache
, "ccr",
622 ®set
[PT_CCR
* size
+ endian_offset
]);
624 supply_register_by_name (regcache
, "cxer",
625 ®set
[PT_XER
* size
+ endian_offset
]);
627 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
628 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
631 /* Hardware Transactional Memory checkpointed floating-point regset
635 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
638 const char *regset
= (const char *) buf
;
640 base
= find_regno (regcache
->tdesc
, "cf0");
642 for (i
= 0; i
< 32; i
++)
643 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
645 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
648 /* Hardware Transactional Memory checkpointed vector regset store
652 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
655 const char *regset
= (const char *) buf
;
658 base
= find_regno (regcache
->tdesc
, "cvr0");
660 for (i
= 0; i
< 32; i
++)
661 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
663 if (__BYTE_ORDER
== __BIG_ENDIAN
)
666 supply_register_by_name (regcache
, "cvscr",
667 ®set
[32 * 16 + vscr_offset
]);
669 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
672 /* Hardware Transactional Memory checkpointed vector-scalar regset
676 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
679 const char *regset
= (const char *) buf
;
681 base
= find_regno (regcache
->tdesc
, "cvs0h");
682 for (i
= 0; i
< 32; i
++)
683 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
686 /* Hardware Transactional Memory checkpointed Program Priority
687 Register regset store function. */
690 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
692 const char *cppr
= (const char *) buf
;
694 supply_register_by_name (regcache
, "cppr", cppr
);
697 /* Hardware Transactional Memory checkpointed Data Stream Control
698 Register regset store function. */
701 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
703 const char *cdscr
= (const char *) buf
;
705 supply_register_by_name (regcache
, "cdscr", cdscr
);
708 /* Hardware Transactional Memory checkpointed Target Address Register
709 regset store function. */
712 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
714 const char *ctar
= (const char *) buf
;
716 supply_register_by_name (regcache
, "ctar", ctar
);
720 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
723 char *regset
= (char *) buf
;
725 base
= find_regno (regcache
->tdesc
, "vs0h");
726 for (i
= 0; i
< 32; i
++)
727 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
731 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
734 const char *regset
= (const char *) buf
;
736 base
= find_regno (regcache
->tdesc
, "vs0h");
737 for (i
= 0; i
< 32; i
++)
738 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
742 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
745 char *regset
= (char *) buf
;
748 base
= find_regno (regcache
->tdesc
, "vr0");
749 for (i
= 0; i
< 32; i
++)
750 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
752 if (__BYTE_ORDER
== __BIG_ENDIAN
)
755 collect_register_by_name (regcache
, "vscr",
756 ®set
[32 * 16 + vscr_offset
]);
758 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
762 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
765 const char *regset
= (const char *) buf
;
768 base
= find_regno (regcache
->tdesc
, "vr0");
769 for (i
= 0; i
< 32; i
++)
770 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
772 if (__BYTE_ORDER
== __BIG_ENDIAN
)
775 supply_register_by_name (regcache
, "vscr",
776 ®set
[32 * 16 + vscr_offset
]);
777 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
780 struct gdb_evrregset_t
782 unsigned long evr
[32];
783 unsigned long long acc
;
784 unsigned long spefscr
;
788 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
791 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
793 ev0
= find_regno (regcache
->tdesc
, "ev0h");
794 for (i
= 0; i
< 32; i
++)
795 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
797 collect_register_by_name (regcache
, "acc", ®set
->acc
);
798 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
802 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
805 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
807 ev0
= find_regno (regcache
->tdesc
, "ev0h");
808 for (i
= 0; i
< 32; i
++)
809 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
811 supply_register_by_name (regcache
, "acc", ®set
->acc
);
812 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
815 /* Support for hardware single step. */
818 ppc_supports_hardware_single_step (void)
823 static struct regset_info ppc_regsets
[] = {
824 /* List the extra register sets before GENERAL_REGS. That way we will
825 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
826 general registers. Some kernels support these, but not the newer
827 PPC_PTRACE_GETREGS. */
828 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
829 NULL
, ppc_store_tm_ctarregset
},
830 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
831 NULL
, ppc_store_tm_cdscrregset
},
832 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
833 NULL
, ppc_store_tm_cpprregset
},
834 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
835 NULL
, ppc_store_tm_cvsxregset
},
836 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
837 NULL
, ppc_store_tm_cvrregset
},
838 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
839 NULL
, ppc_store_tm_cfprregset
},
840 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
841 NULL
, ppc_store_tm_cgprregset
},
842 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
843 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
844 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
845 NULL
, ppc_store_ebbregset
},
846 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
847 ppc_fill_pmuregset
, ppc_store_pmuregset
},
848 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
849 ppc_fill_tarregset
, ppc_store_tarregset
},
850 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
851 ppc_fill_pprregset
, ppc_store_pprregset
},
852 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
853 ppc_fill_dscrregset
, ppc_store_dscrregset
},
854 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
855 ppc_fill_vsxregset
, ppc_store_vsxregset
},
856 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
857 ppc_fill_vrregset
, ppc_store_vrregset
},
858 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
859 ppc_fill_evrregset
, ppc_store_evrregset
},
860 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
864 static struct usrregs_info ppc_usrregs_info
=
870 static struct regsets_info ppc_regsets_info
=
872 ppc_regsets
, /* regsets */
874 NULL
, /* disabled_regsets */
877 static struct regs_info regs_info
=
879 NULL
, /* regset_bitmap */
884 static const struct regs_info
*
891 ppc_arch_setup (void)
893 const struct target_desc
*tdesc
;
894 struct regset_info
*regset
;
895 struct ppc_linux_features features
= ppc_linux_no_features
;
897 int tid
= lwpid_of (current_thread
);
899 features
.wordsize
= ppc_linux_target_wordsize (tid
);
901 if (features
.wordsize
== 4)
902 tdesc
= tdesc_powerpc_32l
;
904 tdesc
= tdesc_powerpc_64l
;
906 current_process ()->tdesc
= tdesc
;
908 /* The value of current_process ()->tdesc needs to be set for this
910 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
911 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
913 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
915 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
918 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
919 features
.altivec
= true;
921 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
922 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
923 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
925 features
.ppr_dscr
= true;
926 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
927 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
928 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
929 && ppc_check_regset (tid
, NT_PPC_TAR
,
930 PPC_LINUX_SIZEOF_TARREGSET
)
931 && ppc_check_regset (tid
, NT_PPC_EBB
,
932 PPC_LINUX_SIZEOF_EBBREGSET
)
933 && ppc_check_regset (tid
, NT_PPC_PMU
,
934 PPC_LINUX_SIZEOF_PMUREGSET
))
936 features
.isa207
= true;
937 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
938 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
939 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
944 if (ppc_hwcap
& PPC_FEATURE_CELL
)
945 features
.cell
= true;
947 tdesc
= ppc_linux_match_description (features
);
949 /* On 32-bit machines, check for SPE registers.
950 Set the low target's regmap field as appropriately. */
951 #ifndef __powerpc64__
952 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
953 tdesc
= tdesc_powerpc_e500l
;
955 if (!ppc_regmap_adjusted
)
957 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
958 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
960 /* If the FPSCR is 64-bit wide, we need to fetch the whole
961 64-bit slot and not just its second word. The PT_FPSCR
962 supplied in a 32-bit GDB compilation doesn't reflect
964 if (register_size (tdesc
, 70) == 8)
965 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
967 ppc_regmap_adjusted
= 1;
971 current_process ()->tdesc
= tdesc
;
973 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
974 switch (regset
->get_request
)
976 case PTRACE_GETVRREGS
:
977 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
979 case PTRACE_GETVSXREGS
:
980 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
982 case PTRACE_GETEVRREGS
:
983 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
984 regset
->size
= 32 * 4 + 8 + 4;
988 case PTRACE_GETREGSET
:
989 switch (regset
->nt_type
)
992 regset
->size
= (features
.ppr_dscr
?
993 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
996 regset
->size
= (features
.ppr_dscr
?
997 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
1000 regset
->size
= (features
.isa207
?
1001 PPC_LINUX_SIZEOF_TARREGSET
: 0);
1004 regset
->size
= (features
.isa207
?
1005 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
1008 regset
->size
= (features
.isa207
?
1009 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
1012 regset
->size
= (features
.htm
?
1013 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
1015 case NT_PPC_TM_CGPR
:
1016 if (features
.wordsize
== 4)
1017 regset
->size
= (features
.htm
?
1018 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
1020 regset
->size
= (features
.htm
?
1021 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
1023 case NT_PPC_TM_CFPR
:
1024 regset
->size
= (features
.htm
?
1025 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
1027 case NT_PPC_TM_CVMX
:
1028 regset
->size
= (features
.htm
?
1029 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
1031 case NT_PPC_TM_CVSX
:
1032 regset
->size
= (features
.htm
?
1033 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
1035 case NT_PPC_TM_CPPR
:
1036 regset
->size
= (features
.htm
?
1037 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
1039 case NT_PPC_TM_CDSCR
:
1040 regset
->size
= (features
.htm
?
1041 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1043 case NT_PPC_TM_CTAR
:
1044 regset
->size
= (features
.htm
?
1045 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1056 /* Implementation of linux_target_ops method "supports_tracepoints". */
1059 ppc_supports_tracepoints (void)
1064 /* Get the thread area address. This is used to recognize which
1065 thread is which when tracing with the in-process agent library. We
1066 don't read anything from the address, and treat it as opaque; it's
1067 the address itself that we assume is unique per-thread. */
1070 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1072 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1073 struct thread_info
*thr
= get_lwp_thread (lwp
);
1074 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1077 #ifdef __powerpc64__
1078 if (register_size (regcache
->tdesc
, 0) == 8)
1079 collect_register_by_name (regcache
, "r13", &tp
);
1082 collect_register_by_name (regcache
, "r2", &tp
);
1089 #ifdef __powerpc64__
1091 /* Older glibc doesn't provide this. */
1093 #ifndef EF_PPC64_ABI
1094 #define EF_PPC64_ABI 3
1097 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1101 is_elfv2_inferior (void)
1103 /* To be used as fallback if we're unable to determine the right result -
1104 assume inferior uses the same ABI as gdbserver. */
1106 const int def_res
= 1;
1108 const int def_res
= 0;
1113 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
1116 /* Assume ELF header is at the beginning of the page where program headers
1117 are located. If it doesn't look like one, bail. */
1119 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1120 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1123 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1128 /* Generate a ds-form instruction in BUF and return the number of bytes written
1131 | OPCD | RST | RA | DS |XO| */
1133 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1135 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1139 gdb_assert ((opcd
& ~0x3f) == 0);
1140 gdb_assert ((rst
& ~0x1f) == 0);
1141 gdb_assert ((ra
& ~0x1f) == 0);
1142 gdb_assert ((xo
& ~0x3) == 0);
1144 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1145 *buf
= (opcd
<< 26) | insn
;
1149 /* Followings are frequently used ds-form instructions. */
1151 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1152 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1153 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1154 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1156 /* Generate a d-form instruction in BUF.
1159 | OPCD | RST | RA | D | */
1162 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1166 gdb_assert ((opcd
& ~0x3f) == 0);
1167 gdb_assert ((rst
& ~0x1f) == 0);
1168 gdb_assert ((ra
& ~0x1f) == 0);
1170 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1171 *buf
= (opcd
<< 26) | insn
;
1175 /* Followings are frequently used d-form instructions. */
1177 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1178 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1179 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1180 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1181 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1182 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1183 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1184 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1185 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1187 /* Generate a xfx-form instruction in BUF and return the number of bytes
1191 | OPCD | RST | RI | XO |/| */
1194 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1197 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1199 gdb_assert ((opcd
& ~0x3f) == 0);
1200 gdb_assert ((rst
& ~0x1f) == 0);
1201 gdb_assert ((xo
& ~0x3ff) == 0);
1203 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1204 *buf
= (opcd
<< 26) | insn
;
1208 /* Followings are frequently used xfx-form instructions. */
1210 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1211 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1212 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1213 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1214 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1216 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1219 /* Generate a x-form instruction in BUF and return the number of bytes written.
1222 | OPCD | RST | RA | RB | XO |RC| */
1225 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1229 gdb_assert ((opcd
& ~0x3f) == 0);
1230 gdb_assert ((rst
& ~0x1f) == 0);
1231 gdb_assert ((ra
& ~0x1f) == 0);
1232 gdb_assert ((rb
& ~0x1f) == 0);
1233 gdb_assert ((xo
& ~0x3ff) == 0);
1234 gdb_assert ((rc
& ~1) == 0);
1236 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1237 *buf
= (opcd
<< 26) | insn
;
1241 /* Followings are frequently used x-form instructions. */
1243 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1244 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1245 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1246 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1247 /* Assume bf = cr7. */
1248 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1251 /* Generate a md-form instruction in BUF and return the number of bytes written.
1253 0 6 11 16 21 27 30 31 32
1254 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1257 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1261 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1262 unsigned int sh0_4
= sh
& 0x1f;
1263 unsigned int sh5
= (sh
>> 5) & 1;
1265 gdb_assert ((opcd
& ~0x3f) == 0);
1266 gdb_assert ((rs
& ~0x1f) == 0);
1267 gdb_assert ((ra
& ~0x1f) == 0);
1268 gdb_assert ((sh
& ~0x3f) == 0);
1269 gdb_assert ((mb
& ~0x3f) == 0);
1270 gdb_assert ((xo
& ~0x7) == 0);
1271 gdb_assert ((rc
& ~0x1) == 0);
1273 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1274 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1275 *buf
= (opcd
<< 26) | insn
;
1279 /* The following are frequently used md-form instructions. */
1281 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1282 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1283 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1284 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1286 /* Generate a i-form instruction in BUF and return the number of bytes written.
1289 | OPCD | LI |AA|LK| */
1292 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1296 gdb_assert ((opcd
& ~0x3f) == 0);
1298 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1299 *buf
= (opcd
<< 26) | insn
;
1303 /* The following are frequently used i-form instructions. */
1305 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1306 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1308 /* Generate a b-form instruction in BUF and return the number of bytes written.
1311 | OPCD | BO | BI | BD |AA|LK| */
1314 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1319 gdb_assert ((opcd
& ~0x3f) == 0);
1320 gdb_assert ((bo
& ~0x1f) == 0);
1321 gdb_assert ((bi
& ~0x1f) == 0);
1323 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1324 *buf
= (opcd
<< 26) | insn
;
1328 /* The following are frequently used b-form instructions. */
1329 /* Assume bi = cr7. */
1330 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1332 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1333 respectively. They are primary used for save/restore GPRs in jump-pad,
1334 not used for bytecode compiling. */
1336 #ifdef __powerpc64__
1337 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1338 GEN_LD (buf, rt, ra, si) : \
1339 GEN_LWZ (buf, rt, ra, si))
1340 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1341 GEN_STD (buf, rt, ra, si) : \
1342 GEN_STW (buf, rt, ra, si))
1344 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1345 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1348 /* Generate a sequence of instructions to load IMM in the register REG.
1349 Write the instructions in BUF and return the number of bytes written. */
1352 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1356 if ((imm
+ 32768) < 65536)
1358 /* li reg, imm[15:0] */
1359 p
+= GEN_LI (p
, reg
, imm
);
1361 else if ((imm
>> 32) == 0)
1363 /* lis reg, imm[31:16]
1364 ori reg, reg, imm[15:0]
1365 rldicl reg, reg, 0, 32 */
1366 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1367 if ((imm
& 0xffff) != 0)
1368 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1369 /* Clear upper 32-bit if sign-bit is set. */
1370 if (imm
& (1u << 31) && is_64
)
1371 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1376 /* lis reg, <imm[63:48]>
1377 ori reg, reg, <imm[48:32]>
1378 rldicr reg, reg, 32, 31
1379 oris reg, reg, <imm[31:16]>
1380 ori reg, reg, <imm[15:0]> */
1381 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1382 if (((imm
>> 32) & 0xffff) != 0)
1383 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1384 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1385 if (((imm
>> 16) & 0xffff) != 0)
1386 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1387 if ((imm
& 0xffff) != 0)
1388 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1394 /* Generate a sequence for atomically exchange at location LOCK.
1395 This code sequence clobbers r6, r7, r8. LOCK is the location for
1396 the atomic-xchg, OLD_VALUE is expected old value stored in the
1397 location, and R_NEW is a register for the new value. */
1400 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1403 const int r_lock
= 6;
1404 const int r_old
= 7;
1405 const int r_tmp
= 8;
1409 1: lwarx TMP, 0, LOCK
1415 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1416 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1418 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1419 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1420 p
+= GEN_BNE (p
, -8);
1421 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1422 p
+= GEN_BNE (p
, -16);
1427 /* Generate a sequence of instructions for calling a function
1428 at address of FN. Return the number of bytes are written in BUF. */
1431 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1435 /* Must be called by r12 for caller to calculate TOC address. */
1436 p
+= gen_limm (p
, 12, fn
, is_64
);
1439 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1440 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1441 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1443 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1444 *p
++ = 0x4e800421; /* bctrl */
1449 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1450 of instruction. This function is used to adjust pc-relative instructions
1454 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1459 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1460 op6
= PPC_OP6 (insn
);
1462 if (op6
== 18 && (insn
& 2) == 0)
1464 /* branch && AA = 0 */
1465 rel
= PPC_LI (insn
);
1466 newrel
= (oldloc
- *to
) + rel
;
1468 /* Out of range. Cannot relocate instruction. */
1469 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1472 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1474 else if (op6
== 16 && (insn
& 2) == 0)
1476 /* conditional branch && AA = 0 */
1478 /* If the new relocation is too big for even a 26-bit unconditional
1479 branch, there is nothing we can do. Just abort.
1481 Otherwise, if it can be fit in 16-bit conditional branch, just
1482 copy the instruction and relocate the address.
1484 If the it's big for conditional-branch (16-bit), try to invert the
1485 condition and jump with 26-bit branch. For example,
1496 After this transform, we are actually jump from *TO+4 instead of *TO,
1497 so check the relocation again because it will be 1-insn farther then
1498 before if *TO is after OLDLOC.
1501 For BDNZT (or so) is transformed from
1513 See also "BO field encodings". */
1515 rel
= PPC_BD (insn
);
1516 newrel
= (oldloc
- *to
) + rel
;
1518 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1519 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1520 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1524 /* Out of range. Cannot relocate instruction. */
1525 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1528 if ((PPC_BO (insn
) & 0x14) == 0x4)
1530 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1533 /* Jump over the unconditional branch. */
1534 insn
= (insn
& ~0xfffc) | 0x8;
1535 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1538 /* Build a unconditional branch and copy LK bit. */
1539 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1540 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1545 else if ((PPC_BO (insn
) & 0x14) == 0)
1547 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1548 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1552 /* Out of range. Cannot relocate instruction. */
1553 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1556 /* Copy BI field. */
1557 bf_insn
|= (insn
& 0x1f0000);
1559 /* Invert condition. */
1560 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1561 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1563 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1565 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1568 /* Build a unconditional branch and copy LK bit. */
1569 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1570 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1575 else /* (BO & 0x14) == 0x14, branch always. */
1577 /* Out of range. Cannot relocate instruction. */
1578 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1581 /* Build a unconditional branch and copy LK bit. */
1582 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1583 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1590 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1594 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1595 See target.h for details. */
1598 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1599 CORE_ADDR collector
,
1602 CORE_ADDR
*jump_entry
,
1603 CORE_ADDR
*trampoline
,
1604 ULONGEST
*trampoline_size
,
1605 unsigned char *jjump_pad_insn
,
1606 ULONGEST
*jjump_pad_insn_size
,
1607 CORE_ADDR
*adjusted_insn_addr
,
1608 CORE_ADDR
*adjusted_insn_addr_end
,
1614 CORE_ADDR buildaddr
= *jump_entry
;
1615 const CORE_ADDR entryaddr
= *jump_entry
;
1616 int rsz
, min_frame
, frame_size
, tp_reg
;
1617 #ifdef __powerpc64__
1618 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1619 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1620 int is_opd
= is_64
&& !is_elfv2_inferior ();
1622 int is_64
= 0, is_opd
= 0;
1625 #ifdef __powerpc64__
1628 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1631 frame_size
= (40 * rsz
) + min_frame
;
1639 frame_size
= (40 * rsz
) + min_frame
;
1641 #ifdef __powerpc64__
1645 /* Stack frame layout for this jump pad,
1647 High thread_area (r13/r2) |
1648 tpoint - collecting_t obj
1658 R0 - collected registers
1664 The code flow of this jump pad,
1669 4. Call gdb_collector
1670 5. Restore GPR and SPR
1672 7. Build a jump for back to the program
1673 8. Copy/relocate original instruction
1674 9. Build a jump for replacing orignal instruction. */
1676 /* Adjust stack pointer. */
1678 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1680 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1682 /* Store GPRs. Save R1 later, because it had just been modified, but
1683 we want the original value. */
1684 for (j
= 2; j
< 32; j
++)
1685 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1686 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1687 /* Set r0 to the original value of r1 before adjusting stack frame,
1688 and then save it. */
1689 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1690 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1692 /* Save CR, XER, LR, and CTR. */
1693 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1694 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1695 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1696 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1697 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1698 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1699 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1700 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1702 /* Save PC<tpaddr> */
1703 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1704 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1707 /* Setup arguments to collector. */
1708 /* Set r4 to collected registers. */
1709 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1710 /* Set r3 to TPOINT. */
1711 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1713 /* Prepare collecting_t object for lock. */
1714 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1715 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1716 /* Set R5 to collecting object. */
1717 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1719 p
+= GEN_LWSYNC (p
);
1720 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1721 p
+= GEN_LWSYNC (p
);
1723 /* Call to collector. */
1724 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1726 /* Simply write 0 to release the lock. */
1727 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1728 p
+= gen_limm (p
, 4, 0, is_64
);
1729 p
+= GEN_LWSYNC (p
);
1730 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1732 /* Restore stack and registers. */
1733 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1734 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1735 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1736 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1737 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1738 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1739 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1740 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1743 for (j
= 2; j
< 32; j
++)
1744 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1745 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1747 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1749 /* Flush instructions to inferior memory. */
1750 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1752 /* Now, insert the original instruction to execute in the jump pad. */
1753 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1754 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1755 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1757 /* Verify the relocation size. If should be 4 for normal copy,
1758 8 or 12 for some conditional branch. */
1759 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1760 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1762 sprintf (err
, "E.Unexpected instruction length = %d"
1763 "when relocate instruction.",
1764 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1768 buildaddr
= *adjusted_insn_addr_end
;
1770 /* Finally, write a jump back to the program. */
1771 offset
= (tpaddr
+ 4) - buildaddr
;
1772 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1774 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1775 "(offset 0x%x > 26-bit).", offset
);
1779 p
+= GEN_B (p
, offset
);
1780 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1781 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1783 /* The jump pad is now built. Wire in a jump to our jump pad. This
1784 is always done last (by our caller actually), so that we can
1785 install fast tracepoints with threads running. This relies on
1786 the agent's atomic write support. */
1787 offset
= entryaddr
- tpaddr
;
1788 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1790 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1791 "(offset 0x%x > 26-bit).", offset
);
1795 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1796 *jjump_pad_insn_size
= 4;
1801 /* Returns the minimum instruction length for installing a tracepoint. */
1804 ppc_get_min_fast_tracepoint_insn_len (void)
1809 /* Emits a given buffer into the target at current_insn_ptr. Length
1810 is in units of 32-bit words. */
1813 emit_insns (uint32_t *buf
, int n
)
1815 n
= n
* sizeof (uint32_t);
1816 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1817 current_insn_ptr
+= n
;
1820 #define __EMIT_ASM(NAME, INSNS) \
1823 extern uint32_t start_bcax_ ## NAME []; \
1824 extern uint32_t end_bcax_ ## NAME []; \
1825 emit_insns (start_bcax_ ## NAME, \
1826 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1827 __asm__ (".section .text.__ppcbcax\n\t" \
1828 "start_bcax_" #NAME ":\n\t" \
1830 "end_bcax_" #NAME ":\n\t" \
1834 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1835 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1839 Bytecode execution stack frame - 32-bit
1841 | LR save area (SP + 4)
1842 SP' -> +- Back chain (SP + 0)
1843 | Save r31 for access saved arguments
1844 | Save r30 for bytecode stack pointer
1845 | Save r4 for incoming argument *value
1846 | Save r3 for incoming argument regs
1847 r30 -> +- Bytecode execution stack
1849 | 64-byte (8 doublewords) at initial.
1850 | Expand stack as needed.
1853 | Some padding for minimum stack frame and 16-byte alignment.
1855 SP +- Back-chain (SP')
1861 r30 is the stack-pointer for bytecode machine.
1862 It should point to next-empty, so we can use LDU for pop.
1863 r3 is used for cache of the high part of TOP value.
1864 It was the first argument, pointer to regs.
1865 r4 is used for cache of the low part of TOP value.
1866 It was the second argument, pointer to the result.
1867 We should set *result = TOP after leaving this function.
1870 * To restore stack at epilogue
1872 * To check stack is big enough for bytecode execution.
1874 * To return execution result.
1879 /* Regardless of endian, register 3 is always high part, 4 is low part.
1880 These defines are used when the register pair is stored/loaded.
1881 Likewise, to simplify code, have a similiar define for 5:6. */
1883 #if __BYTE_ORDER == __LITTLE_ENDIAN
1884 #define TOP_FIRST "4"
1885 #define TOP_SECOND "3"
1886 #define TMP_FIRST "6"
1887 #define TMP_SECOND "5"
1889 #define TOP_FIRST "3"
1890 #define TOP_SECOND "4"
1891 #define TMP_FIRST "5"
1892 #define TMP_SECOND "6"
1895 /* Emit prologue in inferior memory. See above comments. */
1898 ppc_emit_prologue (void)
1900 EMIT_ASM (/* Save return address. */
1903 /* Adjust SP. 96 is the initial frame size. */
1905 /* Save r30 and incoming arguments. */
1906 "stw 31, 96-4(1) \n"
1907 "stw 30, 96-8(1) \n"
1908 "stw 4, 96-12(1) \n"
1909 "stw 3, 96-16(1) \n"
1910 /* Point r31 to original r1 for access arguments. */
1912 /* Set r30 to pointing stack-top. */
1914 /* Initial r3/TOP to 0. */
1919 /* Emit epilogue in inferior memory. See above comments. */
1922 ppc_emit_epilogue (void)
1924 EMIT_ASM (/* *result = TOP */
1926 "stw " TOP_FIRST
", 0(5) \n"
1927 "stw " TOP_SECOND
", 4(5) \n"
1928 /* Restore registers. */
1935 /* Return 0 for no-error. */
1941 /* TOP = stack[--sp] + TOP */
1946 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1947 "lwz " TMP_SECOND
", 4(30)\n"
1952 /* TOP = stack[--sp] - TOP */
1957 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1958 "lwz " TMP_SECOND
", 4(30) \n"
1960 "subfe 3, 3, 5 \n");
1963 /* TOP = stack[--sp] * TOP */
1968 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1969 "lwz " TMP_SECOND
", 4(30) \n"
1978 /* TOP = stack[--sp] << TOP */
1983 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1984 "lwz " TMP_SECOND
", 4(30) \n"
1985 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1986 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1987 "slw 5, 5, 4\n" /* Shift high part left */
1988 "slw 4, 6, 4\n" /* Shift low part left */
1989 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1990 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1992 "or 3, 7, 3\n"); /* Assemble high part */
1995 /* Top = stack[--sp] >> TOP
1996 (Arithmetic shift right) */
1999 ppc_emit_rsh_signed (void)
2001 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2002 "lwz " TMP_SECOND
", 4(30) \n"
2003 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2004 "sraw 3, 5, 4\n" /* Shift high part right */
2006 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
2007 "sraw 4, 5, 7\n" /* Shift high to low */
2010 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2011 "srw 4, 6, 4\n" /* Shift low part right */
2012 "slw 5, 5, 7\n" /* Shift high to low */
2013 "or 4, 4, 5\n" /* Assemble low part */
2017 /* Top = stack[--sp] >> TOP
2018 (Logical shift right) */
2021 ppc_emit_rsh_unsigned (void)
2023 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2024 "lwz " TMP_SECOND
", 4(30) \n"
2025 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2026 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2027 "srw 6, 6, 4\n" /* Shift low part right */
2028 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2029 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2031 "srw 3, 5, 4\n" /* Shift high part right */
2032 "or 4, 6, 7\n"); /* Assemble low part */
2035 /* Emit code for signed-extension specified by ARG. */
2038 ppc_emit_ext (int arg
)
2043 EMIT_ASM ("extsb 4, 4\n"
2047 EMIT_ASM ("extsh 4, 4\n"
2051 EMIT_ASM ("srawi 3, 4, 31");
2058 /* Emit code for zero-extension specified by ARG. */
2061 ppc_emit_zero_ext (int arg
)
2066 EMIT_ASM ("clrlwi 4,4,24\n"
2070 EMIT_ASM ("clrlwi 4,4,16\n"
2074 EMIT_ASM ("li 3, 0");
2082 i.e., TOP = (TOP == 0) ? 1 : 0; */
2085 ppc_emit_log_not (void)
2087 EMIT_ASM ("or 4, 3, 4 \n"
2093 /* TOP = stack[--sp] & TOP */
2096 ppc_emit_bit_and (void)
2098 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2099 "lwz " TMP_SECOND
", 4(30) \n"
2104 /* TOP = stack[--sp] | TOP */
2107 ppc_emit_bit_or (void)
2109 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2110 "lwz " TMP_SECOND
", 4(30) \n"
2115 /* TOP = stack[--sp] ^ TOP */
2118 ppc_emit_bit_xor (void)
2120 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2121 "lwz " TMP_SECOND
", 4(30) \n"
2127 i.e., TOP = ~(TOP | TOP) */
2130 ppc_emit_bit_not (void)
2132 EMIT_ASM ("nor 3, 3, 3 \n"
2136 /* TOP = stack[--sp] == TOP */
2139 ppc_emit_equal (void)
2141 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2142 "lwz " TMP_SECOND
", 4(30) \n"
2151 /* TOP = stack[--sp] < TOP
2152 (Signed comparison) */
2155 ppc_emit_less_signed (void)
2157 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2158 "lwz " TMP_SECOND
", 4(30) \n"
2161 /* CR6 bit 0 = low less and high equal */
2162 "crand 6*4+0, 6*4+0, 7*4+2\n"
2163 /* CR7 bit 0 = (low less and high equal) or high less */
2164 "cror 7*4+0, 7*4+0, 6*4+0\n"
2166 "rlwinm 4, 4, 29, 31, 31 \n"
2170 /* TOP = stack[--sp] < TOP
2171 (Unsigned comparison) */
2174 ppc_emit_less_unsigned (void)
2176 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2177 "lwz " TMP_SECOND
", 4(30) \n"
2180 /* CR6 bit 0 = low less and high equal */
2181 "crand 6*4+0, 6*4+0, 7*4+2\n"
2182 /* CR7 bit 0 = (low less and high equal) or high less */
2183 "cror 7*4+0, 7*4+0, 6*4+0\n"
2185 "rlwinm 4, 4, 29, 31, 31 \n"
2189 /* Access the memory address in TOP in size of SIZE.
2190 Zero-extend the read value. */
2193 ppc_emit_ref (int size
)
2198 EMIT_ASM ("lbz 4, 0(4)\n"
2202 EMIT_ASM ("lhz 4, 0(4)\n"
2206 EMIT_ASM ("lwz 4, 0(4)\n"
2210 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2211 EMIT_ASM ("lwz 3, 4(4)\n"
2214 EMIT_ASM ("lwz 3, 0(4)\n"
2223 ppc_emit_const (LONGEST num
)
2228 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2229 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2231 emit_insns (buf
, p
- buf
);
2232 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2235 /* Set TOP to the value of register REG by calling get_raw_reg function
2236 with two argument, collected buffer and register number. */
2239 ppc_emit_reg (int reg
)
2244 /* fctx->regs is passed in r3 and then saved in -16(31). */
2245 p
+= GEN_LWZ (p
, 3, 31, -16);
2246 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2247 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2249 emit_insns (buf
, p
- buf
);
2250 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2252 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2254 EMIT_ASM ("mr 5, 4\n"
2260 /* TOP = stack[--sp] */
2265 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2266 "lwz " TOP_SECOND
", 4(30) \n");
2269 /* stack[sp++] = TOP
2271 Because we may use up bytecode stack, expand 8 doublewords more
2275 ppc_emit_stack_flush (void)
2277 /* Make sure bytecode stack is big enough before push.
2278 Otherwise, expand 64-byte more. */
2280 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2281 " stw " TOP_SECOND
", 4(30)\n"
2282 " addi 5, 30, -(8 + 8) \n"
2285 " stwu 31, -64(1) \n"
2286 "1:addi 30, 30, -8 \n");
2289 /* Swap TOP and stack[sp-1] */
2292 ppc_emit_swap (void)
2294 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2295 "lwz " TMP_SECOND
", 12(30) \n"
2296 "stw " TOP_FIRST
", 8(30) \n"
2297 "stw " TOP_SECOND
", 12(30) \n"
2302 /* Discard N elements in the stack. Also used for ppc64. */
2305 ppc_emit_stack_adjust (int n
)
2317 p
+= GEN_ADDI (p
, 30, 30, n
);
2319 emit_insns (buf
, p
- buf
);
2320 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2323 /* Call function FN. */
2326 ppc_emit_call (CORE_ADDR fn
)
2331 p
+= gen_call (p
, fn
, 0, 0);
2333 emit_insns (buf
, p
- buf
);
2334 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2337 /* FN's prototype is `LONGEST(*fn)(int)'.
2342 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2347 /* Setup argument. arg1 is a 16-bit value. */
2348 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2349 p
+= gen_call (p
, fn
, 0, 0);
2351 emit_insns (buf
, p
- buf
);
2352 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2354 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2356 EMIT_ASM ("mr 5, 4\n"
2362 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2365 TOP should be preserved/restored before/after the call. */
2368 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2373 /* Save TOP. 0(30) is next-empty. */
2374 p
+= GEN_STW (p
, 3, 30, 0);
2375 p
+= GEN_STW (p
, 4, 30, 4);
2377 /* Setup argument. arg1 is a 16-bit value. */
2378 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2380 p
+= GEN_MR (p
, 5, 4);
2381 p
+= GEN_MR (p
, 6, 3);
2385 p
+= GEN_MR (p
, 5, 3);
2386 p
+= GEN_MR (p
, 6, 4);
2388 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2389 p
+= gen_call (p
, fn
, 0, 0);
2392 p
+= GEN_LWZ (p
, 3, 30, 0);
2393 p
+= GEN_LWZ (p
, 4, 30, 4);
2395 emit_insns (buf
, p
- buf
);
2396 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2399 /* Note in the following goto ops:
2401 When emitting goto, the target address is later relocated by
2402 write_goto_address. OFFSET_P is the offset of the branch instruction
2403 in the code sequence, and SIZE_P is how to relocate the instruction,
2404 recognized by ppc_write_goto_address. In current implementation,
2405 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2408 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2411 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2413 EMIT_ASM ("or. 3, 3, 4 \n"
2414 "lwzu " TOP_FIRST
", 8(30) \n"
2415 "lwz " TOP_SECOND
", 4(30) \n"
2424 /* Unconditional goto. Also used for ppc64. */
2427 ppc_emit_goto (int *offset_p
, int *size_p
)
2429 EMIT_ASM ("1:b 1b");
2437 /* Goto if stack[--sp] == TOP */
2440 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2442 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2443 "lwz " TMP_SECOND
", 4(30) \n"
2447 "lwzu " TOP_FIRST
", 8(30) \n"
2448 "lwz " TOP_SECOND
", 4(30) \n"
2457 /* Goto if stack[--sp] != TOP */
2460 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2462 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2463 "lwz " TMP_SECOND
", 4(30) \n"
2467 "lwzu " TOP_FIRST
", 8(30) \n"
2468 "lwz " TOP_SECOND
", 4(30) \n"
2477 /* Goto if stack[--sp] < TOP */
2480 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2482 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2483 "lwz " TMP_SECOND
", 4(30) \n"
2486 /* CR6 bit 0 = low less and high equal */
2487 "crand 6*4+0, 6*4+0, 7*4+2\n"
2488 /* CR7 bit 0 = (low less and high equal) or high less */
2489 "cror 7*4+0, 7*4+0, 6*4+0\n"
2490 "lwzu " TOP_FIRST
", 8(30) \n"
2491 "lwz " TOP_SECOND
", 4(30)\n"
2500 /* Goto if stack[--sp] <= TOP */
2503 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2505 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2506 "lwz " TMP_SECOND
", 4(30) \n"
2509 /* CR6 bit 0 = low less/equal and high equal */
2510 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2511 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2512 "cror 7*4+0, 7*4+0, 6*4+0\n"
2513 "lwzu " TOP_FIRST
", 8(30) \n"
2514 "lwz " TOP_SECOND
", 4(30)\n"
2523 /* Goto if stack[--sp] > TOP */
2526 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2528 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2529 "lwz " TMP_SECOND
", 4(30) \n"
2532 /* CR6 bit 0 = low greater and high equal */
2533 "crand 6*4+0, 6*4+1, 7*4+2\n"
2534 /* CR7 bit 0 = (low greater and high equal) or high greater */
2535 "cror 7*4+0, 7*4+1, 6*4+0\n"
2536 "lwzu " TOP_FIRST
", 8(30) \n"
2537 "lwz " TOP_SECOND
", 4(30)\n"
2546 /* Goto if stack[--sp] >= TOP */
2549 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2551 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2552 "lwz " TMP_SECOND
", 4(30) \n"
2555 /* CR6 bit 0 = low ge and high equal */
2556 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2557 /* CR7 bit 0 = (low ge and high equal) or high greater */
2558 "cror 7*4+0, 7*4+1, 6*4+0\n"
2559 "lwzu " TOP_FIRST
", 8(30)\n"
2560 "lwz " TOP_SECOND
", 4(30)\n"
2569 /* Relocate previous emitted branch instruction. FROM is the address
2570 of the branch instruction, TO is the goto target address, and SIZE
2571 if the value we set by *SIZE_P before. Currently, it is either
2572 24 or 14 of branch and conditional-branch instruction.
2573 Also used for ppc64. */
2576 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2578 long rel
= to
- from
;
2582 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2583 opcd
= (insn
>> 26) & 0x3f;
2589 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2591 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2595 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2597 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2604 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2607 /* Table of emit ops for 32-bit. */
2609 static struct emit_ops ppc_emit_ops_impl
=
2617 ppc_emit_rsh_signed
,
2618 ppc_emit_rsh_unsigned
,
2626 ppc_emit_less_signed
,
2627 ppc_emit_less_unsigned
,
2631 ppc_write_goto_address
,
2636 ppc_emit_stack_flush
,
2639 ppc_emit_stack_adjust
,
2640 ppc_emit_int_call_1
,
2641 ppc_emit_void_call_2
,
2650 #ifdef __powerpc64__
2654 Bytecode execution stack frame - 64-bit
2656 | LR save area (SP + 16)
2657 | CR save area (SP + 8)
2658 SP' -> +- Back chain (SP + 0)
2659 | Save r31 for access saved arguments
2660 | Save r30 for bytecode stack pointer
2661 | Save r4 for incoming argument *value
2662 | Save r3 for incoming argument regs
2663 r30 -> +- Bytecode execution stack
2665 | 64-byte (8 doublewords) at initial.
2666 | Expand stack as needed.
2669 | Some padding for minimum stack frame.
2671 SP +- Back-chain (SP')
2674 = 112 + (4 * 8) + 64
2677 r30 is the stack-pointer for bytecode machine.
2678 It should point to next-empty, so we can use LDU for pop.
2679 r3 is used for cache of TOP value.
2680 It was the first argument, pointer to regs.
2681 r4 is the second argument, pointer to the result.
2682 We should set *result = TOP after leaving this function.
2685 * To restore stack at epilogue
2687 * To check stack is big enough for bytecode execution.
2688 => r30 - 8 > SP + 112
2689 * To return execution result.
2694 /* Emit prologue in inferior memory. See above comments. */
2697 ppc64v1_emit_prologue (void)
2699 /* On ELFv1, function pointers really point to function descriptor,
2700 so emit one here. We don't care about contents of words 1 and 2,
2701 so let them just overlap out code. */
2702 uint64_t opd
= current_insn_ptr
+ 8;
2705 /* Mind the strict aliasing rules. */
2706 memcpy (buf
, &opd
, sizeof buf
);
2708 EMIT_ASM (/* Save return address. */
2711 /* Save r30 and incoming arguments. */
2716 /* Point r31 to current r1 for access arguments. */
2718 /* Adjust SP. 208 is the initial frame size. */
2719 "stdu 1, -208(1) \n"
2720 /* Set r30 to pointing stack-top. */
2721 "addi 30, 1, 168 \n"
2722 /* Initial r3/TOP to 0. */
2726 /* Emit prologue in inferior memory. See above comments. */
2729 ppc64v2_emit_prologue (void)
2731 EMIT_ASM (/* Save return address. */
2734 /* Save r30 and incoming arguments. */
2739 /* Point r31 to current r1 for access arguments. */
2741 /* Adjust SP. 208 is the initial frame size. */
2742 "stdu 1, -208(1) \n"
2743 /* Set r30 to pointing stack-top. */
2744 "addi 30, 1, 168 \n"
2745 /* Initial r3/TOP to 0. */
2749 /* Emit epilogue in inferior memory. See above comments. */
2752 ppc64_emit_epilogue (void)
2754 EMIT_ASM (/* Restore SP. */
2759 /* Restore registers. */
2764 /* Return 0 for no-error. */
2770 /* TOP = stack[--sp] + TOP */
2773 ppc64_emit_add (void)
2775 EMIT_ASM ("ldu 4, 8(30) \n"
2779 /* TOP = stack[--sp] - TOP */
2782 ppc64_emit_sub (void)
2784 EMIT_ASM ("ldu 4, 8(30) \n"
2788 /* TOP = stack[--sp] * TOP */
2791 ppc64_emit_mul (void)
2793 EMIT_ASM ("ldu 4, 8(30) \n"
2794 "mulld 3, 4, 3 \n");
2797 /* TOP = stack[--sp] << TOP */
2800 ppc64_emit_lsh (void)
2802 EMIT_ASM ("ldu 4, 8(30) \n"
2806 /* Top = stack[--sp] >> TOP
2807 (Arithmetic shift right) */
2810 ppc64_emit_rsh_signed (void)
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2816 /* Top = stack[--sp] >> TOP
2817 (Logical shift right) */
2820 ppc64_emit_rsh_unsigned (void)
2822 EMIT_ASM ("ldu 4, 8(30) \n"
2826 /* Emit code for signed-extension specified by ARG. */
2829 ppc64_emit_ext (int arg
)
2834 EMIT_ASM ("extsb 3, 3");
2837 EMIT_ASM ("extsh 3, 3");
2840 EMIT_ASM ("extsw 3, 3");
2847 /* Emit code for zero-extension specified by ARG. */
2850 ppc64_emit_zero_ext (int arg
)
2855 EMIT_ASM ("rldicl 3,3,0,56");
2858 EMIT_ASM ("rldicl 3,3,0,48");
2861 EMIT_ASM ("rldicl 3,3,0,32");
2869 i.e., TOP = (TOP == 0) ? 1 : 0; */
2872 ppc64_emit_log_not (void)
2874 EMIT_ASM ("cntlzd 3, 3 \n"
2878 /* TOP = stack[--sp] & TOP */
2881 ppc64_emit_bit_and (void)
2883 EMIT_ASM ("ldu 4, 8(30) \n"
2887 /* TOP = stack[--sp] | TOP */
2890 ppc64_emit_bit_or (void)
2892 EMIT_ASM ("ldu 4, 8(30) \n"
2896 /* TOP = stack[--sp] ^ TOP */
2899 ppc64_emit_bit_xor (void)
2901 EMIT_ASM ("ldu 4, 8(30) \n"
2906 i.e., TOP = ~(TOP | TOP) */
2909 ppc64_emit_bit_not (void)
2911 EMIT_ASM ("nor 3, 3, 3 \n");
2914 /* TOP = stack[--sp] == TOP */
2917 ppc64_emit_equal (void)
2919 EMIT_ASM ("ldu 4, 8(30) \n"
2925 /* TOP = stack[--sp] < TOP
2926 (Signed comparison) */
2929 ppc64_emit_less_signed (void)
2931 EMIT_ASM ("ldu 4, 8(30) \n"
2934 "rlwinm 3, 3, 29, 31, 31 \n");
2937 /* TOP = stack[--sp] < TOP
2938 (Unsigned comparison) */
2941 ppc64_emit_less_unsigned (void)
2943 EMIT_ASM ("ldu 4, 8(30) \n"
2946 "rlwinm 3, 3, 29, 31, 31 \n");
2949 /* Access the memory address in TOP in size of SIZE.
2950 Zero-extend the read value. */
2953 ppc64_emit_ref (int size
)
2958 EMIT_ASM ("lbz 3, 0(3)");
2961 EMIT_ASM ("lhz 3, 0(3)");
2964 EMIT_ASM ("lwz 3, 0(3)");
2967 EMIT_ASM ("ld 3, 0(3)");
2975 ppc64_emit_const (LONGEST num
)
2980 p
+= gen_limm (p
, 3, num
, 1);
2982 emit_insns (buf
, p
- buf
);
2983 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2986 /* Set TOP to the value of register REG by calling get_raw_reg function
2987 with two argument, collected buffer and register number. */
2990 ppc64v1_emit_reg (int reg
)
2995 /* fctx->regs is passed in r3 and then saved in 176(1). */
2996 p
+= GEN_LD (p
, 3, 31, -32);
2997 p
+= GEN_LI (p
, 4, reg
);
2998 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2999 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
3000 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3002 emit_insns (buf
, p
- buf
);
3003 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3006 /* Likewise, for ELFv2. */
3009 ppc64v2_emit_reg (int reg
)
3014 /* fctx->regs is passed in r3 and then saved in 176(1). */
3015 p
+= GEN_LD (p
, 3, 31, -32);
3016 p
+= GEN_LI (p
, 4, reg
);
3017 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3018 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
3019 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3021 emit_insns (buf
, p
- buf
);
3022 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3025 /* TOP = stack[--sp] */
3028 ppc64_emit_pop (void)
3030 EMIT_ASM ("ldu 3, 8(30)");
3033 /* stack[sp++] = TOP
3035 Because we may use up bytecode stack, expand 8 doublewords more
3039 ppc64_emit_stack_flush (void)
3041 /* Make sure bytecode stack is big enough before push.
3042 Otherwise, expand 64-byte more. */
3044 EMIT_ASM (" std 3, 0(30) \n"
3045 " addi 4, 30, -(112 + 8) \n"
3048 " stdu 31, -64(1) \n"
3049 "1:addi 30, 30, -8 \n");
3052 /* Swap TOP and stack[sp-1] */
3055 ppc64_emit_swap (void)
3057 EMIT_ASM ("ld 4, 8(30) \n"
3062 /* Call function FN - ELFv1. */
3065 ppc64v1_emit_call (CORE_ADDR fn
)
3070 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3071 p
+= gen_call (p
, fn
, 1, 1);
3072 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3074 emit_insns (buf
, p
- buf
);
3075 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3078 /* Call function FN - ELFv2. */
3081 ppc64v2_emit_call (CORE_ADDR fn
)
3086 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3087 p
+= gen_call (p
, fn
, 1, 0);
3088 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3090 emit_insns (buf
, p
- buf
);
3091 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3094 /* FN's prototype is `LONGEST(*fn)(int)'.
3099 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3104 /* Setup argument. arg1 is a 16-bit value. */
3105 p
+= gen_limm (p
, 3, arg1
, 1);
3106 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3107 p
+= gen_call (p
, fn
, 1, 1);
3108 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3110 emit_insns (buf
, p
- buf
);
3111 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3114 /* Likewise for ELFv2. */
3117 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3122 /* Setup argument. arg1 is a 16-bit value. */
3123 p
+= gen_limm (p
, 3, arg1
, 1);
3124 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3125 p
+= gen_call (p
, fn
, 1, 0);
3126 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3128 emit_insns (buf
, p
- buf
);
3129 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3132 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3135 TOP should be preserved/restored before/after the call. */
3138 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3143 /* Save TOP. 0(30) is next-empty. */
3144 p
+= GEN_STD (p
, 3, 30, 0);
3146 /* Setup argument. arg1 is a 16-bit value. */
3147 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3148 p
+= gen_limm (p
, 3, arg1
, 1);
3149 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3150 p
+= gen_call (p
, fn
, 1, 1);
3151 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3154 p
+= GEN_LD (p
, 3, 30, 0);
3156 emit_insns (buf
, p
- buf
);
3157 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3160 /* Likewise for ELFv2. */
3163 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3168 /* Save TOP. 0(30) is next-empty. */
3169 p
+= GEN_STD (p
, 3, 30, 0);
3171 /* Setup argument. arg1 is a 16-bit value. */
3172 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3173 p
+= gen_limm (p
, 3, arg1
, 1);
3174 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3175 p
+= gen_call (p
, fn
, 1, 0);
3176 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3179 p
+= GEN_LD (p
, 3, 30, 0);
3181 emit_insns (buf
, p
- buf
);
3182 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3185 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3188 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3190 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3200 /* Goto if stack[--sp] == TOP */
3203 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3205 EMIT_ASM ("ldu 4, 8(30) \n"
3216 /* Goto if stack[--sp] != TOP */
3219 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3221 EMIT_ASM ("ldu 4, 8(30) \n"
3232 /* Goto if stack[--sp] < TOP */
3235 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3237 EMIT_ASM ("ldu 4, 8(30) \n"
3248 /* Goto if stack[--sp] <= TOP */
3251 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3253 EMIT_ASM ("ldu 4, 8(30) \n"
3264 /* Goto if stack[--sp] > TOP */
3267 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3269 EMIT_ASM ("ldu 4, 8(30) \n"
3280 /* Goto if stack[--sp] >= TOP */
3283 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3285 EMIT_ASM ("ldu 4, 8(30) \n"
3296 /* Table of emit ops for 64-bit ELFv1. */
3298 static struct emit_ops ppc64v1_emit_ops_impl
=
3300 ppc64v1_emit_prologue
,
3301 ppc64_emit_epilogue
,
3306 ppc64_emit_rsh_signed
,
3307 ppc64_emit_rsh_unsigned
,
3315 ppc64_emit_less_signed
,
3316 ppc64_emit_less_unsigned
,
3320 ppc_write_goto_address
,
3325 ppc64_emit_stack_flush
,
3326 ppc64_emit_zero_ext
,
3328 ppc_emit_stack_adjust
,
3329 ppc64v1_emit_int_call_1
,
3330 ppc64v1_emit_void_call_2
,
3339 /* Table of emit ops for 64-bit ELFv2. */
3341 static struct emit_ops ppc64v2_emit_ops_impl
=
3343 ppc64v2_emit_prologue
,
3344 ppc64_emit_epilogue
,
3349 ppc64_emit_rsh_signed
,
3350 ppc64_emit_rsh_unsigned
,
3358 ppc64_emit_less_signed
,
3359 ppc64_emit_less_unsigned
,
3363 ppc_write_goto_address
,
3368 ppc64_emit_stack_flush
,
3369 ppc64_emit_zero_ext
,
3371 ppc_emit_stack_adjust
,
3372 ppc64v2_emit_int_call_1
,
3373 ppc64v2_emit_void_call_2
,
3384 /* Implementation of linux_target_ops method "emit_ops". */
3386 static struct emit_ops
*
3389 #ifdef __powerpc64__
3390 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3392 if (register_size (regcache
->tdesc
, 0) == 8)
3394 if (is_elfv2_inferior ())
3395 return &ppc64v2_emit_ops_impl
;
3397 return &ppc64v1_emit_ops_impl
;
3400 return &ppc_emit_ops_impl
;
3403 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3406 ppc_get_ipa_tdesc_idx (void)
3408 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3409 const struct target_desc
*tdesc
= regcache
->tdesc
;
3411 #ifdef __powerpc64__
3412 if (tdesc
== tdesc_powerpc_64l
)
3413 return PPC_TDESC_BASE
;
3414 if (tdesc
== tdesc_powerpc_altivec64l
)
3415 return PPC_TDESC_ALTIVEC
;
3416 if (tdesc
== tdesc_powerpc_cell64l
)
3417 return PPC_TDESC_CELL
;
3418 if (tdesc
== tdesc_powerpc_vsx64l
)
3419 return PPC_TDESC_VSX
;
3420 if (tdesc
== tdesc_powerpc_isa205_64l
)
3421 return PPC_TDESC_ISA205
;
3422 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3423 return PPC_TDESC_ISA205_ALTIVEC
;
3424 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3425 return PPC_TDESC_ISA205_VSX
;
3426 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3427 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3428 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3429 return PPC_TDESC_ISA207_VSX
;
3430 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3431 return PPC_TDESC_ISA207_HTM_VSX
;
3434 if (tdesc
== tdesc_powerpc_32l
)
3435 return PPC_TDESC_BASE
;
3436 if (tdesc
== tdesc_powerpc_altivec32l
)
3437 return PPC_TDESC_ALTIVEC
;
3438 if (tdesc
== tdesc_powerpc_cell32l
)
3439 return PPC_TDESC_CELL
;
3440 if (tdesc
== tdesc_powerpc_vsx32l
)
3441 return PPC_TDESC_VSX
;
3442 if (tdesc
== tdesc_powerpc_isa205_32l
)
3443 return PPC_TDESC_ISA205
;
3444 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3445 return PPC_TDESC_ISA205_ALTIVEC
;
3446 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3447 return PPC_TDESC_ISA205_VSX
;
3448 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3449 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3450 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3451 return PPC_TDESC_ISA207_VSX
;
3452 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3453 return PPC_TDESC_ISA207_HTM_VSX
;
3454 if (tdesc
== tdesc_powerpc_e500l
)
3455 return PPC_TDESC_E500
;
3460 struct linux_target_ops the_low_target
= {
3463 ppc_cannot_fetch_register
,
3464 ppc_cannot_store_register
,
3465 NULL
, /* fetch_register */
3468 NULL
, /* breakpoint_kind_from_pc */
3469 ppc_sw_breakpoint_from_kind
,
3473 ppc_supports_z_point_type
,
3478 ppc_collect_ptrace_register
,
3479 ppc_supply_ptrace_register
,
3480 NULL
, /* siginfo_fixup */
3481 NULL
, /* new_process */
3482 NULL
, /* delete_process */
3483 NULL
, /* new_thread */
3484 NULL
, /* delete_thread */
3485 NULL
, /* new_fork */
3486 NULL
, /* prepare_to_resume */
3487 NULL
, /* process_qsupported */
3488 ppc_supports_tracepoints
,
3489 ppc_get_thread_area
,
3490 ppc_install_fast_tracepoint_jump_pad
,
3492 ppc_get_min_fast_tracepoint_insn_len
,
3493 NULL
, /* supports_range_stepping */
3494 NULL
, /* breakpoint_kind_from_current_state */
3495 ppc_supports_hardware_single_step
,
3496 NULL
, /* get_syscall_trapinfo */
3497 ppc_get_ipa_tdesc_idx
,
3501 initialize_low_arch (void)
3503 /* Initialize the Linux target descriptions. */
3505 init_registers_powerpc_32l ();
3506 init_registers_powerpc_altivec32l ();
3507 init_registers_powerpc_cell32l ();
3508 init_registers_powerpc_vsx32l ();
3509 init_registers_powerpc_isa205_32l ();
3510 init_registers_powerpc_isa205_altivec32l ();
3511 init_registers_powerpc_isa205_vsx32l ();
3512 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3513 init_registers_powerpc_isa207_vsx32l ();
3514 init_registers_powerpc_isa207_htm_vsx32l ();
3515 init_registers_powerpc_e500l ();
3517 init_registers_powerpc_64l ();
3518 init_registers_powerpc_altivec64l ();
3519 init_registers_powerpc_cell64l ();
3520 init_registers_powerpc_vsx64l ();
3521 init_registers_powerpc_isa205_64l ();
3522 init_registers_powerpc_isa205_altivec64l ();
3523 init_registers_powerpc_isa205_vsx64l ();
3524 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3525 init_registers_powerpc_isa207_vsx64l ();
3526 init_registers_powerpc_isa207_htm_vsx64l ();
3529 initialize_regsets_info (&ppc_regsets_info
);