1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
75 #include "nat/gdb_ptrace.h"
78 #ifndef PTRACE_GET_THREAD_AREA
79 #define PTRACE_GET_THREAD_AREA 25
82 /* This definition comes from prctl.h, but some kernels may not have it. */
83 #ifndef PTRACE_ARCH_PRCTL
84 #define PTRACE_ARCH_PRCTL 30
87 /* The following definitions come from prctl.h, but may be absent
88 for certain configurations. */
90 #define ARCH_SET_GS 0x1001
91 #define ARCH_SET_FS 0x1002
92 #define ARCH_GET_FS 0x1003
93 #define ARCH_GET_GS 0x1004
96 /* Per-process arch-specific data we want to keep. */
98 struct arch_process_info
100 struct x86_debug_reg_state debug_reg_state
;
105 /* Mapping between the general-purpose registers in `struct user'
106 format and GDB's register array layout.
107 Note that the transfer layout uses 64-bit regs. */
108 static /*const*/ int i386_regmap
[] =
110 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
111 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
112 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
113 DS
* 8, ES
* 8, FS
* 8, GS
* 8
116 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
118 /* So code below doesn't have to care, i386 or amd64. */
119 #define ORIG_EAX ORIG_RAX
122 static const int x86_64_regmap
[] =
124 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
125 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
126 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
127 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
128 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
129 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
130 -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1,
134 -1, -1, -1, -1, -1, -1, -1, -1,
136 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
141 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
142 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
143 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
144 -1, -1, -1, -1, -1, -1, -1, -1,
145 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
146 -1, -1, -1, -1, -1, -1, -1, -1,
147 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
148 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
149 -1, -1, -1, -1, -1, -1, -1, -1,
150 -1, -1, -1, -1, -1, -1, -1, -1,
151 -1, -1, -1, -1, -1, -1, -1, -1
154 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
155 #define X86_64_USER_REGS (GS + 1)
157 #else /* ! __x86_64__ */
159 /* Mapping between the general-purpose registers in `struct user'
160 format and GDB's register array layout. */
161 static /*const*/ int i386_regmap
[] =
163 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
164 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
165 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
166 DS
* 4, ES
* 4, FS
* 4, GS
* 4
169 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
177 /* Returns true if the current inferior belongs to a x86-64 process,
181 is_64bit_tdesc (void)
183 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
185 return register_size (regcache
->tdesc
, 0) == 8;
191 /* Called by libthread_db. */
194 ps_get_thread_area (struct ps_prochandle
*ph
,
195 lwpid_t lwpid
, int idx
, void **base
)
198 int use_64bit
= is_64bit_tdesc ();
205 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
209 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
220 unsigned int desc
[4];
222 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
223 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
226 /* Ensure we properly extend the value to 64-bits for x86_64. */
227 *base
= (void *) (uintptr_t) desc
[1];
232 /* Get the thread area address. This is used to recognize which
233 thread is which when tracing with the in-process agent library. We
234 don't read anything from the address, and treat it as opaque; it's
235 the address itself that we assume is unique per-thread. */
238 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
241 int use_64bit
= is_64bit_tdesc ();
246 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
248 *addr
= (CORE_ADDR
) (uintptr_t) base
;
257 struct lwp_info
*lwp
= find_lwp_pid (pid_to_ptid (lwpid
));
258 struct thread_info
*thr
= get_lwp_thread (lwp
);
259 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
260 unsigned int desc
[4];
262 const int reg_thread_area
= 3; /* bits to scale down register value. */
265 collect_register_by_name (regcache
, "gs", &gs
);
267 idx
= gs
>> reg_thread_area
;
269 if (ptrace (PTRACE_GET_THREAD_AREA
,
271 (void *) (long) idx
, (unsigned long) &desc
) < 0)
282 x86_cannot_store_register (int regno
)
285 if (is_64bit_tdesc ())
289 return regno
>= I386_NUM_REGS
;
293 x86_cannot_fetch_register (int regno
)
296 if (is_64bit_tdesc ())
300 return regno
>= I386_NUM_REGS
;
304 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
309 if (register_size (regcache
->tdesc
, 0) == 8)
311 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
312 if (x86_64_regmap
[i
] != -1)
313 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
315 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
318 int lwpid
= lwpid_of (current_thread
);
320 collect_register_by_name (regcache
, "fs_base", &base
);
321 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
323 collect_register_by_name (regcache
, "gs_base", &base
);
324 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
331 /* 32-bit inferior registers need to be zero-extended.
332 Callers would read uninitialized memory otherwise. */
333 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
336 for (i
= 0; i
< I386_NUM_REGS
; i
++)
337 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
339 collect_register_by_name (regcache
, "orig_eax",
340 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
344 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
349 if (register_size (regcache
->tdesc
, 0) == 8)
351 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
352 if (x86_64_regmap
[i
] != -1)
353 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
355 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
358 int lwpid
= lwpid_of (current_thread
);
360 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
361 supply_register_by_name (regcache
, "fs_base", &base
);
363 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
364 supply_register_by_name (regcache
, "gs_base", &base
);
371 for (i
= 0; i
< I386_NUM_REGS
; i
++)
372 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
374 supply_register_by_name (regcache
, "orig_eax",
375 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
379 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
382 i387_cache_to_fxsave (regcache
, buf
);
384 i387_cache_to_fsave (regcache
, buf
);
389 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
392 i387_fxsave_to_cache (regcache
, buf
);
394 i387_fsave_to_cache (regcache
, buf
);
401 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
403 i387_cache_to_fxsave (regcache
, buf
);
407 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
409 i387_fxsave_to_cache (regcache
, buf
);
415 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
417 i387_cache_to_xsave (regcache
, buf
);
421 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
423 i387_xsave_to_cache (regcache
, buf
);
426 /* ??? The non-biarch i386 case stores all the i387 regs twice.
427 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
428 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
429 doesn't work. IWBN to avoid the duplication in the case where it
430 does work. Maybe the arch_setup routine could check whether it works
431 and update the supported regsets accordingly. */
433 static struct regset_info x86_regsets
[] =
435 #ifdef HAVE_PTRACE_GETREGS
436 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
438 x86_fill_gregset
, x86_store_gregset
},
439 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
440 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
442 # ifdef HAVE_PTRACE_GETFPXREGS
443 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
445 x86_fill_fpxregset
, x86_store_fpxregset
},
448 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
450 x86_fill_fpregset
, x86_store_fpregset
},
451 #endif /* HAVE_PTRACE_GETREGS */
456 x86_get_pc (struct regcache
*regcache
)
458 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
464 collect_register_by_name (regcache
, "rip", &pc
);
465 return (CORE_ADDR
) pc
;
471 collect_register_by_name (regcache
, "eip", &pc
);
472 return (CORE_ADDR
) pc
;
477 x86_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
479 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
485 supply_register_by_name (regcache
, "rip", &newpc
);
491 supply_register_by_name (regcache
, "eip", &newpc
);
495 static const gdb_byte x86_breakpoint
[] = { 0xCC };
496 #define x86_breakpoint_len 1
499 x86_breakpoint_at (CORE_ADDR pc
)
503 (*the_target
->read_memory
) (pc
, &c
, 1);
510 /* Low-level function vector. */
511 struct x86_dr_low_type x86_dr_low
=
513 x86_linux_dr_set_control
,
514 x86_linux_dr_set_addr
,
515 x86_linux_dr_get_addr
,
516 x86_linux_dr_get_status
,
517 x86_linux_dr_get_control
,
521 /* Breakpoint/Watchpoint support. */
524 x86_supports_z_point_type (char z_type
)
530 case Z_PACKET_WRITE_WP
:
531 case Z_PACKET_ACCESS_WP
:
539 x86_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
540 int size
, struct raw_breakpoint
*bp
)
542 struct process_info
*proc
= current_process ();
546 case raw_bkpt_type_hw
:
547 case raw_bkpt_type_write_wp
:
548 case raw_bkpt_type_access_wp
:
550 enum target_hw_bp_type hw_type
551 = raw_bkpt_type_to_target_hw_bp_type (type
);
552 struct x86_debug_reg_state
*state
553 = &proc
->priv
->arch_private
->debug_reg_state
;
555 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
565 x86_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
566 int size
, struct raw_breakpoint
*bp
)
568 struct process_info
*proc
= current_process ();
572 case raw_bkpt_type_hw
:
573 case raw_bkpt_type_write_wp
:
574 case raw_bkpt_type_access_wp
:
576 enum target_hw_bp_type hw_type
577 = raw_bkpt_type_to_target_hw_bp_type (type
);
578 struct x86_debug_reg_state
*state
579 = &proc
->priv
->arch_private
->debug_reg_state
;
581 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
590 x86_stopped_by_watchpoint (void)
592 struct process_info
*proc
= current_process ();
593 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
597 x86_stopped_data_address (void)
599 struct process_info
*proc
= current_process ();
601 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
607 /* Called when a new process is created. */
609 static struct arch_process_info
*
610 x86_linux_new_process (void)
612 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
614 x86_low_init_dregs (&info
->debug_reg_state
);
619 /* Target routine for linux_new_fork. */
622 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
624 /* These are allocated by linux_add_process. */
625 gdb_assert (parent
->priv
!= NULL
626 && parent
->priv
->arch_private
!= NULL
);
627 gdb_assert (child
->priv
!= NULL
628 && child
->priv
->arch_private
!= NULL
);
630 /* Linux kernel before 2.6.33 commit
631 72f674d203cd230426437cdcf7dd6f681dad8b0d
632 will inherit hardware debug registers from parent
633 on fork/vfork/clone. Newer Linux kernels create such tasks with
634 zeroed debug registers.
636 GDB core assumes the child inherits the watchpoints/hw
637 breakpoints of the parent, and will remove them all from the
638 forked off process. Copy the debug registers mirrors into the
639 new process so that all breakpoints and watchpoints can be
640 removed together. The debug registers mirror will become zeroed
641 in the end before detaching the forked off process, thus making
642 this compatible with older Linux kernels too. */
644 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
647 /* See nat/x86-dregs.h. */
649 struct x86_debug_reg_state
*
650 x86_debug_reg_state (pid_t pid
)
652 struct process_info
*proc
= find_process_pid (pid
);
654 return &proc
->priv
->arch_private
->debug_reg_state
;
657 /* When GDBSERVER is built as a 64-bit application on linux, the
658 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
659 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
660 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
661 conversion in-place ourselves. */
663 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
664 layout of the inferiors' architecture. Returns true if any
665 conversion was done; false otherwise. If DIRECTION is 1, then copy
666 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
670 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
673 unsigned int machine
;
674 int tid
= lwpid_of (current_thread
);
675 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
677 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
678 if (!is_64bit_tdesc ())
679 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
681 /* No fixup for native x32 GDB. */
682 else if (!is_elf64
&& sizeof (void *) == 8)
683 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
692 /* Format of XSAVE extended state is:
696 sw_usable_bytes[464..511]
697 xstate_hdr_bytes[512..575]
702 Same memory layout will be used for the coredump NT_X86_XSTATE
703 representing the XSAVE extended state registers.
705 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
706 extended state mask, which is the same as the extended control register
707 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
708 together with the mask saved in the xstate_hdr_bytes to determine what
709 states the processor/OS supports and what state, used or initialized,
710 the process/thread is in. */
711 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
713 /* Does the current host support the GETFPXREGS request? The header
714 file may or may not define it, and even if it is defined, the
715 kernel will return EIO if it's running on a pre-SSE processor. */
716 int have_ptrace_getfpxregs
=
717 #ifdef HAVE_PTRACE_GETFPXREGS
724 /* Get Linux/x86 target description from running target. */
726 static const struct target_desc
*
727 x86_linux_read_description (void)
729 unsigned int machine
;
733 static uint64_t xcr0
;
734 struct regset_info
*regset
;
736 tid
= lwpid_of (current_thread
);
738 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
740 if (sizeof (void *) == 4)
743 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
745 else if (machine
== EM_X86_64
)
746 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
750 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
751 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
753 elf_fpxregset_t fpxregs
;
755 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
757 have_ptrace_getfpxregs
= 0;
758 have_ptrace_getregset
= 0;
759 return tdesc_i386_mmx_linux
;
762 have_ptrace_getfpxregs
= 1;
768 x86_xcr0
= X86_XSTATE_SSE_MASK
;
772 if (machine
== EM_X86_64
)
773 return tdesc_amd64_linux_no_xml
;
776 return tdesc_i386_linux_no_xml
;
779 if (have_ptrace_getregset
== -1)
781 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
784 iov
.iov_base
= xstateregs
;
785 iov
.iov_len
= sizeof (xstateregs
);
787 /* Check if PTRACE_GETREGSET works. */
788 if (ptrace (PTRACE_GETREGSET
, tid
,
789 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
790 have_ptrace_getregset
= 0;
793 have_ptrace_getregset
= 1;
795 /* Get XCR0 from XSAVE extended state. */
796 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
797 / sizeof (uint64_t))];
799 /* Use PTRACE_GETREGSET if it is available. */
800 for (regset
= x86_regsets
;
801 regset
->fill_function
!= NULL
; regset
++)
802 if (regset
->get_request
== PTRACE_GETREGSET
)
803 regset
->size
= X86_XSTATE_SIZE (xcr0
);
804 else if (regset
->type
!= GENERAL_REGS
)
809 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
810 xcr0_features
= (have_ptrace_getregset
811 && (xcr0
& X86_XSTATE_ALL_MASK
));
816 if (machine
== EM_X86_64
)
823 switch (xcr0
& X86_XSTATE_ALL_MASK
)
825 case X86_XSTATE_AVX512_MASK
:
826 return tdesc_amd64_avx512_linux
;
828 case X86_XSTATE_AVX_MPX_MASK
:
829 return tdesc_amd64_avx_mpx_linux
;
831 case X86_XSTATE_MPX_MASK
:
832 return tdesc_amd64_mpx_linux
;
834 case X86_XSTATE_AVX_MASK
:
835 return tdesc_amd64_avx_linux
;
838 return tdesc_amd64_linux
;
842 return tdesc_amd64_linux
;
848 switch (xcr0
& X86_XSTATE_ALL_MASK
)
850 case X86_XSTATE_AVX512_MASK
:
851 return tdesc_x32_avx512_linux
;
853 case X86_XSTATE_MPX_MASK
: /* No MPX on x32. */
854 case X86_XSTATE_AVX_MASK
:
855 return tdesc_x32_avx_linux
;
858 return tdesc_x32_linux
;
862 return tdesc_x32_linux
;
870 switch (xcr0
& X86_XSTATE_ALL_MASK
)
872 case (X86_XSTATE_AVX512_MASK
):
873 return tdesc_i386_avx512_linux
;
875 case (X86_XSTATE_MPX_MASK
):
876 return tdesc_i386_mpx_linux
;
878 case (X86_XSTATE_AVX_MPX_MASK
):
879 return tdesc_i386_avx_mpx_linux
;
881 case (X86_XSTATE_AVX_MASK
):
882 return tdesc_i386_avx_linux
;
885 return tdesc_i386_linux
;
889 return tdesc_i386_linux
;
892 gdb_assert_not_reached ("failed to return tdesc");
895 /* Callback for find_inferior. Stops iteration when a thread with a
896 given PID is found. */
899 same_process_callback (struct inferior_list_entry
*entry
, void *data
)
901 int pid
= *(int *) data
;
903 return (ptid_get_pid (entry
->id
) == pid
);
906 /* Callback for for_each_inferior. Calls the arch_setup routine for
910 x86_arch_setup_process_callback (struct inferior_list_entry
*entry
)
912 int pid
= ptid_get_pid (entry
->id
);
914 /* Look up any thread of this processes. */
916 = (struct thread_info
*) find_inferior (&all_threads
,
917 same_process_callback
, &pid
);
919 the_low_target
.arch_setup ();
922 /* Update all the target description of all processes; a new GDB
923 connected, and it may or not support xml target descriptions. */
926 x86_linux_update_xmltarget (void)
928 struct thread_info
*saved_thread
= current_thread
;
930 /* Before changing the register cache's internal layout, flush the
931 contents of the current valid caches back to the threads, and
932 release the current regcache objects. */
935 for_each_inferior (&all_processes
, x86_arch_setup_process_callback
);
937 current_thread
= saved_thread
;
940 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
944 x86_linux_process_qsupported (char **features
, int count
)
948 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
949 with "i386" in qSupported query, it supports x86 XML target
952 for (i
= 0; i
< count
; i
++)
954 const char *feature
= features
[i
];
956 if (startswith (feature
, "xmlRegisters="))
958 char *copy
= xstrdup (feature
+ 13);
961 for (p
= strtok (copy
, ","); p
!= NULL
; p
= strtok (NULL
, ","))
963 if (strcmp (p
, "i386") == 0)
973 x86_linux_update_xmltarget ();
976 /* Common for x86/x86-64. */
978 static struct regsets_info x86_regsets_info
=
980 x86_regsets
, /* regsets */
982 NULL
, /* disabled_regsets */
986 static struct regs_info amd64_linux_regs_info
=
988 NULL
, /* regset_bitmap */
989 NULL
, /* usrregs_info */
993 static struct usrregs_info i386_linux_usrregs_info
=
999 static struct regs_info i386_linux_regs_info
=
1001 NULL
, /* regset_bitmap */
1002 &i386_linux_usrregs_info
,
1006 const struct regs_info
*
1007 x86_linux_regs_info (void)
1010 if (is_64bit_tdesc ())
1011 return &amd64_linux_regs_info
;
1014 return &i386_linux_regs_info
;
1017 /* Initialize the target description for the architecture of the
1021 x86_arch_setup (void)
1023 current_process ()->tdesc
= x86_linux_read_description ();
1026 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1027 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1030 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1032 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1038 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1039 *sysno
= (int) l_sysno
;
1042 collect_register_by_name (regcache
, "orig_eax", sysno
);
1046 x86_supports_tracepoints (void)
1052 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1054 write_inferior_memory (*to
, buf
, len
);
1059 push_opcode (unsigned char *buf
, char *op
)
1061 unsigned char *buf_org
= buf
;
1066 unsigned long ul
= strtoul (op
, &endptr
, 16);
1075 return buf
- buf_org
;
1080 /* Build a jump pad that saves registers and calls a collection
1081 function. Writes a jump instruction to the jump pad to
1082 JJUMPAD_INSN. The caller is responsible to write it in at the
1083 tracepoint address. */
1086 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1087 CORE_ADDR collector
,
1090 CORE_ADDR
*jump_entry
,
1091 CORE_ADDR
*trampoline
,
1092 ULONGEST
*trampoline_size
,
1093 unsigned char *jjump_pad_insn
,
1094 ULONGEST
*jjump_pad_insn_size
,
1095 CORE_ADDR
*adjusted_insn_addr
,
1096 CORE_ADDR
*adjusted_insn_addr_end
,
1099 unsigned char buf
[40];
1103 CORE_ADDR buildaddr
= *jump_entry
;
1105 /* Build the jump pad. */
1107 /* First, do tracepoint data collection. Save registers. */
1109 /* Need to ensure stack pointer saved first. */
1110 buf
[i
++] = 0x54; /* push %rsp */
1111 buf
[i
++] = 0x55; /* push %rbp */
1112 buf
[i
++] = 0x57; /* push %rdi */
1113 buf
[i
++] = 0x56; /* push %rsi */
1114 buf
[i
++] = 0x52; /* push %rdx */
1115 buf
[i
++] = 0x51; /* push %rcx */
1116 buf
[i
++] = 0x53; /* push %rbx */
1117 buf
[i
++] = 0x50; /* push %rax */
1118 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1119 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1120 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1121 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1122 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1123 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1124 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1125 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1126 buf
[i
++] = 0x9c; /* pushfq */
1127 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1129 memcpy (buf
+ i
, &tpaddr
, 8);
1131 buf
[i
++] = 0x57; /* push %rdi */
1132 append_insns (&buildaddr
, i
, buf
);
1134 /* Stack space for the collecting_t object. */
1136 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1137 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1138 memcpy (buf
+ i
, &tpoint
, 8);
1140 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1141 i
+= push_opcode (&buf
[i
],
1142 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1143 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1144 append_insns (&buildaddr
, i
, buf
);
1148 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1149 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1151 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1152 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1153 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1154 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1155 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1156 append_insns (&buildaddr
, i
, buf
);
1158 /* Set up the gdb_collect call. */
1159 /* At this point, (stack pointer + 0x18) is the base of our saved
1163 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1164 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1166 /* tpoint address may be 64-bit wide. */
1167 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1168 memcpy (buf
+ i
, &tpoint
, 8);
1170 append_insns (&buildaddr
, i
, buf
);
1172 /* The collector function being in the shared library, may be
1173 >31-bits away off the jump pad. */
1175 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1176 memcpy (buf
+ i
, &collector
, 8);
1178 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1179 append_insns (&buildaddr
, i
, buf
);
1181 /* Clear the spin-lock. */
1183 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1184 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1185 memcpy (buf
+ i
, &lockaddr
, 8);
1187 append_insns (&buildaddr
, i
, buf
);
1189 /* Remove stack that had been used for the collect_t object. */
1191 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1192 append_insns (&buildaddr
, i
, buf
);
1194 /* Restore register state. */
1196 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1200 buf
[i
++] = 0x9d; /* popfq */
1201 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1202 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1203 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1204 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1205 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1206 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1207 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1208 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1209 buf
[i
++] = 0x58; /* pop %rax */
1210 buf
[i
++] = 0x5b; /* pop %rbx */
1211 buf
[i
++] = 0x59; /* pop %rcx */
1212 buf
[i
++] = 0x5a; /* pop %rdx */
1213 buf
[i
++] = 0x5e; /* pop %rsi */
1214 buf
[i
++] = 0x5f; /* pop %rdi */
1215 buf
[i
++] = 0x5d; /* pop %rbp */
1216 buf
[i
++] = 0x5c; /* pop %rsp */
1217 append_insns (&buildaddr
, i
, buf
);
1219 /* Now, adjust the original instruction to execute in the jump
1221 *adjusted_insn_addr
= buildaddr
;
1222 relocate_instruction (&buildaddr
, tpaddr
);
1223 *adjusted_insn_addr_end
= buildaddr
;
1225 /* Finally, write a jump back to the program. */
1227 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1228 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1231 "E.Jump back from jump pad too far from tracepoint "
1232 "(offset 0x%" PRIx64
" > int32).", loffset
);
1236 offset
= (int) loffset
;
1237 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1238 memcpy (buf
+ 1, &offset
, 4);
1239 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1241 /* The jump pad is now built. Wire in a jump to our jump pad. This
1242 is always done last (by our caller actually), so that we can
1243 install fast tracepoints with threads running. This relies on
1244 the agent's atomic write support. */
1245 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1246 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1249 "E.Jump pad too far from tracepoint "
1250 "(offset 0x%" PRIx64
" > int32).", loffset
);
1254 offset
= (int) loffset
;
1256 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1257 memcpy (buf
+ 1, &offset
, 4);
1258 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1259 *jjump_pad_insn_size
= sizeof (jump_insn
);
1261 /* Return the end address of our pad. */
1262 *jump_entry
= buildaddr
;
1267 #endif /* __x86_64__ */
1269 /* Build a jump pad that saves registers and calls a collection
1270 function. Writes a jump instruction to the jump pad to
1271 JJUMPAD_INSN. The caller is responsible to write it in at the
1272 tracepoint address. */
1275 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1276 CORE_ADDR collector
,
1279 CORE_ADDR
*jump_entry
,
1280 CORE_ADDR
*trampoline
,
1281 ULONGEST
*trampoline_size
,
1282 unsigned char *jjump_pad_insn
,
1283 ULONGEST
*jjump_pad_insn_size
,
1284 CORE_ADDR
*adjusted_insn_addr
,
1285 CORE_ADDR
*adjusted_insn_addr_end
,
1288 unsigned char buf
[0x100];
1290 CORE_ADDR buildaddr
= *jump_entry
;
1292 /* Build the jump pad. */
1294 /* First, do tracepoint data collection. Save registers. */
1296 buf
[i
++] = 0x60; /* pushad */
1297 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1298 *((int *)(buf
+ i
)) = (int) tpaddr
;
1300 buf
[i
++] = 0x9c; /* pushf */
1301 buf
[i
++] = 0x1e; /* push %ds */
1302 buf
[i
++] = 0x06; /* push %es */
1303 buf
[i
++] = 0x0f; /* push %fs */
1305 buf
[i
++] = 0x0f; /* push %gs */
1307 buf
[i
++] = 0x16; /* push %ss */
1308 buf
[i
++] = 0x0e; /* push %cs */
1309 append_insns (&buildaddr
, i
, buf
);
1311 /* Stack space for the collecting_t object. */
1313 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1315 /* Build the object. */
1316 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1317 memcpy (buf
+ i
, &tpoint
, 4);
1319 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1321 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1322 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1323 append_insns (&buildaddr
, i
, buf
);
1325 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1326 If we cared for it, this could be using xchg alternatively. */
1329 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1330 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1332 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1334 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1335 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1336 append_insns (&buildaddr
, i
, buf
);
1339 /* Set up arguments to the gdb_collect call. */
1341 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1342 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1343 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1344 append_insns (&buildaddr
, i
, buf
);
1347 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1348 append_insns (&buildaddr
, i
, buf
);
1351 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1352 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1354 append_insns (&buildaddr
, i
, buf
);
1356 buf
[0] = 0xe8; /* call <reladdr> */
1357 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1358 memcpy (buf
+ 1, &offset
, 4);
1359 append_insns (&buildaddr
, 5, buf
);
1360 /* Clean up after the call. */
1361 buf
[0] = 0x83; /* add $0x8,%esp */
1364 append_insns (&buildaddr
, 3, buf
);
1367 /* Clear the spin-lock. This would need the LOCK prefix on older
1370 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1371 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1372 memcpy (buf
+ i
, &lockaddr
, 4);
1374 append_insns (&buildaddr
, i
, buf
);
1377 /* Remove stack that had been used for the collect_t object. */
1379 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1380 append_insns (&buildaddr
, i
, buf
);
1383 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1386 buf
[i
++] = 0x17; /* pop %ss */
1387 buf
[i
++] = 0x0f; /* pop %gs */
1389 buf
[i
++] = 0x0f; /* pop %fs */
1391 buf
[i
++] = 0x07; /* pop %es */
1392 buf
[i
++] = 0x1f; /* pop %ds */
1393 buf
[i
++] = 0x9d; /* popf */
1394 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1397 buf
[i
++] = 0x61; /* popad */
1398 append_insns (&buildaddr
, i
, buf
);
1400 /* Now, adjust the original instruction to execute in the jump
1402 *adjusted_insn_addr
= buildaddr
;
1403 relocate_instruction (&buildaddr
, tpaddr
);
1404 *adjusted_insn_addr_end
= buildaddr
;
1406 /* Write the jump back to the program. */
1407 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1408 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1409 memcpy (buf
+ 1, &offset
, 4);
1410 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1412 /* The jump pad is now built. Wire in a jump to our jump pad. This
1413 is always done last (by our caller actually), so that we can
1414 install fast tracepoints with threads running. This relies on
1415 the agent's atomic write support. */
1418 /* Create a trampoline. */
1419 *trampoline_size
= sizeof (jump_insn
);
1420 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1422 /* No trampoline space available. */
1424 "E.Cannot allocate trampoline space needed for fast "
1425 "tracepoints on 4-byte instructions.");
1429 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1430 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1431 memcpy (buf
+ 1, &offset
, 4);
1432 write_inferior_memory (*trampoline
, buf
, sizeof (jump_insn
));
1434 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1435 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1436 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1437 memcpy (buf
+ 2, &offset
, 2);
1438 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1439 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1443 /* Else use a 32-bit relative jump instruction. */
1444 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1445 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1446 memcpy (buf
+ 1, &offset
, 4);
1447 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1448 *jjump_pad_insn_size
= sizeof (jump_insn
);
1451 /* Return the end address of our pad. */
1452 *jump_entry
= buildaddr
;
1458 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1459 CORE_ADDR collector
,
1462 CORE_ADDR
*jump_entry
,
1463 CORE_ADDR
*trampoline
,
1464 ULONGEST
*trampoline_size
,
1465 unsigned char *jjump_pad_insn
,
1466 ULONGEST
*jjump_pad_insn_size
,
1467 CORE_ADDR
*adjusted_insn_addr
,
1468 CORE_ADDR
*adjusted_insn_addr_end
,
1472 if (is_64bit_tdesc ())
1473 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1474 collector
, lockaddr
,
1475 orig_size
, jump_entry
,
1476 trampoline
, trampoline_size
,
1478 jjump_pad_insn_size
,
1480 adjusted_insn_addr_end
,
1484 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1485 collector
, lockaddr
,
1486 orig_size
, jump_entry
,
1487 trampoline
, trampoline_size
,
1489 jjump_pad_insn_size
,
1491 adjusted_insn_addr_end
,
1495 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1499 x86_get_min_fast_tracepoint_insn_len (void)
1501 static int warned_about_fast_tracepoints
= 0;
1504 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1505 used for fast tracepoints. */
1506 if (is_64bit_tdesc ())
1510 if (agent_loaded_p ())
1512 char errbuf
[IPA_BUFSIZ
];
1516 /* On x86, if trampolines are available, then 4-byte jump instructions
1517 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1518 with a 4-byte offset are used instead. */
1519 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1523 /* GDB has no channel to explain to user why a shorter fast
1524 tracepoint is not possible, but at least make GDBserver
1525 mention that something has gone awry. */
1526 if (!warned_about_fast_tracepoints
)
1528 warning ("4-byte fast tracepoints not available; %s\n", errbuf
);
1529 warned_about_fast_tracepoints
= 1;
1536 /* Indicate that the minimum length is currently unknown since the IPA
1537 has not loaded yet. */
1543 add_insns (unsigned char *start
, int len
)
1545 CORE_ADDR buildaddr
= current_insn_ptr
;
1548 debug_printf ("Adding %d bytes of insn at %s\n",
1549 len
, paddress (buildaddr
));
1551 append_insns (&buildaddr
, len
, start
);
1552 current_insn_ptr
= buildaddr
;
1555 /* Our general strategy for emitting code is to avoid specifying raw
1556 bytes whenever possible, and instead copy a block of inline asm
1557 that is embedded in the function. This is a little messy, because
1558 we need to keep the compiler from discarding what looks like dead
1559 code, plus suppress various warnings. */
1561 #define EMIT_ASM(NAME, INSNS) \
1564 extern unsigned char start_ ## NAME, end_ ## NAME; \
1565 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1566 __asm__ ("jmp end_" #NAME "\n" \
1567 "\t" "start_" #NAME ":" \
1569 "\t" "end_" #NAME ":"); \
1574 #define EMIT_ASM32(NAME,INSNS) \
1577 extern unsigned char start_ ## NAME, end_ ## NAME; \
1578 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1579 __asm__ (".code32\n" \
1580 "\t" "jmp end_" #NAME "\n" \
1581 "\t" "start_" #NAME ":\n" \
1583 "\t" "end_" #NAME ":\n" \
1589 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1596 amd64_emit_prologue (void)
1598 EMIT_ASM (amd64_prologue
,
1600 "movq %rsp,%rbp\n\t"
1601 "sub $0x20,%rsp\n\t"
1602 "movq %rdi,-8(%rbp)\n\t"
1603 "movq %rsi,-16(%rbp)");
1608 amd64_emit_epilogue (void)
1610 EMIT_ASM (amd64_epilogue
,
1611 "movq -16(%rbp),%rdi\n\t"
1612 "movq %rax,(%rdi)\n\t"
1619 amd64_emit_add (void)
1621 EMIT_ASM (amd64_add
,
1622 "add (%rsp),%rax\n\t"
1623 "lea 0x8(%rsp),%rsp");
1627 amd64_emit_sub (void)
1629 EMIT_ASM (amd64_sub
,
1630 "sub %rax,(%rsp)\n\t"
1635 amd64_emit_mul (void)
1641 amd64_emit_lsh (void)
1647 amd64_emit_rsh_signed (void)
1653 amd64_emit_rsh_unsigned (void)
1659 amd64_emit_ext (int arg
)
1664 EMIT_ASM (amd64_ext_8
,
1670 EMIT_ASM (amd64_ext_16
,
1675 EMIT_ASM (amd64_ext_32
,
1684 amd64_emit_log_not (void)
1686 EMIT_ASM (amd64_log_not
,
1687 "test %rax,%rax\n\t"
1693 amd64_emit_bit_and (void)
1695 EMIT_ASM (amd64_and
,
1696 "and (%rsp),%rax\n\t"
1697 "lea 0x8(%rsp),%rsp");
1701 amd64_emit_bit_or (void)
1704 "or (%rsp),%rax\n\t"
1705 "lea 0x8(%rsp),%rsp");
1709 amd64_emit_bit_xor (void)
1711 EMIT_ASM (amd64_xor
,
1712 "xor (%rsp),%rax\n\t"
1713 "lea 0x8(%rsp),%rsp");
1717 amd64_emit_bit_not (void)
1719 EMIT_ASM (amd64_bit_not
,
1720 "xorq $0xffffffffffffffff,%rax");
1724 amd64_emit_equal (void)
1726 EMIT_ASM (amd64_equal
,
1727 "cmp %rax,(%rsp)\n\t"
1728 "je .Lamd64_equal_true\n\t"
1730 "jmp .Lamd64_equal_end\n\t"
1731 ".Lamd64_equal_true:\n\t"
1733 ".Lamd64_equal_end:\n\t"
1734 "lea 0x8(%rsp),%rsp");
1738 amd64_emit_less_signed (void)
1740 EMIT_ASM (amd64_less_signed
,
1741 "cmp %rax,(%rsp)\n\t"
1742 "jl .Lamd64_less_signed_true\n\t"
1744 "jmp .Lamd64_less_signed_end\n\t"
1745 ".Lamd64_less_signed_true:\n\t"
1747 ".Lamd64_less_signed_end:\n\t"
1748 "lea 0x8(%rsp),%rsp");
1752 amd64_emit_less_unsigned (void)
1754 EMIT_ASM (amd64_less_unsigned
,
1755 "cmp %rax,(%rsp)\n\t"
1756 "jb .Lamd64_less_unsigned_true\n\t"
1758 "jmp .Lamd64_less_unsigned_end\n\t"
1759 ".Lamd64_less_unsigned_true:\n\t"
1761 ".Lamd64_less_unsigned_end:\n\t"
1762 "lea 0x8(%rsp),%rsp");
1766 amd64_emit_ref (int size
)
1771 EMIT_ASM (amd64_ref1
,
1775 EMIT_ASM (amd64_ref2
,
1779 EMIT_ASM (amd64_ref4
,
1780 "movl (%rax),%eax");
1783 EMIT_ASM (amd64_ref8
,
1784 "movq (%rax),%rax");
1790 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1792 EMIT_ASM (amd64_if_goto
,
1796 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1804 amd64_emit_goto (int *offset_p
, int *size_p
)
1806 EMIT_ASM (amd64_goto
,
1807 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1815 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1817 int diff
= (to
- (from
+ size
));
1818 unsigned char buf
[sizeof (int)];
1826 memcpy (buf
, &diff
, sizeof (int));
1827 write_inferior_memory (from
, buf
, sizeof (int));
1831 amd64_emit_const (LONGEST num
)
1833 unsigned char buf
[16];
1835 CORE_ADDR buildaddr
= current_insn_ptr
;
1838 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1839 memcpy (&buf
[i
], &num
, sizeof (num
));
1841 append_insns (&buildaddr
, i
, buf
);
1842 current_insn_ptr
= buildaddr
;
1846 amd64_emit_call (CORE_ADDR fn
)
1848 unsigned char buf
[16];
1850 CORE_ADDR buildaddr
;
1853 /* The destination function being in the shared library, may be
1854 >31-bits away off the compiled code pad. */
1856 buildaddr
= current_insn_ptr
;
1858 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1862 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1864 /* Offset is too large for a call. Use callq, but that requires
1865 a register, so avoid it if possible. Use r10, since it is
1866 call-clobbered, we don't have to push/pop it. */
1867 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1869 memcpy (buf
+ i
, &fn
, 8);
1871 buf
[i
++] = 0xff; /* callq *%r10 */
1876 int offset32
= offset64
; /* we know we can't overflow here. */
1878 buf
[i
++] = 0xe8; /* call <reladdr> */
1879 memcpy (buf
+ i
, &offset32
, 4);
1883 append_insns (&buildaddr
, i
, buf
);
1884 current_insn_ptr
= buildaddr
;
1888 amd64_emit_reg (int reg
)
1890 unsigned char buf
[16];
1892 CORE_ADDR buildaddr
;
1894 /* Assume raw_regs is still in %rdi. */
1895 buildaddr
= current_insn_ptr
;
1897 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1898 memcpy (&buf
[i
], ®
, sizeof (reg
));
1900 append_insns (&buildaddr
, i
, buf
);
1901 current_insn_ptr
= buildaddr
;
1902 amd64_emit_call (get_raw_reg_func_addr ());
1906 amd64_emit_pop (void)
1908 EMIT_ASM (amd64_pop
,
1913 amd64_emit_stack_flush (void)
1915 EMIT_ASM (amd64_stack_flush
,
1920 amd64_emit_zero_ext (int arg
)
1925 EMIT_ASM (amd64_zero_ext_8
,
1929 EMIT_ASM (amd64_zero_ext_16
,
1930 "and $0xffff,%rax");
1933 EMIT_ASM (amd64_zero_ext_32
,
1934 "mov $0xffffffff,%rcx\n\t"
1943 amd64_emit_swap (void)
1945 EMIT_ASM (amd64_swap
,
1952 amd64_emit_stack_adjust (int n
)
1954 unsigned char buf
[16];
1956 CORE_ADDR buildaddr
= current_insn_ptr
;
1959 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1963 /* This only handles adjustments up to 16, but we don't expect any more. */
1965 append_insns (&buildaddr
, i
, buf
);
1966 current_insn_ptr
= buildaddr
;
1969 /* FN's prototype is `LONGEST(*fn)(int)'. */
1972 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1974 unsigned char buf
[16];
1976 CORE_ADDR buildaddr
;
1978 buildaddr
= current_insn_ptr
;
1980 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1981 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1983 append_insns (&buildaddr
, i
, buf
);
1984 current_insn_ptr
= buildaddr
;
1985 amd64_emit_call (fn
);
1988 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
1991 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
1993 unsigned char buf
[16];
1995 CORE_ADDR buildaddr
;
1997 buildaddr
= current_insn_ptr
;
1999 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2000 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2002 append_insns (&buildaddr
, i
, buf
);
2003 current_insn_ptr
= buildaddr
;
2004 EMIT_ASM (amd64_void_call_2_a
,
2005 /* Save away a copy of the stack top. */
2007 /* Also pass top as the second argument. */
2009 amd64_emit_call (fn
);
2010 EMIT_ASM (amd64_void_call_2_b
,
2011 /* Restore the stack top, %rax may have been trashed. */
2016 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2019 "cmp %rax,(%rsp)\n\t"
2020 "jne .Lamd64_eq_fallthru\n\t"
2021 "lea 0x8(%rsp),%rsp\n\t"
2023 /* jmp, but don't trust the assembler to choose the right jump */
2024 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2025 ".Lamd64_eq_fallthru:\n\t"
2026 "lea 0x8(%rsp),%rsp\n\t"
2036 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2039 "cmp %rax,(%rsp)\n\t"
2040 "je .Lamd64_ne_fallthru\n\t"
2041 "lea 0x8(%rsp),%rsp\n\t"
2043 /* jmp, but don't trust the assembler to choose the right jump */
2044 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2045 ".Lamd64_ne_fallthru:\n\t"
2046 "lea 0x8(%rsp),%rsp\n\t"
2056 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2059 "cmp %rax,(%rsp)\n\t"
2060 "jnl .Lamd64_lt_fallthru\n\t"
2061 "lea 0x8(%rsp),%rsp\n\t"
2063 /* jmp, but don't trust the assembler to choose the right jump */
2064 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2065 ".Lamd64_lt_fallthru:\n\t"
2066 "lea 0x8(%rsp),%rsp\n\t"
2076 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2079 "cmp %rax,(%rsp)\n\t"
2080 "jnle .Lamd64_le_fallthru\n\t"
2081 "lea 0x8(%rsp),%rsp\n\t"
2083 /* jmp, but don't trust the assembler to choose the right jump */
2084 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2085 ".Lamd64_le_fallthru:\n\t"
2086 "lea 0x8(%rsp),%rsp\n\t"
2096 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2099 "cmp %rax,(%rsp)\n\t"
2100 "jng .Lamd64_gt_fallthru\n\t"
2101 "lea 0x8(%rsp),%rsp\n\t"
2103 /* jmp, but don't trust the assembler to choose the right jump */
2104 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2105 ".Lamd64_gt_fallthru:\n\t"
2106 "lea 0x8(%rsp),%rsp\n\t"
2116 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2119 "cmp %rax,(%rsp)\n\t"
2120 "jnge .Lamd64_ge_fallthru\n\t"
2121 ".Lamd64_ge_jump:\n\t"
2122 "lea 0x8(%rsp),%rsp\n\t"
2124 /* jmp, but don't trust the assembler to choose the right jump */
2125 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2126 ".Lamd64_ge_fallthru:\n\t"
2127 "lea 0x8(%rsp),%rsp\n\t"
2136 struct emit_ops amd64_emit_ops
=
2138 amd64_emit_prologue
,
2139 amd64_emit_epilogue
,
2144 amd64_emit_rsh_signed
,
2145 amd64_emit_rsh_unsigned
,
2153 amd64_emit_less_signed
,
2154 amd64_emit_less_unsigned
,
2158 amd64_write_goto_address
,
2163 amd64_emit_stack_flush
,
2164 amd64_emit_zero_ext
,
2166 amd64_emit_stack_adjust
,
2167 amd64_emit_int_call_1
,
2168 amd64_emit_void_call_2
,
2177 #endif /* __x86_64__ */
2180 i386_emit_prologue (void)
2182 EMIT_ASM32 (i386_prologue
,
2186 /* At this point, the raw regs base address is at 8(%ebp), and the
2187 value pointer is at 12(%ebp). */
2191 i386_emit_epilogue (void)
2193 EMIT_ASM32 (i386_epilogue
,
2194 "mov 12(%ebp),%ecx\n\t"
2195 "mov %eax,(%ecx)\n\t"
2196 "mov %ebx,0x4(%ecx)\n\t"
2204 i386_emit_add (void)
2206 EMIT_ASM32 (i386_add
,
2207 "add (%esp),%eax\n\t"
2208 "adc 0x4(%esp),%ebx\n\t"
2209 "lea 0x8(%esp),%esp");
2213 i386_emit_sub (void)
2215 EMIT_ASM32 (i386_sub
,
2216 "subl %eax,(%esp)\n\t"
2217 "sbbl %ebx,4(%esp)\n\t"
2223 i386_emit_mul (void)
2229 i386_emit_lsh (void)
2235 i386_emit_rsh_signed (void)
2241 i386_emit_rsh_unsigned (void)
2247 i386_emit_ext (int arg
)
2252 EMIT_ASM32 (i386_ext_8
,
2255 "movl %eax,%ebx\n\t"
2259 EMIT_ASM32 (i386_ext_16
,
2261 "movl %eax,%ebx\n\t"
2265 EMIT_ASM32 (i386_ext_32
,
2266 "movl %eax,%ebx\n\t"
2275 i386_emit_log_not (void)
2277 EMIT_ASM32 (i386_log_not
,
2279 "test %eax,%eax\n\t"
2286 i386_emit_bit_and (void)
2288 EMIT_ASM32 (i386_and
,
2289 "and (%esp),%eax\n\t"
2290 "and 0x4(%esp),%ebx\n\t"
2291 "lea 0x8(%esp),%esp");
2295 i386_emit_bit_or (void)
2297 EMIT_ASM32 (i386_or
,
2298 "or (%esp),%eax\n\t"
2299 "or 0x4(%esp),%ebx\n\t"
2300 "lea 0x8(%esp),%esp");
2304 i386_emit_bit_xor (void)
2306 EMIT_ASM32 (i386_xor
,
2307 "xor (%esp),%eax\n\t"
2308 "xor 0x4(%esp),%ebx\n\t"
2309 "lea 0x8(%esp),%esp");
2313 i386_emit_bit_not (void)
2315 EMIT_ASM32 (i386_bit_not
,
2316 "xor $0xffffffff,%eax\n\t"
2317 "xor $0xffffffff,%ebx\n\t");
2321 i386_emit_equal (void)
2323 EMIT_ASM32 (i386_equal
,
2324 "cmpl %ebx,4(%esp)\n\t"
2325 "jne .Li386_equal_false\n\t"
2326 "cmpl %eax,(%esp)\n\t"
2327 "je .Li386_equal_true\n\t"
2328 ".Li386_equal_false:\n\t"
2330 "jmp .Li386_equal_end\n\t"
2331 ".Li386_equal_true:\n\t"
2333 ".Li386_equal_end:\n\t"
2335 "lea 0x8(%esp),%esp");
2339 i386_emit_less_signed (void)
2341 EMIT_ASM32 (i386_less_signed
,
2342 "cmpl %ebx,4(%esp)\n\t"
2343 "jl .Li386_less_signed_true\n\t"
2344 "jne .Li386_less_signed_false\n\t"
2345 "cmpl %eax,(%esp)\n\t"
2346 "jl .Li386_less_signed_true\n\t"
2347 ".Li386_less_signed_false:\n\t"
2349 "jmp .Li386_less_signed_end\n\t"
2350 ".Li386_less_signed_true:\n\t"
2352 ".Li386_less_signed_end:\n\t"
2354 "lea 0x8(%esp),%esp");
2358 i386_emit_less_unsigned (void)
2360 EMIT_ASM32 (i386_less_unsigned
,
2361 "cmpl %ebx,4(%esp)\n\t"
2362 "jb .Li386_less_unsigned_true\n\t"
2363 "jne .Li386_less_unsigned_false\n\t"
2364 "cmpl %eax,(%esp)\n\t"
2365 "jb .Li386_less_unsigned_true\n\t"
2366 ".Li386_less_unsigned_false:\n\t"
2368 "jmp .Li386_less_unsigned_end\n\t"
2369 ".Li386_less_unsigned_true:\n\t"
2371 ".Li386_less_unsigned_end:\n\t"
2373 "lea 0x8(%esp),%esp");
2377 i386_emit_ref (int size
)
2382 EMIT_ASM32 (i386_ref1
,
2386 EMIT_ASM32 (i386_ref2
,
2390 EMIT_ASM32 (i386_ref4
,
2391 "movl (%eax),%eax");
2394 EMIT_ASM32 (i386_ref8
,
2395 "movl 4(%eax),%ebx\n\t"
2396 "movl (%eax),%eax");
2402 i386_emit_if_goto (int *offset_p
, int *size_p
)
2404 EMIT_ASM32 (i386_if_goto
,
2410 /* Don't trust the assembler to choose the right jump */
2411 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2414 *offset_p
= 11; /* be sure that this matches the sequence above */
2420 i386_emit_goto (int *offset_p
, int *size_p
)
2422 EMIT_ASM32 (i386_goto
,
2423 /* Don't trust the assembler to choose the right jump */
2424 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2432 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2434 int diff
= (to
- (from
+ size
));
2435 unsigned char buf
[sizeof (int)];
2437 /* We're only doing 4-byte sizes at the moment. */
2444 memcpy (buf
, &diff
, sizeof (int));
2445 write_inferior_memory (from
, buf
, sizeof (int));
2449 i386_emit_const (LONGEST num
)
2451 unsigned char buf
[16];
2453 CORE_ADDR buildaddr
= current_insn_ptr
;
2456 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2457 lo
= num
& 0xffffffff;
2458 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2460 hi
= ((num
>> 32) & 0xffffffff);
2463 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2464 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2469 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2471 append_insns (&buildaddr
, i
, buf
);
2472 current_insn_ptr
= buildaddr
;
2476 i386_emit_call (CORE_ADDR fn
)
2478 unsigned char buf
[16];
2480 CORE_ADDR buildaddr
;
2482 buildaddr
= current_insn_ptr
;
2484 buf
[i
++] = 0xe8; /* call <reladdr> */
2485 offset
= ((int) fn
) - (buildaddr
+ 5);
2486 memcpy (buf
+ 1, &offset
, 4);
2487 append_insns (&buildaddr
, 5, buf
);
2488 current_insn_ptr
= buildaddr
;
2492 i386_emit_reg (int reg
)
2494 unsigned char buf
[16];
2496 CORE_ADDR buildaddr
;
2498 EMIT_ASM32 (i386_reg_a
,
2500 buildaddr
= current_insn_ptr
;
2502 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2503 memcpy (&buf
[i
], ®
, sizeof (reg
));
2505 append_insns (&buildaddr
, i
, buf
);
2506 current_insn_ptr
= buildaddr
;
2507 EMIT_ASM32 (i386_reg_b
,
2508 "mov %eax,4(%esp)\n\t"
2509 "mov 8(%ebp),%eax\n\t"
2511 i386_emit_call (get_raw_reg_func_addr ());
2512 EMIT_ASM32 (i386_reg_c
,
2514 "lea 0x8(%esp),%esp");
2518 i386_emit_pop (void)
2520 EMIT_ASM32 (i386_pop
,
2526 i386_emit_stack_flush (void)
2528 EMIT_ASM32 (i386_stack_flush
,
2534 i386_emit_zero_ext (int arg
)
2539 EMIT_ASM32 (i386_zero_ext_8
,
2540 "and $0xff,%eax\n\t"
2544 EMIT_ASM32 (i386_zero_ext_16
,
2545 "and $0xffff,%eax\n\t"
2549 EMIT_ASM32 (i386_zero_ext_32
,
2558 i386_emit_swap (void)
2560 EMIT_ASM32 (i386_swap
,
2570 i386_emit_stack_adjust (int n
)
2572 unsigned char buf
[16];
2574 CORE_ADDR buildaddr
= current_insn_ptr
;
2577 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2581 append_insns (&buildaddr
, i
, buf
);
2582 current_insn_ptr
= buildaddr
;
2585 /* FN's prototype is `LONGEST(*fn)(int)'. */
2588 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2590 unsigned char buf
[16];
2592 CORE_ADDR buildaddr
;
2594 EMIT_ASM32 (i386_int_call_1_a
,
2595 /* Reserve a bit of stack space. */
2597 /* Put the one argument on the stack. */
2598 buildaddr
= current_insn_ptr
;
2600 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2603 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2605 append_insns (&buildaddr
, i
, buf
);
2606 current_insn_ptr
= buildaddr
;
2607 i386_emit_call (fn
);
2608 EMIT_ASM32 (i386_int_call_1_c
,
2610 "lea 0x8(%esp),%esp");
2613 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2616 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2618 unsigned char buf
[16];
2620 CORE_ADDR buildaddr
;
2622 EMIT_ASM32 (i386_void_call_2_a
,
2623 /* Preserve %eax only; we don't have to worry about %ebx. */
2625 /* Reserve a bit of stack space for arguments. */
2626 "sub $0x10,%esp\n\t"
2627 /* Copy "top" to the second argument position. (Note that
2628 we can't assume function won't scribble on its
2629 arguments, so don't try to restore from this.) */
2630 "mov %eax,4(%esp)\n\t"
2631 "mov %ebx,8(%esp)");
2632 /* Put the first argument on the stack. */
2633 buildaddr
= current_insn_ptr
;
2635 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2638 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2640 append_insns (&buildaddr
, i
, buf
);
2641 current_insn_ptr
= buildaddr
;
2642 i386_emit_call (fn
);
2643 EMIT_ASM32 (i386_void_call_2_b
,
2644 "lea 0x10(%esp),%esp\n\t"
2645 /* Restore original stack top. */
2651 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2654 /* Check low half first, more likely to be decider */
2655 "cmpl %eax,(%esp)\n\t"
2656 "jne .Leq_fallthru\n\t"
2657 "cmpl %ebx,4(%esp)\n\t"
2658 "jne .Leq_fallthru\n\t"
2659 "lea 0x8(%esp),%esp\n\t"
2662 /* jmp, but don't trust the assembler to choose the right jump */
2663 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2664 ".Leq_fallthru:\n\t"
2665 "lea 0x8(%esp),%esp\n\t"
2676 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2679 /* Check low half first, more likely to be decider */
2680 "cmpl %eax,(%esp)\n\t"
2682 "cmpl %ebx,4(%esp)\n\t"
2683 "je .Lne_fallthru\n\t"
2685 "lea 0x8(%esp),%esp\n\t"
2688 /* jmp, but don't trust the assembler to choose the right jump */
2689 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2690 ".Lne_fallthru:\n\t"
2691 "lea 0x8(%esp),%esp\n\t"
2702 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2705 "cmpl %ebx,4(%esp)\n\t"
2707 "jne .Llt_fallthru\n\t"
2708 "cmpl %eax,(%esp)\n\t"
2709 "jnl .Llt_fallthru\n\t"
2711 "lea 0x8(%esp),%esp\n\t"
2714 /* jmp, but don't trust the assembler to choose the right jump */
2715 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2716 ".Llt_fallthru:\n\t"
2717 "lea 0x8(%esp),%esp\n\t"
2728 i386_emit_le_goto (int *offset_p
, int *size_p
)
2731 "cmpl %ebx,4(%esp)\n\t"
2733 "jne .Lle_fallthru\n\t"
2734 "cmpl %eax,(%esp)\n\t"
2735 "jnle .Lle_fallthru\n\t"
2737 "lea 0x8(%esp),%esp\n\t"
2740 /* jmp, but don't trust the assembler to choose the right jump */
2741 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2742 ".Lle_fallthru:\n\t"
2743 "lea 0x8(%esp),%esp\n\t"
2754 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2757 "cmpl %ebx,4(%esp)\n\t"
2759 "jne .Lgt_fallthru\n\t"
2760 "cmpl %eax,(%esp)\n\t"
2761 "jng .Lgt_fallthru\n\t"
2763 "lea 0x8(%esp),%esp\n\t"
2766 /* jmp, but don't trust the assembler to choose the right jump */
2767 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2768 ".Lgt_fallthru:\n\t"
2769 "lea 0x8(%esp),%esp\n\t"
2780 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2783 "cmpl %ebx,4(%esp)\n\t"
2785 "jne .Lge_fallthru\n\t"
2786 "cmpl %eax,(%esp)\n\t"
2787 "jnge .Lge_fallthru\n\t"
2789 "lea 0x8(%esp),%esp\n\t"
2792 /* jmp, but don't trust the assembler to choose the right jump */
2793 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2794 ".Lge_fallthru:\n\t"
2795 "lea 0x8(%esp),%esp\n\t"
2805 struct emit_ops i386_emit_ops
=
2813 i386_emit_rsh_signed
,
2814 i386_emit_rsh_unsigned
,
2822 i386_emit_less_signed
,
2823 i386_emit_less_unsigned
,
2827 i386_write_goto_address
,
2832 i386_emit_stack_flush
,
2835 i386_emit_stack_adjust
,
2836 i386_emit_int_call_1
,
2837 i386_emit_void_call_2
,
2847 static struct emit_ops
*
2851 if (is_64bit_tdesc ())
2852 return &amd64_emit_ops
;
2855 return &i386_emit_ops
;
2858 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2860 static const gdb_byte
*
2861 x86_sw_breakpoint_from_kind (int kind
, int *size
)
2863 *size
= x86_breakpoint_len
;
2864 return x86_breakpoint
;
2868 x86_supports_range_stepping (void)
2873 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2877 x86_supports_hardware_single_step (void)
2883 x86_get_ipa_tdesc_idx (void)
2885 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2886 const struct target_desc
*tdesc
= regcache
->tdesc
;
2889 if (tdesc
== tdesc_amd64_linux
|| tdesc
== tdesc_amd64_linux_no_xml
2890 || tdesc
== tdesc_x32_linux
)
2891 return X86_TDESC_SSE
;
2892 if (tdesc
== tdesc_amd64_avx_linux
|| tdesc
== tdesc_x32_avx_linux
)
2893 return X86_TDESC_AVX
;
2894 if (tdesc
== tdesc_amd64_mpx_linux
)
2895 return X86_TDESC_MPX
;
2896 if (tdesc
== tdesc_amd64_avx_mpx_linux
)
2897 return X86_TDESC_AVX_MPX
;
2898 if (tdesc
== tdesc_amd64_avx512_linux
|| tdesc
== tdesc_x32_avx512_linux
)
2899 return X86_TDESC_AVX512
;
2902 if (tdesc
== tdesc_i386_mmx_linux
)
2903 return X86_TDESC_MMX
;
2904 if (tdesc
== tdesc_i386_linux
|| tdesc
== tdesc_i386_linux_no_xml
)
2905 return X86_TDESC_SSE
;
2906 if (tdesc
== tdesc_i386_avx_linux
)
2907 return X86_TDESC_AVX
;
2908 if (tdesc
== tdesc_i386_mpx_linux
)
2909 return X86_TDESC_MPX
;
2910 if (tdesc
== tdesc_i386_avx_mpx_linux
)
2911 return X86_TDESC_AVX_MPX
;
2912 if (tdesc
== tdesc_i386_avx512_linux
)
2913 return X86_TDESC_AVX512
;
2918 /* This is initialized assuming an amd64 target.
2919 x86_arch_setup will correct it for i386 or amd64 targets. */
2921 struct linux_target_ops the_low_target
=
2924 x86_linux_regs_info
,
2925 x86_cannot_fetch_register
,
2926 x86_cannot_store_register
,
2927 NULL
, /* fetch_register */
2930 NULL
, /* breakpoint_kind_from_pc */
2931 x86_sw_breakpoint_from_kind
,
2935 x86_supports_z_point_type
,
2938 x86_stopped_by_watchpoint
,
2939 x86_stopped_data_address
,
2940 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2941 native i386 case (no registers smaller than an xfer unit), and are not
2942 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2945 /* need to fix up i386 siginfo if host is amd64 */
2947 x86_linux_new_process
,
2948 x86_linux_new_thread
,
2950 x86_linux_prepare_to_resume
,
2951 x86_linux_process_qsupported
,
2952 x86_supports_tracepoints
,
2953 x86_get_thread_area
,
2954 x86_install_fast_tracepoint_jump_pad
,
2956 x86_get_min_fast_tracepoint_insn_len
,
2957 x86_supports_range_stepping
,
2958 NULL
, /* breakpoint_kind_from_current_state */
2959 x86_supports_hardware_single_step
,
2960 x86_get_syscall_trapinfo
,
2961 x86_get_ipa_tdesc_idx
,
2965 initialize_low_arch (void)
2967 /* Initialize the Linux target descriptions. */
2969 init_registers_amd64_linux ();
2970 init_registers_amd64_avx_linux ();
2971 init_registers_amd64_avx512_linux ();
2972 init_registers_amd64_mpx_linux ();
2973 init_registers_amd64_avx_mpx_linux ();
2975 init_registers_x32_linux ();
2976 init_registers_x32_avx_linux ();
2977 init_registers_x32_avx512_linux ();
2979 tdesc_amd64_linux_no_xml
= XNEW (struct target_desc
);
2980 copy_target_description (tdesc_amd64_linux_no_xml
, tdesc_amd64_linux
);
2981 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2983 init_registers_i386_linux ();
2984 init_registers_i386_mmx_linux ();
2985 init_registers_i386_avx_linux ();
2986 init_registers_i386_avx512_linux ();
2987 init_registers_i386_mpx_linux ();
2988 init_registers_i386_avx_mpx_linux ();
2990 tdesc_i386_linux_no_xml
= XNEW (struct target_desc
);
2991 copy_target_description (tdesc_i386_linux_no_xml
, tdesc_i386_linux
);
2992 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2994 initialize_regsets_info (&x86_regsets_info
);