1 /* Native-dependent code for the i386.
3 Copyright (C) 2001-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "breakpoint.h"
26 #include "gdb_assert.h"
29 /* Support for hardware watchpoints and breakpoints using the i386
32 This provides several functions for inserting and removing
33 hardware-assisted breakpoints and watchpoints, testing if one or
34 more of the watchpoints triggered and at what address, checking
35 whether a given region can be watched, etc.
37 The functions below implement debug registers sharing by reference
38 counts, and allow to watch regions up to 16 bytes long. */
40 /* Whether or not to print the mirrored debug registers. */
41 static int debug_hw_points
;
43 /* Function used for printing mirrored debug registers. */
44 #define debug_printf(fmt, args...) \
45 fprintf_unfiltered (gdb_stdlog, fmt, ##args);
47 /* Low-level function vector. */
48 struct i386_dr_low_type i386_dr_low
;
50 #define i386_dr_low_can_set_addr() (i386_dr_low.set_addr != NULL)
51 #define i386_dr_low_can_set_control() (i386_dr_low.set_control != NULL)
53 #define i386_dr_low_set_addr(new_state, i) \
54 (i386_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)]))
56 #define i386_dr_low_set_control(new_state) \
57 (i386_dr_low.set_control ((new_state)->dr_control_mirror))
59 #define i386_dr_low_get_addr(i) (i386_dr_low.get_addr ((i)))
60 #define i386_dr_low_get_status() (i386_dr_low.get_status ())
61 #define i386_dr_low_get_control() (i386_dr_low.get_control ())
63 /* Debug register size, in bytes. */
64 #define i386_get_debug_register_length() \
65 (i386_dr_low.debug_register_length)
67 /* Support for 8-byte wide hw watchpoints. */
68 #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8)
70 /* DR7 Debug Control register fields. */
72 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
73 #define DR_CONTROL_SHIFT 16
74 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
75 #define DR_CONTROL_SIZE 4
77 /* Watchpoint/breakpoint read/write fields in DR7. */
78 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
79 #define DR_RW_WRITE (0x1) /* Break on data writes. */
80 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
82 /* This is here for completeness. No platform supports this
83 functionality yet (as of March 2001). Note that the DE flag in the
84 CR4 register needs to be set to support this. */
86 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
89 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
90 is so we could OR this with the read/write field defined above. */
91 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
92 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
93 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
94 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
96 /* Local and Global Enable flags in DR7.
98 When the Local Enable flag is set, the breakpoint/watchpoint is
99 enabled only for the current task; the processor automatically
100 clears this flag on every task switch. When the Global Enable flag
101 is set, the breakpoint/watchpoint is enabled for all tasks; the
102 processor never clears this flag.
104 Currently, all watchpoint are locally enabled. If you need to
105 enable them globally, read the comment which pertains to this in
106 i386_insert_aligned_watchpoint below. */
107 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
108 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
109 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
111 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
112 flags). These are only required on i386, to allow detection of the
113 exact instruction which caused a watchpoint to break; i486 and
114 later processors do that automatically. We set these flags for
115 backwards compatibility. */
116 #define DR_LOCAL_SLOWDOWN (0x100)
117 #define DR_GLOBAL_SLOWDOWN (0x200)
119 /* Fields reserved by Intel. This includes the GD (General Detect
120 Enable) flag, which causes a debug exception to be generated when a
121 MOV instruction accesses one of the debug registers.
123 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
124 #define DR_CONTROL_RESERVED (0xFC00)
126 /* Auxiliary helper macros. */
128 /* A value that masks all fields in DR7 that are reserved by Intel. */
129 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
131 /* The I'th debug register is vacant if its Local and Global Enable
132 bits are reset in the Debug Control register. */
133 #define I386_DR_VACANT(state, i) \
134 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
136 /* Locally enable the break/watchpoint in the I'th debug register. */
137 #define I386_DR_LOCAL_ENABLE(state, i) \
139 (state)->dr_control_mirror |= \
140 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
143 /* Globally enable the break/watchpoint in the I'th debug register. */
144 #define I386_DR_GLOBAL_ENABLE(state, i) \
146 (state)->dr_control_mirror |= \
147 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
150 /* Disable the break/watchpoint in the I'th debug register. */
151 #define I386_DR_DISABLE(state, i) \
153 (state)->dr_control_mirror &= \
154 ~(3 << (DR_ENABLE_SIZE * (i))); \
157 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
158 #define I386_DR_SET_RW_LEN(state, i, rwlen) \
160 (state)->dr_control_mirror &= \
161 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
162 (state)->dr_control_mirror |= \
163 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
166 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
167 #define I386_DR_GET_RW_LEN(dr7, i) \
169 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
171 /* Did the watchpoint whose address is in the I'th register break? */
172 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
174 /* A macro to loop over all debug registers. */
175 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
177 /* Per-process data. We don't bind this to a per-inferior registry
178 because of targets like x86 GNU/Linux that need to keep track of
179 processes that aren't bound to any inferior (e.g., fork children,
182 struct i386_process_info
185 struct i386_process_info
*next
;
187 /* The process identifier. */
190 /* Copy of i386 hardware debug registers. */
191 struct i386_debug_reg_state state
;
194 static struct i386_process_info
*i386_process_list
= NULL
;
196 /* Find process data for process PID. */
198 static struct i386_process_info
*
199 i386_find_process_pid (pid_t pid
)
201 struct i386_process_info
*proc
;
203 for (proc
= i386_process_list
; proc
; proc
= proc
->next
)
204 if (proc
->pid
== pid
)
210 /* Add process data for process PID. Returns newly allocated info
213 static struct i386_process_info
*
214 i386_add_process (pid_t pid
)
216 struct i386_process_info
*proc
;
218 proc
= xcalloc (1, sizeof (*proc
));
221 proc
->next
= i386_process_list
;
222 i386_process_list
= proc
;
227 /* Get data specific info for process PID, creating it if necessary.
228 Never returns NULL. */
230 static struct i386_process_info
*
231 i386_process_info_get (pid_t pid
)
233 struct i386_process_info
*proc
;
235 proc
= i386_find_process_pid (pid
);
237 proc
= i386_add_process (pid
);
242 /* Get debug registers state for process PID. */
244 struct i386_debug_reg_state
*
245 i386_debug_reg_state (pid_t pid
)
247 return &i386_process_info_get (pid
)->state
;
250 /* See declaration in i386-nat.h. */
253 i386_forget_process (pid_t pid
)
255 struct i386_process_info
*proc
, **proc_link
;
257 proc
= i386_process_list
;
258 proc_link
= &i386_process_list
;
262 if (proc
->pid
== pid
)
264 *proc_link
= proc
->next
;
270 proc_link
= &proc
->next
;
275 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
276 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
278 /* Implementation. */
280 /* Clear the reference counts and forget everything we knew about the
284 i386_cleanup_dregs (void)
286 /* Starting from scratch has the same effect. */
287 i386_forget_process (ptid_get_pid (inferior_ptid
));
290 /* Print the values of the mirrored debug registers. */
293 i386_show_dr (struct i386_debug_reg_state
*state
,
294 const char *func
, CORE_ADDR addr
,
295 int len
, enum target_hw_bp_type type
)
299 debug_printf ("%s", func
);
301 debug_printf (" (addr=%s, len=%d, type=%s)",
303 type
== hw_write
? "data-write"
304 : (type
== hw_read
? "data-read"
305 : (type
== hw_access
? "data-read/write"
306 : (type
== hw_execute
? "instruction-execute"
307 /* FIXME: if/when I/O read/write
308 watchpoints are supported, add them
311 debug_printf (":\n");
312 debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
313 phex (state
->dr_control_mirror
, 8),
314 phex (state
->dr_status_mirror
, 8));
315 ALL_DEBUG_REGISTERS (i
)
318 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
319 i
, phex (state
->dr_mirror
[i
],
320 i386_get_debug_register_length ()),
321 state
->dr_ref_count
[i
],
322 i
+ 1, phex (state
->dr_mirror
[i
+ 1],
323 i386_get_debug_register_length ()),
324 state
->dr_ref_count
[i
+ 1]);
329 /* Return the value of a 4-bit field for DR7 suitable for watching a
330 region of LEN bytes for accesses of type TYPE. LEN is assumed to
331 have the value of 1, 2, or 4. */
334 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
347 internal_error (__FILE__
, __LINE__
,
348 _("The i386 doesn't support "
349 "data-read watchpoints.\n"));
354 /* Not yet supported. */
360 internal_error (__FILE__
, __LINE__
, _("\
361 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
368 return (DR_LEN_1
| rw
);
370 return (DR_LEN_2
| rw
);
372 return (DR_LEN_4
| rw
);
374 if (TARGET_HAS_DR_LEN_8
)
375 return (DR_LEN_8
| rw
);
376 /* ELSE FALL THROUGH */
378 internal_error (__FILE__
, __LINE__
, _("\
379 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len
);
383 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
384 according to the length of the region to watch. LEN_RW_BITS is the
385 value of the bits from DR7 which describes the length and access
386 type of the region to be watched by this watchpoint. Return 0 on
387 success, -1 on failure. */
390 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
391 CORE_ADDR addr
, unsigned len_rw_bits
)
395 if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ())
398 /* First, look for an occupied debug register with the same address
399 and the same RW and LEN definitions. If we find one, we can
400 reuse it for this watchpoint as well (and save a register). */
401 ALL_DEBUG_REGISTERS (i
)
403 if (!I386_DR_VACANT (state
, i
)
404 && state
->dr_mirror
[i
] == addr
405 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
407 state
->dr_ref_count
[i
]++;
412 /* Next, look for a vacant debug register. */
413 ALL_DEBUG_REGISTERS (i
)
415 if (I386_DR_VACANT (state
, i
))
419 /* No more debug registers! */
423 /* Now set up the register I to watch our region. */
425 /* Record the info in our local mirrored array. */
426 state
->dr_mirror
[i
] = addr
;
427 state
->dr_ref_count
[i
] = 1;
428 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
429 /* Note: we only enable the watchpoint locally, i.e. in the current
430 task. Currently, no i386 target allows or supports global
431 watchpoints; however, if any target would want that in the
432 future, GDB should probably provide a command to control whether
433 to enable watchpoints globally or locally, and the code below
434 should use global or local enable and slow-down flags as
436 I386_DR_LOCAL_ENABLE (state
, i
);
437 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
438 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
443 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
444 according to the length of the region to watch. LEN_RW_BITS is the
445 value of the bits from DR7 which describes the length and access
446 type of the region watched by this watchpoint. Return 0 on
447 success, -1 on failure. */
450 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
451 CORE_ADDR addr
, unsigned len_rw_bits
)
455 ALL_DEBUG_REGISTERS (i
)
457 if (!I386_DR_VACANT (state
, i
)
458 && state
->dr_mirror
[i
] == addr
459 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
461 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
463 /* Reset our mirror. */
464 state
->dr_mirror
[i
] = 0;
465 I386_DR_DISABLE (state
, i
);
474 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
475 number of debug registers required to watch a region at address
476 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
477 successful insertion or removal, a positive number when queried
478 about the number of registers, or -1 on failure. If WHAT is not a
479 valid value, bombs through internal_error. */
482 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
483 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
484 enum target_hw_bp_type type
)
487 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
489 static const int size_try_array
[8][8] =
491 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
492 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
493 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
494 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
495 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
496 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
497 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
498 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
503 int align
= addr
% max_wp_len
;
504 /* Four (eight on AMD64) is the maximum length a debug register
506 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
507 int size
= size_try_array
[try][align
];
509 if (what
== WP_COUNT
)
511 /* size_try_array[] is defined such that each iteration
512 through the loop is guaranteed to produce an address and a
513 size that can be watched with a single debug register.
514 Thus, for counting the registers required to watch a
515 region, we simply need to increment the count on each
521 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
523 if (what
== WP_INSERT
)
524 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
525 else if (what
== WP_REMOVE
)
526 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
528 internal_error (__FILE__
, __LINE__
, _("\
529 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
542 /* Update the inferior debug registers state, in STATE, with the
543 new debug registers state, in NEW_STATE. */
546 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*state
,
547 struct i386_debug_reg_state
*new_state
)
551 ALL_DEBUG_REGISTERS (i
)
553 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (state
, i
))
554 i386_dr_low_set_addr (new_state
, i
);
556 gdb_assert (new_state
->dr_mirror
[i
] == state
->dr_mirror
[i
]);
559 if (new_state
->dr_control_mirror
!= state
->dr_control_mirror
)
560 i386_dr_low_set_control (new_state
);
565 /* Insert a watchpoint to watch a memory region which starts at
566 address ADDR and whose length is LEN bytes. Watch memory accesses
567 of the type TYPE. Return 0 on success, -1 on failure. */
570 i386_insert_watchpoint (struct target_ops
*self
,
571 CORE_ADDR addr
, int len
, int type
,
572 struct expression
*cond
)
574 struct i386_debug_reg_state
*state
575 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
577 /* Work on a local copy of the debug registers, and on success,
578 commit the change back to the inferior. */
579 struct i386_debug_reg_state local_state
= *state
;
582 return 1; /* unsupported */
584 if (((len
!= 1 && len
!= 2 && len
!= 4)
585 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
588 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
594 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
596 retval
= i386_insert_aligned_watchpoint (&local_state
,
601 i386_update_inferior_debug_regs (state
, &local_state
);
604 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
609 /* Remove a watchpoint that watched the memory region which starts at
610 address ADDR, whose length is LEN bytes, and for accesses of the
611 type TYPE. Return 0 on success, -1 on failure. */
613 i386_remove_watchpoint (struct target_ops
*self
,
614 CORE_ADDR addr
, int len
, int type
,
615 struct expression
*cond
)
617 struct i386_debug_reg_state
*state
618 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
620 /* Work on a local copy of the debug registers, and on success,
621 commit the change back to the inferior. */
622 struct i386_debug_reg_state local_state
= *state
;
624 if (((len
!= 1 && len
!= 2 && len
!= 4)
625 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
628 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
634 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
636 retval
= i386_remove_aligned_watchpoint (&local_state
,
641 i386_update_inferior_debug_regs (state
, &local_state
);
644 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
649 /* Return non-zero if we can watch a memory region that starts at
650 address ADDR and whose length is LEN bytes. */
653 i386_region_ok_for_watchpoint (struct target_ops
*self
,
654 CORE_ADDR addr
, int len
)
656 struct i386_debug_reg_state
*state
657 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
660 /* Compute how many aligned watchpoints we would need to cover this
662 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
663 addr
, len
, hw_write
);
664 return nregs
<= DR_NADDR
? 1 : 0;
667 /* If the inferior has some break/watchpoint that triggered, set the
668 address associated with that break/watchpoint and return non-zero.
669 Otherwise, return zero. */
672 i386_stopped_data_address (struct target_ops
*ops
, CORE_ADDR
*addr_p
)
674 struct i386_debug_reg_state
*state
675 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
679 /* The current thread's DR_STATUS. We always need to read this to
680 check whether some watchpoint caused the trap. */
682 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
683 data breakpoint trap. Only fetch it when necessary, to avoid an
684 unnecessary extra syscall when no watchpoint triggered. */
686 unsigned control
= 0;
688 /* In non-stop/async, threads can be running while we change the
689 global dr_mirror (and friends). Say, we set a watchpoint, and
690 let threads resume. Now, say you delete the watchpoint, or
691 add/remove watchpoints such that dr_mirror changes while threads
692 are running. On targets that support non-stop,
693 inserting/deleting watchpoints updates the global dr_mirror only.
694 It does not update the real thread's debug registers; that's only
695 done prior to resume. Instead, if threads are running when the
696 mirror changes, a temporary and transparent stop on all threads
697 is forced so they can get their copy of the debug registers
698 updated on re-resume. Now, say, a thread hit a watchpoint before
699 having been updated with the new dr_mirror contents, and we
700 haven't yet handled the corresponding SIGTRAP. If we trusted
701 dr_mirror below, we'd mistake the real trapped address (from the
702 last time we had updated debug registers in the thread) with
703 whatever was currently in dr_mirror. So to fix this, dr_mirror
704 always represents intention, what we _want_ threads to have in
705 debug registers. To get at the address and cause of the trap, we
706 need to read the state the thread still has in its debug
709 In sum, always get the current debug register values the current
710 thread has, instead of trusting the global mirror. If the thread
711 was running when we last changed watchpoints, the mirror no
712 longer represents what was set in this thread's debug
714 status
= i386_dr_low_get_status ();
716 ALL_DEBUG_REGISTERS (i
)
718 if (!I386_DR_WATCH_HIT (status
, i
))
723 control
= i386_dr_low_get_control ();
727 /* This second condition makes sure DRi is set up for a data
728 watchpoint, not a hardware breakpoint. The reason is that
729 GDB doesn't call the target_stopped_data_address method
730 except for data watchpoints. In other words, I'm being
732 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
734 addr
= i386_dr_low_get_addr (i
);
737 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
741 if (debug_hw_points
&& addr
== 0)
742 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
749 /* Return non-zero if the inferior has some watchpoint that triggered.
750 Otherwise return zero. */
753 i386_stopped_by_watchpoint (struct target_ops
*ops
)
756 return i386_stopped_data_address (ops
, &addr
);
759 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
760 Return 0 on success, EBUSY on failure. */
762 i386_insert_hw_breakpoint (struct target_ops
*self
, struct gdbarch
*gdbarch
,
763 struct bp_target_info
*bp_tgt
)
765 struct i386_debug_reg_state
*state
766 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
767 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
768 CORE_ADDR addr
= bp_tgt
->placed_address
;
769 /* Work on a local copy of the debug registers, and on success,
770 commit the change back to the inferior. */
771 struct i386_debug_reg_state local_state
= *state
;
772 int retval
= i386_insert_aligned_watchpoint (&local_state
,
773 addr
, len_rw
) ? EBUSY
: 0;
776 i386_update_inferior_debug_regs (state
, &local_state
);
779 i386_show_dr (state
, "insert_hwbp", addr
, 1, hw_execute
);
784 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
785 Return 0 on success, -1 on failure. */
788 i386_remove_hw_breakpoint (struct target_ops
*self
, struct gdbarch
*gdbarch
,
789 struct bp_target_info
*bp_tgt
)
791 struct i386_debug_reg_state
*state
792 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
793 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
794 CORE_ADDR addr
= bp_tgt
->placed_address
;
795 /* Work on a local copy of the debug registers, and on success,
796 commit the change back to the inferior. */
797 struct i386_debug_reg_state local_state
= *state
;
798 int retval
= i386_remove_aligned_watchpoint (&local_state
,
802 i386_update_inferior_debug_regs (state
, &local_state
);
805 i386_show_dr (state
, "remove_hwbp", addr
, 1, hw_execute
);
810 /* Returns the number of hardware watchpoints of type TYPE that we can
811 set. Value is positive if we can set CNT watchpoints, zero if
812 setting watchpoints of type TYPE is not supported, and negative if
813 CNT is more than the maximum number of watchpoints of type TYPE
814 that we can support. TYPE is one of bp_hardware_watchpoint,
815 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
816 CNT is the number of such watchpoints used so far (including this
817 one). OTHERTYPE is non-zero if other types of watchpoints are
820 We always return 1 here because we don't have enough information
821 about possible overlap of addresses that they want to watch. As an
822 extreme example, consider the case where all the watchpoints watch
823 the same address and the same region length: then we can handle a
824 virtually unlimited number of watchpoints, due to debug register
825 sharing implemented via reference counts in i386-nat.c. */
828 i386_can_use_hw_breakpoint (struct target_ops
*self
,
829 int type
, int cnt
, int othertype
)
835 add_show_debug_regs_command (void)
837 /* A maintenance command to enable printing the internal DRi mirror
839 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
840 &debug_hw_points
, _("\
841 Set whether to show variables that mirror the x86 debug registers."), _("\
842 Show whether to show variables that mirror the x86 debug registers."), _("\
843 Use \"on\" to enable, \"off\" to disable.\n\
844 If enabled, the debug registers values are shown when GDB inserts\n\
845 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
846 triggers a breakpoint or watchpoint."),
849 &maintenance_set_cmdlist
,
850 &maintenance_show_cmdlist
);
853 /* There are only two global functions left. */
856 i386_use_watchpoints (struct target_ops
*t
)
858 /* After a watchpoint trap, the PC points to the instruction after the
859 one that caused the trap. Therefore we don't need to step over it.
860 But we do need to reset the status register to avoid another trap. */
861 t
->to_have_continuable_watchpoint
= 1;
863 t
->to_can_use_hw_breakpoint
= i386_can_use_hw_breakpoint
;
864 t
->to_region_ok_for_hw_watchpoint
= i386_region_ok_for_watchpoint
;
865 t
->to_stopped_by_watchpoint
= i386_stopped_by_watchpoint
;
866 t
->to_stopped_data_address
= i386_stopped_data_address
;
867 t
->to_insert_watchpoint
= i386_insert_watchpoint
;
868 t
->to_remove_watchpoint
= i386_remove_watchpoint
;
869 t
->to_insert_hw_breakpoint
= i386_insert_hw_breakpoint
;
870 t
->to_remove_hw_breakpoint
= i386_remove_hw_breakpoint
;
874 i386_set_debug_register_length (int len
)
876 /* This function should be called only once for each native target. */
877 gdb_assert (i386_dr_low
.debug_register_length
== 0);
878 gdb_assert (len
== 4 || len
== 8);
879 i386_dr_low
.debug_register_length
= len
;
880 add_show_debug_regs_command ();