1 /* Native-dependent code for the i386.
3 Copyright 2001, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 #include "breakpoint.h"
27 /* Support for hardware watchpoints and breakpoints using the i386
30 This provides several functions for inserting and removing
31 hardware-assisted breakpoints and watchpoints, testing if one or
32 more of the watchpoints triggered and at what address, checking
33 whether a given region can be watched, etc.
35 A target which wants to use these functions should define several
36 macros, such as `target_insert_watchpoint' and
37 `target_stopped_data_address', listed in target.h, to call the
38 appropriate functions below. It should also define
39 I386_USE_GENERIC_WATCHPOINTS in its tm.h file.
41 In addition, each target should provide several low-level macros
42 that will be called to insert watchpoints and hardware breakpoints
43 into the inferior, remove them, and check their status. These
46 I386_DR_LOW_SET_CONTROL -- set the debug control (DR7)
47 register to a given value
49 I386_DR_LOW_SET_ADDR -- put an address into one debug
52 I386_DR_LOW_RESET_ADDR -- reset the address stored in
55 I386_DR_LOW_GET_STATUS -- return the value of the debug
56 status (DR6) register.
58 The functions below implement debug registers sharing by reference
59 counts, and allow to watch regions up to 16 bytes long. */
61 #ifdef I386_USE_GENERIC_WATCHPOINTS
63 /* Support for 8-byte wide hw watchpoints. */
64 #ifndef TARGET_HAS_DR_LEN_8
65 #define TARGET_HAS_DR_LEN_8 0
68 /* Debug registers' indices. */
69 #define DR_NADDR 4 /* The number of debug address registers. */
70 #define DR_STATUS 6 /* Index of debug status register (DR6). */
71 #define DR_CONTROL 7 /* Index of debug control register (DR7). */
73 /* DR7 Debug Control register fields. */
75 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
76 #define DR_CONTROL_SHIFT 16
77 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
78 #define DR_CONTROL_SIZE 4
80 /* Watchpoint/breakpoint read/write fields in DR7. */
81 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
82 #define DR_RW_WRITE (0x1) /* Break on data writes. */
83 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
85 /* This is here for completeness. No platform supports this
86 functionality yet (as of March 2001). Note that the DE flag in the
87 CR4 register needs to be set to support this. */
89 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
92 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
93 is so we could OR this with the read/write field defined above. */
94 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
95 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
96 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
97 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
99 /* Local and Global Enable flags in DR7.
101 When the Local Enable flag is set, the breakpoint/watchpoint is
102 enabled only for the current task; the processor automatically
103 clears this flag on every task switch. When the Global Enable flag
104 is set, the breakpoint/watchpoint is enabled for all tasks; the
105 processor never clears this flag.
107 Currently, all watchpoint are locally enabled. If you need to
108 enable them globally, read the comment which pertains to this in
109 i386_insert_aligned_watchpoint below. */
110 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
111 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
112 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
114 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
115 flags). These are only required on i386, to allow detection of the
116 exact instruction which caused a watchpoint to break; i486 and
117 later processors do that automatically. We set these flags for
118 backwards compatibility. */
119 #define DR_LOCAL_SLOWDOWN (0x100)
120 #define DR_GLOBAL_SLOWDOWN (0x200)
122 /* Fields reserved by Intel. This includes the GD (General Detect
123 Enable) flag, which causes a debug exception to be generated when a
124 MOV instruction accesses one of the debug registers.
126 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
127 #define DR_CONTROL_RESERVED (0xFC00)
129 /* Auxiliary helper macros. */
131 /* A value that masks all fields in DR7 that are reserved by Intel. */
132 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
134 /* The I'th debug register is vacant if its Local and Global Enable
135 bits are reset in the Debug Control register. */
136 #define I386_DR_VACANT(i) \
137 ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
139 /* Locally enable the break/watchpoint in the I'th debug register. */
140 #define I386_DR_LOCAL_ENABLE(i) \
141 dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
143 /* Globally enable the break/watchpoint in the I'th debug register. */
144 #define I386_DR_GLOBAL_ENABLE(i) \
145 dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
147 /* Disable the break/watchpoint in the I'th debug register. */
148 #define I386_DR_DISABLE(i) \
149 dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
151 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
152 #define I386_DR_SET_RW_LEN(i,rwlen) \
154 dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
155 dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
158 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
159 #define I386_DR_GET_RW_LEN(i) \
160 ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
162 /* Did the watchpoint whose address is in the I'th register break? */
163 #define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i)))
165 /* A macro to loop over all debug registers. */
166 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
168 /* Mirror the inferior's DRi registers. We keep the status and
169 control registers separated because they don't hold addresses. */
170 static CORE_ADDR dr_mirror
[DR_NADDR
];
171 static unsigned dr_status_mirror
, dr_control_mirror
;
173 /* Reference counts for each debug register. */
174 static int dr_ref_count
[DR_NADDR
];
176 /* Whether or not to print the mirrored debug registers. */
177 static int maint_show_dr
;
179 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
180 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
182 /* Internal functions. */
184 /* Return the value of a 4-bit field for DR7 suitable for watching a
185 region of LEN bytes for accesses of type TYPE. LEN is assumed to
186 have the value of 1, 2, or 4. */
187 static unsigned i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
);
189 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
190 according to the length of the region to watch. LEN_RW_BITS is the
191 value of the bit-field from DR7 which describes the length and
192 access type of the region to be watched by this watchpoint. Return
193 0 on success, -1 on failure. */
194 static int i386_insert_aligned_watchpoint (CORE_ADDR addr
,
195 unsigned len_rw_bits
);
197 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
198 according to the length of the region to watch. LEN_RW_BITS is the
199 value of the bits from DR7 which describes the length and access
200 type of the region watched by this watchpoint. Return 0 on
201 success, -1 on failure. */
202 static int i386_remove_aligned_watchpoint (CORE_ADDR addr
,
203 unsigned len_rw_bits
);
205 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
206 number of debug registers required to watch a region at address
207 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
208 successful insertion or removal, a positive number when queried
209 about the number of registers, or -1 on failure. If WHAT is not a
210 valid value, bombs through internal_error. */
211 static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what
,
212 CORE_ADDR addr
, int len
,
213 enum target_hw_bp_type type
);
215 /* Implementation. */
217 /* Clear the reference counts and forget everything we knew about the
221 i386_cleanup_dregs (void)
225 ALL_DEBUG_REGISTERS(i
)
230 dr_control_mirror
= 0;
231 dr_status_mirror
= 0;
234 #ifndef LINUX_CHILD_POST_STARTUP_INFERIOR
236 /* Reset all debug registers at each new startup to avoid missing
237 watchpoints after restart. */
240 child_post_startup_inferior (ptid_t ptid
)
242 i386_cleanup_dregs ();
245 #endif /* LINUX_CHILD_POST_STARTUP_INFERIOR */
247 /* Print the values of the mirrored debug registers. This is called
248 when maint_show_dr is non-zero. To set that up, type "maint
249 show-debug-regs" at GDB's prompt. */
252 i386_show_dr (const char *func
, CORE_ADDR addr
,
253 int len
, enum target_hw_bp_type type
)
257 puts_unfiltered (func
);
259 printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
260 /* This code is for ia32, so casting CORE_ADDR
261 to unsigned long should be okay. */
262 (unsigned long)addr
, len
,
263 type
== hw_write
? "data-write"
264 : (type
== hw_read
? "data-read"
265 : (type
== hw_access
? "data-read/write"
266 : (type
== hw_execute
? "instruction-execute"
267 /* FIXME: if/when I/O read/write
268 watchpoints are supported, add them
271 puts_unfiltered (":\n");
272 printf_unfiltered ("\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
273 dr_control_mirror
, dr_status_mirror
);
274 ALL_DEBUG_REGISTERS(i
)
276 printf_unfiltered ("\
277 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
278 i
, paddr(dr_mirror
[i
]), dr_ref_count
[i
],
279 i
+1, paddr(dr_mirror
[i
+1]), dr_ref_count
[i
+1]);
284 /* Return the value of a 4-bit field for DR7 suitable for watching a
285 region of LEN bytes for accesses of type TYPE. LEN is assumed to
286 have the value of 1, 2, or 4. */
289 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
302 /* The i386 doesn't support data-read watchpoints. */
307 /* Not yet supported. */
313 internal_error (__FILE__
, __LINE__
, _("\
314 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
321 return (DR_LEN_1
| rw
);
323 return (DR_LEN_2
| rw
);
325 return (DR_LEN_4
| rw
);
327 if (TARGET_HAS_DR_LEN_8
)
328 return (DR_LEN_8
| rw
);
330 internal_error (__FILE__
, __LINE__
, _("\
331 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len
);
335 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
336 according to the length of the region to watch. LEN_RW_BITS is the
337 value of the bits from DR7 which describes the length and access
338 type of the region to be watched by this watchpoint. Return 0 on
339 success, -1 on failure. */
342 i386_insert_aligned_watchpoint (CORE_ADDR addr
, unsigned len_rw_bits
)
346 /* First, look for an occupied debug register with the same address
347 and the same RW and LEN definitions. If we find one, we can
348 reuse it for this watchpoint as well (and save a register). */
349 ALL_DEBUG_REGISTERS(i
)
351 if (!I386_DR_VACANT (i
)
352 && dr_mirror
[i
] == addr
353 && I386_DR_GET_RW_LEN (i
) == len_rw_bits
)
360 /* Next, look for a vacant debug register. */
361 ALL_DEBUG_REGISTERS(i
)
363 if (I386_DR_VACANT (i
))
367 /* No more debug registers! */
371 /* Now set up the register I to watch our region. */
373 /* Record the info in our local mirrored array. */
376 I386_DR_SET_RW_LEN (i
, len_rw_bits
);
377 /* Note: we only enable the watchpoint locally, i.e. in the current
378 task. Currently, no i386 target allows or supports global
379 watchpoints; however, if any target would want that in the
380 future, GDB should probably provide a command to control whether
381 to enable watchpoints globally or locally, and the code below
382 should use global or local enable and slow-down flags as
384 I386_DR_LOCAL_ENABLE (i
);
385 dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
386 dr_control_mirror
&= I386_DR_CONTROL_MASK
;
388 /* Finally, actually pass the info to the inferior. */
389 I386_DR_LOW_SET_ADDR (i
, addr
);
390 I386_DR_LOW_SET_CONTROL (dr_control_mirror
);
395 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
396 according to the length of the region to watch. LEN_RW_BITS is the
397 value of the bits from DR7 which describes the length and access
398 type of the region watched by this watchpoint. Return 0 on
399 success, -1 on failure. */
402 i386_remove_aligned_watchpoint (CORE_ADDR addr
, unsigned len_rw_bits
)
406 ALL_DEBUG_REGISTERS(i
)
408 if (!I386_DR_VACANT (i
)
409 && dr_mirror
[i
] == addr
410 && I386_DR_GET_RW_LEN (i
) == len_rw_bits
)
412 if (--dr_ref_count
[i
] == 0) /* no longer in use? */
414 /* Reset our mirror. */
417 /* Reset it in the inferior. */
418 I386_DR_LOW_SET_CONTROL (dr_control_mirror
);
419 I386_DR_LOW_RESET_ADDR (i
);
428 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
429 number of debug registers required to watch a region at address
430 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
431 successful insertion or removal, a positive number when queried
432 about the number of registers, or -1 on failure. If WHAT is not a
433 valid value, bombs through internal_error. */
436 i386_handle_nonaligned_watchpoint (i386_wp_op_t what
, CORE_ADDR addr
, int len
,
437 enum target_hw_bp_type type
)
439 int retval
= 0, status
= 0;
440 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
442 static int size_try_array
[8][8] =
444 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
445 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
446 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
447 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
448 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
449 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
450 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
451 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
456 int align
= addr
% max_wp_len
;
457 /* Four (eight on AMD64) is the maximum length a debug register
459 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
460 int size
= size_try_array
[try][align
];
462 if (what
== WP_COUNT
)
464 /* size_try_array[] is defined such that each iteration
465 through the loop is guaranteed to produce an address and a
466 size that can be watched with a single debug register.
467 Thus, for counting the registers required to watch a
468 region, we simply need to increment the count on each
474 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
476 if (what
== WP_INSERT
)
477 status
= i386_insert_aligned_watchpoint (addr
, len_rw
);
478 else if (what
== WP_REMOVE
)
479 status
= i386_remove_aligned_watchpoint (addr
, len_rw
);
481 internal_error (__FILE__
, __LINE__
, _("\
482 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
484 /* We keep the loop going even after a failure, because some
485 of the other aligned watchpoints might still succeed
486 (e.g. if they watch addresses that are already watched,
487 in which case we just increment the reference counts of
488 occupied debug registers). If we break out of the loop
489 too early, we could cause those addresses watched by
490 other watchpoints to be disabled when breakpoint.c reacts
491 to our failure to insert this watchpoint and tries to
504 /* Insert a watchpoint to watch a memory region which starts at
505 address ADDR and whose length is LEN bytes. Watch memory accesses
506 of the type TYPE. Return 0 on success, -1 on failure. */
509 i386_insert_watchpoint (CORE_ADDR addr
, int len
, int type
)
513 if (((len
!= 1 && len
!=2 && len
!=4) && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
515 retval
= i386_handle_nonaligned_watchpoint (WP_INSERT
, addr
, len
, type
);
518 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
520 retval
= i386_insert_aligned_watchpoint (addr
, len_rw
);
524 i386_show_dr ("insert_watchpoint", addr
, len
, type
);
529 /* Remove a watchpoint that watched the memory region which starts at
530 address ADDR, whose length is LEN bytes, and for accesses of the
531 type TYPE. Return 0 on success, -1 on failure. */
533 i386_remove_watchpoint (CORE_ADDR addr
, int len
, int type
)
537 if (((len
!= 1 && len
!=2 && len
!=4) && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
539 retval
= i386_handle_nonaligned_watchpoint (WP_REMOVE
, addr
, len
, type
);
542 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
544 retval
= i386_remove_aligned_watchpoint (addr
, len_rw
);
548 i386_show_dr ("remove_watchpoint", addr
, len
, type
);
553 /* Return non-zero if we can watch a memory region that starts at
554 address ADDR and whose length is LEN bytes. */
557 i386_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
561 /* Compute how many aligned watchpoints we would need to cover this
563 nregs
= i386_handle_nonaligned_watchpoint (WP_COUNT
, addr
, len
, hw_write
);
564 return nregs
<= DR_NADDR
? 1 : 0;
567 /* If the inferior has some watchpoint that triggered, set the
568 address associated with that watchpoint and return non-zero.
569 Otherwise, return zero. */
572 i386_stopped_data_address (CORE_ADDR
*addr_p
)
578 dr_status_mirror
= I386_DR_LOW_GET_STATUS ();
580 ALL_DEBUG_REGISTERS(i
)
582 if (I386_DR_WATCH_HIT (i
)
583 /* This second condition makes sure DRi is set up for a data
584 watchpoint, not a hardware breakpoint. The reason is
585 that GDB doesn't call the target_stopped_data_address
586 method except for data watchpoints. In other words, I'm
588 && I386_DR_GET_RW_LEN (i
) != 0)
593 i386_show_dr ("watchpoint_hit", addr
, -1, hw_write
);
596 if (maint_show_dr
&& addr
== 0)
597 i386_show_dr ("stopped_data_addr", 0, 0, hw_write
);
605 i386_stopped_by_watchpoint (void)
608 return i386_stopped_data_address (&addr
);
611 /* Return non-zero if the inferior has some break/watchpoint that
615 i386_stopped_by_hwbp (void)
619 dr_status_mirror
= I386_DR_LOW_GET_STATUS ();
621 i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute
);
623 ALL_DEBUG_REGISTERS(i
)
625 if (I386_DR_WATCH_HIT (i
))
632 /* Insert a hardware-assisted breakpoint at address ADDR. SHADOW is
633 unused. Return 0 on success, EBUSY on failure. */
635 i386_insert_hw_breakpoint (CORE_ADDR addr
, void *shadow
)
637 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
638 int retval
= i386_insert_aligned_watchpoint (addr
, len_rw
) ? EBUSY
: 0;
641 i386_show_dr ("insert_hwbp", addr
, 1, hw_execute
);
646 /* Remove a hardware-assisted breakpoint at address ADDR. SHADOW is
647 unused. Return 0 on success, -1 on failure. */
650 i386_remove_hw_breakpoint (CORE_ADDR addr
, void *shadow
)
652 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
653 int retval
= i386_remove_aligned_watchpoint (addr
, len_rw
);
656 i386_show_dr ("remove_hwbp", addr
, 1, hw_execute
);
661 #endif /* I386_USE_GENERIC_WATCHPOINTS */
664 /* Provide a prototype to silence -Wmissing-prototypes. */
665 void _initialize_i386_nat (void);
668 _initialize_i386_nat (void)
670 #ifdef I386_USE_GENERIC_WATCHPOINTS
671 /* A maintenance command to enable printing the internal DRi mirror
673 deprecated_add_set_cmd ("show-debug-regs", class_maintenance
,
674 var_boolean
, (char *) &maint_show_dr
, _("\
675 Set whether to show variables that mirror the x86 debug registers.\n\
676 Use \"on\" to enable, \"off\" to disable.\n\
677 If enabled, the debug registers values are shown when GDB inserts\n\
678 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
679 triggers a breakpoint or watchpoint."),
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