1 /* Intel x86 (a.k.a. ia32) native-dependent code.
2 Copyright (C) 2001 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 #include "breakpoint.h"
26 /* Support for hardware watchpoints and breakpoints using the x86
29 This provides several functions for inserting and removing
30 hardware-assisted breakpoints and watchpoints, testing if
31 one or more of the watchpoints triggered and at what address,
32 checking whether a given region can be watched, etc.
34 A target which wants to use these functions should define
35 several macros, such as `target_insert_watchpoint' and
36 `target_stopped_data_address', listed in target.h, to call
37 the appropriate functions below. It should also define
38 I386_USE_GENERIC_WATCHPOINTS in its tm.h file.
40 In addition, each target should provide several low-level
41 macros that will be called to insert watchpoints and hardware
42 breakpoints into the inferior, remove them, and check their
43 status. These macros are:
45 I386_DR_LOW_SET_CONTROL -- set the debug control (DR7)
46 register to a given value
48 I386_DR_LOW_SET_ADDR -- put an address into one debug
51 I386_DR_LOW_RESET_ADDR -- reset the address stored in
54 I386_DR_LOW_GET_STATUS -- return the value of the debug
55 status (DR6) register.
57 The functions below implement debug registers sharing by
58 reference counts, and allow to watch regions up to 16 bytes
61 #ifdef I386_USE_GENERIC_WATCHPOINTS
63 /* Support for 8-byte wide hw watchpoints. */
64 #ifndef TARGET_HAS_DR_LEN_8
65 #define TARGET_HAS_DR_LEN_8 0
68 /* Debug registers' indices. */
69 #define DR_NADDR 4 /* the number of debug address registers */
70 #define DR_STATUS 6 /* index of debug status register (DR6) */
71 #define DR_CONTROL 7 /* index of debug control register (DR7) */
73 /* DR7 Debug Control register fields. */
75 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
76 #define DR_CONTROL_SHIFT 16
77 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
78 #define DR_CONTROL_SIZE 4
80 /* Watchpoint/breakpoint read/write fields in DR7. */
81 #define DR_RW_EXECUTE (0x0) /* break on instruction execution */
82 #define DR_RW_WRITE (0x1) /* break on data writes */
83 #define DR_RW_READ (0x3) /* break on data reads or writes */
85 /* This is here for completeness. No platform supports this
86 functionality yet (as of Mar-2001). Note that the DE flag in the
87 CR4 register needs to be set to support this. */
89 #define DR_RW_IORW (0x2) /* break on I/O reads or writes */
92 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
93 is so we could OR this with the read/write field defined above. */
94 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpt */
95 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch */
96 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch */
97 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (x86-64) */
99 /* Local and Global Enable flags in DR7.
101 When the Local Enable flag is set, the breakpoint/watchpoint is
102 enabled only for the current task; the processor automatically
103 clears this flag on every task switch. When the Global Enable
104 flag is set, the breakpoint/watchpoint is enabled for all tasks;
105 the processor never clears this flag.
107 Currently, all watchpoint are locally enabled. If you need to
108 enable them globally, read the comment which pertains to this in
109 i386_insert_aligned_watchpoint below. */
110 #define DR_LOCAL_ENABLE_SHIFT 0 /* extra shift to the local enable bit */
111 #define DR_GLOBAL_ENABLE_SHIFT 1 /* extra shift to the global enable bit */
112 #define DR_ENABLE_SIZE 2 /* 2 enable bits per debug register */
114 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
115 flags). These are only required on i386, to allow detection of the
116 exact instruction which caused a watchpoint to break; i486 and
117 later processors do that automatically. We set these flags for
118 back compatibility. */
119 #define DR_LOCAL_SLOWDOWN (0x100)
120 #define DR_GLOBAL_SLOWDOWN (0x200)
122 /* Fields reserved by Intel. This includes the GD (General Detect
123 Enable) flag, which causes a debug exception to be generated when a
124 MOV instruction accesses one of the debug registers.
126 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
127 #define DR_CONTROL_RESERVED (0xFC00)
129 /* Auxiliary helper macros. */
131 /* A value that masks all fields in DR7 that are reserved by Intel. */
132 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
134 /* The I'th debug register is vacant if its Local and Global Enable
135 bits are reset in the Debug Control register. */
136 #define I386_DR_VACANT(i) \
137 ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
139 /* Locally enable the break/watchpoint in the I'th debug register. */
140 #define I386_DR_LOCAL_ENABLE(i) \
141 dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
143 /* Globally enable the break/watchpoint in the I'th debug register. */
144 #define I386_DR_GLOBAL_ENABLE(i) \
145 dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
147 /* Disable the break/watchpoint in the I'th debug register. */
148 #define I386_DR_DISABLE(i) \
149 dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
151 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
152 #define I386_DR_SET_RW_LEN(i,rwlen) \
154 dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
155 dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
158 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
159 #define I386_DR_GET_RW_LEN(i) \
160 ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
162 /* Did the watchpoint whose address is in the I'th register break? */
163 #define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i)))
165 /* A macro to loop over all debug registers. */
166 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
168 /* Mirror the inferior's DRi registers. We keep the status and
169 control registers separated because they don't hold addresses. */
170 static CORE_ADDR dr_mirror
[DR_NADDR
];
171 static unsigned dr_status_mirror
, dr_control_mirror
;
173 /* Reference counts for each debug register. */
174 static int dr_ref_count
[DR_NADDR
];
176 /* Whether or not to print the mirrored debug registers. */
177 static int maint_show_dr
;
179 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
180 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
182 /* Internal functions. */
184 /* Return the value of a 4-bit field for DR7 suitable for watching a
185 region of LEN bytes for accesses of type TYPE. LEN is assumed
186 to have the value of 1, 2, or 4. */
187 static unsigned i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
);
189 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
190 according to the length of the region to watch. LEN_RW_BITS is the
191 value of the bit-field from DR7 which describes the length and
192 access type of the region to be watched by this watchpoint. Return
193 0 on success, -1 on failure. */
194 static int i386_insert_aligned_watchpoint (CORE_ADDR addr
,
195 unsigned len_rw_bits
);
197 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
198 according to the length of the region to watch. LEN_RW_BITS is the
199 value of the bits from DR7 which describes the length and access
200 type of the region watched by this watchpoint. Return 0 on
201 success, -1 on failure. */
202 static int i386_remove_aligned_watchpoint (CORE_ADDR addr
,
203 unsigned len_rw_bits
);
205 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
206 number of debug registers required to watch a region at address
207 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
208 successful insertion or removal, a positive number when queried
209 about the number of registers, or -1 on failure. If WHAT is not
210 a valid value, bombs through internal_error. */
211 static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what
,
212 CORE_ADDR addr
, int len
,
213 enum target_hw_bp_type type
);
215 /* Implementation. */
217 /* Clear the reference counts and forget everything we knew about
218 the debug registers. */
220 i386_cleanup_dregs (void)
224 ALL_DEBUG_REGISTERS(i
)
229 dr_control_mirror
= 0;
230 dr_status_mirror
= 0;
233 /* Print the values of the mirrored debug registers.
234 This is called when maint_show_dr is non-zero. To set that
235 up, type "maint show-debug-regs" at GDB's prompt. */
237 i386_show_dr (const char *func
, CORE_ADDR addr
,
238 int len
, enum target_hw_bp_type type
)
242 puts_unfiltered (func
);
244 printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
245 /* This code is for ia32, so casting CORE_ADDR
246 to unsigned long should be okay. */
247 (unsigned long)addr
, len
,
248 type
== hw_write
? "data-write"
249 : (type
== hw_read
? "data-read"
250 : (type
== hw_access
? "data-read/write"
251 : (type
== hw_execute
? "instruction-execute"
252 /* FIXME: if/when I/O read/write
253 watchpoints are supported, add them
256 puts_unfiltered (":\n");
257 printf_unfiltered ("\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
258 dr_control_mirror
, dr_status_mirror
);
259 ALL_DEBUG_REGISTERS(i
)
261 printf_unfiltered ("\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
262 i
, paddr(dr_mirror
[i
]), dr_ref_count
[i
],
263 i
+1, paddr(dr_mirror
[i
+1]), dr_ref_count
[i
+1]);
268 /* Return the value of a 4-bit field for DR7 suitable for watching a
269 region of LEN bytes for accesses of type TYPE. LEN is assumed
270 to have the value of 1, 2, or 4. */
272 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
284 case hw_read
: /* x86 doesn't support data-read watchpoints */
289 case hw_io_access
: /* not yet supported */
294 internal_error (__FILE__
, __LINE__
, "\
295 Invalid hw breakpoint type %d in i386_length_and_rw_bits.\n", (int)type
);
301 return (DR_LEN_1
| rw
);
303 return (DR_LEN_2
| rw
);
305 return (DR_LEN_4
| rw
);
307 if (TARGET_HAS_DR_LEN_8
)
308 return (DR_LEN_8
| rw
);
310 internal_error (__FILE__
, __LINE__
, "\
311 Invalid hw breakpoint length %d in i386_length_and_rw_bits.\n", len
);
315 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
316 according to the length of the region to watch. LEN_RW_BITS is the
317 value of the bits from DR7 which describes the length and access
318 type of the region to be watched by this watchpoint. Return 0 on
319 success, -1 on failure. */
321 i386_insert_aligned_watchpoint (CORE_ADDR addr
, unsigned len_rw_bits
)
325 /* First, look for an occupied debug register with the same address
326 and the same RW and LEN definitions. If we find one, we can
327 reuse it for this watchpoint as well (and save a register). */
328 ALL_DEBUG_REGISTERS(i
)
330 if (!I386_DR_VACANT (i
)
331 && dr_mirror
[i
] == addr
332 && I386_DR_GET_RW_LEN (i
) == len_rw_bits
)
339 /* Next, look for a vacant debug register. */
340 ALL_DEBUG_REGISTERS(i
)
342 if (I386_DR_VACANT (i
))
346 /* No more debug registers! */
350 /* Now set up the register I to watch our region. */
352 /* Record the info in our local mirrored array. */
355 I386_DR_SET_RW_LEN (i
, len_rw_bits
);
356 /* Note: we only enable the watchpoint locally, i.e. in the current
357 task. Currently, no x86 target allows or supports global
358 watchpoints; however, if any target would want that in the
359 future, GDB should probably provide a command to control whether
360 to enable watchpoints globally or locally, and the code below
361 should use global or local enable and slow-down flags as
363 I386_DR_LOCAL_ENABLE (i
);
364 dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
365 dr_control_mirror
&= I386_DR_CONTROL_MASK
;
367 /* Finally, actually pass the info to the inferior. */
368 I386_DR_LOW_SET_ADDR (i
, addr
);
369 I386_DR_LOW_SET_CONTROL (dr_control_mirror
);
374 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
375 according to the length of the region to watch. LEN_RW_BITS is the
376 value of the bits from DR7 which describes the length and access
377 type of the region watched by this watchpoint. Return 0 on
378 success, -1 on failure. */
380 i386_remove_aligned_watchpoint (CORE_ADDR addr
, unsigned len_rw_bits
)
384 ALL_DEBUG_REGISTERS(i
)
386 if (!I386_DR_VACANT (i
)
387 && dr_mirror
[i
] == addr
388 && I386_DR_GET_RW_LEN (i
) == len_rw_bits
)
390 if (--dr_ref_count
[i
] == 0) /* no longer in use? */
392 /* Reset our mirror. */
395 /* Reset it in the inferior. */
396 I386_DR_LOW_SET_CONTROL (dr_control_mirror
);
397 I386_DR_LOW_RESET_ADDR (i
);
406 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
407 number of debug registers required to watch a region at address
408 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
409 successful insertion or removal, a positive number when queried
410 about the number of registers, or -1 on failure. If WHAT is not
411 a valid value, bombs through internal_error. */
413 i386_handle_nonaligned_watchpoint (i386_wp_op_t what
, CORE_ADDR addr
, int len
,
414 enum target_hw_bp_type type
)
418 int rv
= 0, status
= 0;
419 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
421 static int size_try_array
[8][8] =
423 {1, 1, 1, 1, 1, 1, 1, 1}, /* trying size one */
424 {2, 1, 2, 1, 2, 1, 2, 1}, /* trying size two */
425 {2, 1, 2, 1, 2, 1, 2, 1}, /* trying size three */
426 {4, 1, 2, 1, 4, 1, 2, 1}, /* trying size four */
427 {4, 1, 2, 1, 4, 1, 2, 1}, /* trying size five */
428 {4, 1, 2, 1, 4, 1, 2, 1}, /* trying size six */
429 {4, 1, 2, 1, 4, 1, 2, 1}, /* trying size seven */
430 {8, 1, 2, 1, 4, 1, 2, 1}, /* trying size eight */
435 align
= addr
% max_wp_len
;
436 /* Four(eigth on x86_64) is the maximum length an x86 debug register
438 size
= size_try_array
[len
> max_wp_len
? (max_wp_len
- 1) : len
- 1][align
];
439 if (what
== WP_COUNT
)
440 /* size_try_array[] is defined so that each iteration through
441 the loop is guaranteed to produce an address and a size
442 that can be watched with a single debug register. Thus,
443 for counting the registers required to watch a region, we
444 simply need to increment the count on each iteration. */
448 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
450 if (what
== WP_INSERT
)
451 status
= i386_insert_aligned_watchpoint (addr
, len_rw
);
452 else if (what
== WP_REMOVE
)
453 status
= i386_remove_aligned_watchpoint (addr
, len_rw
);
455 internal_error (__FILE__
, __LINE__
, "\
456 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
458 /* We keep the loop going even after a failure, because some
459 of the other aligned watchpoints might still succeed
460 (e.g. if they watch addresses that are already watched,
461 in which case we just increment the reference counts of
462 occupied debug registers). If we break out of the loop
463 too early, we could cause those addresses watched by
464 other watchpoints to be disabled when breakpoint.c reacts
465 to our failure to insert this watchpoint and tries to
476 /* Insert a watchpoint to watch a memory region which starts at
477 address ADDR and whose length is LEN bytes. Watch memory accesses
478 of the type TYPE. Return 0 on success, -1 on failure. */
480 i386_insert_watchpoint (CORE_ADDR addr
, int len
, int type
)
484 if (((len
!= 1 && len
!=2 && len
!=4) && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
486 retval
= i386_handle_nonaligned_watchpoint (WP_INSERT
, addr
, len
, type
);
489 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
491 retval
= i386_insert_aligned_watchpoint (addr
, len_rw
);
495 i386_show_dr ("insert_watchpoint", addr
, len
, type
);
500 /* Remove a watchpoint that watched the memory region which starts at
501 address ADDR, whose length is LEN bytes, and for accesses of the
502 type TYPE. Return 0 on success, -1 on failure. */
504 i386_remove_watchpoint (CORE_ADDR addr
, int len
, int type
)
508 if (((len
!= 1 && len
!=2 && len
!=4) && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
510 retval
= i386_handle_nonaligned_watchpoint (WP_REMOVE
, addr
, len
, type
);
513 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
515 retval
= i386_remove_aligned_watchpoint (addr
, len_rw
);
519 i386_show_dr ("remove_watchpoint", addr
, len
, type
);
524 /* Return non-zero if we can watch a memory region that starts at
525 address ADDR and whose length is LEN bytes. */
527 i386_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
529 /* Compute how many aligned watchpoints we would need to cover this
531 int nregs
= i386_handle_nonaligned_watchpoint (WP_COUNT
, addr
, len
,
534 return nregs
<= DR_NADDR
? 1 : 0;
537 /* If the inferior has some watchpoint that triggered, return the
538 address associated with that watchpoint. Otherwise, return
541 i386_stopped_data_address (void)
546 dr_status_mirror
= I386_DR_LOW_GET_STATUS ();
548 ALL_DEBUG_REGISTERS(i
)
550 if (I386_DR_WATCH_HIT (i
)
551 /* This second condition makes sure DRi is set up for a data
552 watchpoint, not a hardware breakpoint. The reason is
553 that GDB doesn't call the target_stopped_data_address
554 method except for data watchpoints. In other words, I'm
556 && I386_DR_GET_RW_LEN (i
) != 0)
560 i386_show_dr ("watchpoint_hit", ret
, -1, hw_write
);
563 if (maint_show_dr
&& ret
== 0)
564 i386_show_dr ("stopped_data_addr", 0, 0, hw_write
);
569 /* Return non-zero if the inferior has some break/watchpoint that
572 i386_stopped_by_hwbp (void)
576 dr_status_mirror
= I386_DR_LOW_GET_STATUS ();
578 i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute
);
580 ALL_DEBUG_REGISTERS(i
)
582 if (I386_DR_WATCH_HIT (i
))
589 /* Insert a hardware-assisted breakpoint at address ADDR. SHADOW is
590 unused. Return 0 on success, EBUSY on failure. */
592 i386_insert_hw_breakpoint (CORE_ADDR addr
, void *shadow
)
594 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
595 int retval
= i386_insert_aligned_watchpoint (addr
, len_rw
) ? EBUSY
: 0;
598 i386_show_dr ("insert_hwbp", addr
, 1, hw_execute
);
603 /* Remove a hardware-assisted breakpoint at address ADDR. SHADOW is
604 unused. Return 0 on success, -1 on failure. */
606 i386_remove_hw_breakpoint (CORE_ADDR addr
, void *shadow
)
608 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
609 int retval
= i386_remove_aligned_watchpoint (addr
, len_rw
);
612 i386_show_dr ("remove_hwbp", addr
, 1, hw_execute
);
617 #endif /* I386_USE_GENERIC_WATCHPOINTS */
621 _initialize_i386_nat (void)
623 #ifdef I386_USE_GENERIC_WATCHPOINTS
624 /* A maintenance command to enable printing the internal DRi mirror
626 add_set_cmd ("show-debug-regs", class_maintenance
,
627 var_boolean
, (char *) &maint_show_dr
,
629 Set whether to show variables that mirror the x86 debug registers.\n\
630 Use \"on\" to enable, \"off\" to disable.\n\
631 If enabled, the debug registers values are shown when GDB inserts\n\
632 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
633 triggers a breakpoint or watchpoint.", &maintenancelist
);
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