1 /* Native-dependent code for the i386.
3 Copyright (C) 2001-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "breakpoint.h"
26 #include "gdb_assert.h"
29 /* Support for hardware watchpoints and breakpoints using the i386
32 This provides several functions for inserting and removing
33 hardware-assisted breakpoints and watchpoints, testing if one or
34 more of the watchpoints triggered and at what address, checking
35 whether a given region can be watched, etc.
37 The functions below implement debug registers sharing by reference
38 counts, and allow to watch regions up to 16 bytes long. */
40 /* Low-level function vector. */
41 struct i386_dr_low_type i386_dr_low
;
43 /* Support for 8-byte wide hw watchpoints. */
44 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8)
46 /* DR7 Debug Control register fields. */
48 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
49 #define DR_CONTROL_SHIFT 16
50 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
51 #define DR_CONTROL_SIZE 4
53 /* Watchpoint/breakpoint read/write fields in DR7. */
54 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
55 #define DR_RW_WRITE (0x1) /* Break on data writes. */
56 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
58 /* This is here for completeness. No platform supports this
59 functionality yet (as of March 2001). Note that the DE flag in the
60 CR4 register needs to be set to support this. */
62 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
65 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
66 is so we could OR this with the read/write field defined above. */
67 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
68 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
69 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
70 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
72 /* Local and Global Enable flags in DR7.
74 When the Local Enable flag is set, the breakpoint/watchpoint is
75 enabled only for the current task; the processor automatically
76 clears this flag on every task switch. When the Global Enable flag
77 is set, the breakpoint/watchpoint is enabled for all tasks; the
78 processor never clears this flag.
80 Currently, all watchpoint are locally enabled. If you need to
81 enable them globally, read the comment which pertains to this in
82 i386_insert_aligned_watchpoint below. */
83 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
84 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
85 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
87 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
88 flags). These are only required on i386, to allow detection of the
89 exact instruction which caused a watchpoint to break; i486 and
90 later processors do that automatically. We set these flags for
91 backwards compatibility. */
92 #define DR_LOCAL_SLOWDOWN (0x100)
93 #define DR_GLOBAL_SLOWDOWN (0x200)
95 /* Fields reserved by Intel. This includes the GD (General Detect
96 Enable) flag, which causes a debug exception to be generated when a
97 MOV instruction accesses one of the debug registers.
99 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
100 #define DR_CONTROL_RESERVED (0xFC00)
102 /* Auxiliary helper macros. */
104 /* A value that masks all fields in DR7 that are reserved by Intel. */
105 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
107 /* The I'th debug register is vacant if its Local and Global Enable
108 bits are reset in the Debug Control register. */
109 #define I386_DR_VACANT(state, i) \
110 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
112 /* Locally enable the break/watchpoint in the I'th debug register. */
113 #define I386_DR_LOCAL_ENABLE(state, i) \
115 (state)->dr_control_mirror |= \
116 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
119 /* Globally enable the break/watchpoint in the I'th debug register. */
120 #define I386_DR_GLOBAL_ENABLE(state, i) \
122 (state)->dr_control_mirror |= \
123 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
126 /* Disable the break/watchpoint in the I'th debug register. */
127 #define I386_DR_DISABLE(state, i) \
129 (state)->dr_control_mirror &= \
130 ~(3 << (DR_ENABLE_SIZE * (i))); \
133 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
134 #define I386_DR_SET_RW_LEN(state, i, rwlen) \
136 (state)->dr_control_mirror &= \
137 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
138 (state)->dr_control_mirror |= \
139 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
142 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
143 #define I386_DR_GET_RW_LEN(dr7, i) \
145 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
147 /* Did the watchpoint whose address is in the I'th register break? */
148 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
150 /* A macro to loop over all debug registers. */
151 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
153 /* Per-process data. We don't bind this to a per-inferior registry
154 because of targets like x86 GNU/Linux that need to keep track of
155 processes that aren't bound to any inferior (e.g., fork children,
158 struct i386_process_info
161 struct i386_process_info
*next
;
163 /* The process identifier. */
166 /* Copy of i386 hardware debug registers. */
167 struct i386_debug_reg_state state
;
170 static struct i386_process_info
*i386_process_list
= NULL
;
172 /* Find process data for process PID. */
174 static struct i386_process_info
*
175 i386_find_process_pid (pid_t pid
)
177 struct i386_process_info
*proc
;
179 for (proc
= i386_process_list
; proc
; proc
= proc
->next
)
180 if (proc
->pid
== pid
)
186 /* Add process data for process PID. Returns newly allocated info
189 static struct i386_process_info
*
190 i386_add_process (pid_t pid
)
192 struct i386_process_info
*proc
;
194 proc
= xcalloc (1, sizeof (*proc
));
197 proc
->next
= i386_process_list
;
198 i386_process_list
= proc
;
203 /* Get data specific info for process PID, creating it if necessary.
204 Never returns NULL. */
206 static struct i386_process_info
*
207 i386_process_info_get (pid_t pid
)
209 struct i386_process_info
*proc
;
211 proc
= i386_find_process_pid (pid
);
213 proc
= i386_add_process (pid
);
218 /* Get debug registers state for process PID. */
220 struct i386_debug_reg_state
*
221 i386_debug_reg_state (pid_t pid
)
223 return &i386_process_info_get (pid
)->state
;
226 /* See declaration in i386-nat.h. */
229 i386_forget_process (pid_t pid
)
231 struct i386_process_info
*proc
, **proc_link
;
233 proc
= i386_process_list
;
234 proc_link
= &i386_process_list
;
238 if (proc
->pid
== pid
)
240 *proc_link
= proc
->next
;
246 proc_link
= &proc
->next
;
251 /* Whether or not to print the mirrored debug registers. */
252 static int maint_show_dr
;
254 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
255 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
257 /* Implementation. */
259 /* Clear the reference counts and forget everything we knew about the
263 i386_cleanup_dregs (void)
265 /* Starting from scratch has the same effect. */
266 i386_forget_process (ptid_get_pid (inferior_ptid
));
269 /* Print the values of the mirrored debug registers. */
272 i386_show_dr (struct i386_debug_reg_state
*state
,
273 const char *func
, CORE_ADDR addr
,
274 int len
, enum target_hw_bp_type type
)
276 int addr_size
= gdbarch_addr_bit (target_gdbarch ()) / 8;
279 puts_unfiltered (func
);
281 printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
282 /* This code is for ia32, so casting CORE_ADDR
283 to unsigned long should be okay. */
284 (unsigned long) addr
, len
,
285 type
== hw_write
? "data-write"
286 : (type
== hw_read
? "data-read"
287 : (type
== hw_access
? "data-read/write"
288 : (type
== hw_execute
? "instruction-execute"
289 /* FIXME: if/when I/O read/write
290 watchpoints are supported, add them
293 puts_unfiltered (":\n");
294 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
295 phex (state
->dr_control_mirror
, 8),
296 phex (state
->dr_status_mirror
, 8));
297 ALL_DEBUG_REGISTERS (i
)
299 printf_unfiltered ("\
300 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
301 i
, phex (state
->dr_mirror
[i
], addr_size
),
302 state
->dr_ref_count
[i
],
303 i
+ 1, phex (state
->dr_mirror
[i
+ 1], addr_size
),
304 state
->dr_ref_count
[i
+ 1]);
309 /* Return the value of a 4-bit field for DR7 suitable for watching a
310 region of LEN bytes for accesses of type TYPE. LEN is assumed to
311 have the value of 1, 2, or 4. */
314 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
327 internal_error (__FILE__
, __LINE__
,
328 _("The i386 doesn't support "
329 "data-read watchpoints.\n"));
334 /* Not yet supported. */
340 internal_error (__FILE__
, __LINE__
, _("\
341 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
348 return (DR_LEN_1
| rw
);
350 return (DR_LEN_2
| rw
);
352 return (DR_LEN_4
| rw
);
354 if (TARGET_HAS_DR_LEN_8
)
355 return (DR_LEN_8
| rw
);
356 /* ELSE FALL THROUGH */
358 internal_error (__FILE__
, __LINE__
, _("\
359 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len
);
363 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
364 according to the length of the region to watch. LEN_RW_BITS is the
365 value of the bits from DR7 which describes the length and access
366 type of the region to be watched by this watchpoint. Return 0 on
367 success, -1 on failure. */
370 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
371 CORE_ADDR addr
, unsigned len_rw_bits
)
375 if (!i386_dr_low
.set_addr
|| !i386_dr_low
.set_control
)
378 /* First, look for an occupied debug register with the same address
379 and the same RW and LEN definitions. If we find one, we can
380 reuse it for this watchpoint as well (and save a register). */
381 ALL_DEBUG_REGISTERS (i
)
383 if (!I386_DR_VACANT (state
, i
)
384 && state
->dr_mirror
[i
] == addr
385 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
387 state
->dr_ref_count
[i
]++;
392 /* Next, look for a vacant debug register. */
393 ALL_DEBUG_REGISTERS (i
)
395 if (I386_DR_VACANT (state
, i
))
399 /* No more debug registers! */
403 /* Now set up the register I to watch our region. */
405 /* Record the info in our local mirrored array. */
406 state
->dr_mirror
[i
] = addr
;
407 state
->dr_ref_count
[i
] = 1;
408 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
409 /* Note: we only enable the watchpoint locally, i.e. in the current
410 task. Currently, no i386 target allows or supports global
411 watchpoints; however, if any target would want that in the
412 future, GDB should probably provide a command to control whether
413 to enable watchpoints globally or locally, and the code below
414 should use global or local enable and slow-down flags as
416 I386_DR_LOCAL_ENABLE (state
, i
);
417 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
418 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
423 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
424 according to the length of the region to watch. LEN_RW_BITS is the
425 value of the bits from DR7 which describes the length and access
426 type of the region watched by this watchpoint. Return 0 on
427 success, -1 on failure. */
430 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
431 CORE_ADDR addr
, unsigned len_rw_bits
)
435 ALL_DEBUG_REGISTERS (i
)
437 if (!I386_DR_VACANT (state
, i
)
438 && state
->dr_mirror
[i
] == addr
439 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
441 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
443 /* Reset our mirror. */
444 state
->dr_mirror
[i
] = 0;
445 I386_DR_DISABLE (state
, i
);
454 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
455 number of debug registers required to watch a region at address
456 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
457 successful insertion or removal, a positive number when queried
458 about the number of registers, or -1 on failure. If WHAT is not a
459 valid value, bombs through internal_error. */
462 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
463 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
464 enum target_hw_bp_type type
)
467 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
469 static int size_try_array
[8][8] =
471 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
472 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
473 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
474 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
475 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
476 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
477 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
478 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
483 int align
= addr
% max_wp_len
;
484 /* Four (eight on AMD64) is the maximum length a debug register
486 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
487 int size
= size_try_array
[try][align
];
489 if (what
== WP_COUNT
)
491 /* size_try_array[] is defined such that each iteration
492 through the loop is guaranteed to produce an address and a
493 size that can be watched with a single debug register.
494 Thus, for counting the registers required to watch a
495 region, we simply need to increment the count on each
501 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
503 if (what
== WP_INSERT
)
504 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
505 else if (what
== WP_REMOVE
)
506 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
508 internal_error (__FILE__
, __LINE__
, _("\
509 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
522 /* Update the inferior's debug registers with the new debug registers
523 state, in NEW_STATE, and then update our local mirror to match. */
526 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*new_state
)
528 struct i386_debug_reg_state
*state
529 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
532 ALL_DEBUG_REGISTERS (i
)
534 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (state
, i
))
535 i386_dr_low
.set_addr (i
, new_state
->dr_mirror
[i
]);
537 gdb_assert (new_state
->dr_mirror
[i
] == state
->dr_mirror
[i
]);
540 if (new_state
->dr_control_mirror
!= state
->dr_control_mirror
)
541 i386_dr_low
.set_control (new_state
->dr_control_mirror
);
546 /* Insert a watchpoint to watch a memory region which starts at
547 address ADDR and whose length is LEN bytes. Watch memory accesses
548 of the type TYPE. Return 0 on success, -1 on failure. */
551 i386_insert_watchpoint (struct target_ops
*self
,
552 CORE_ADDR addr
, int len
, int type
,
553 struct expression
*cond
)
555 struct i386_debug_reg_state
*state
556 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
558 /* Work on a local copy of the debug registers, and on success,
559 commit the change back to the inferior. */
560 struct i386_debug_reg_state local_state
= *state
;
563 return 1; /* unsupported */
565 if (((len
!= 1 && len
!= 2 && len
!= 4)
566 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
569 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
575 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
577 retval
= i386_insert_aligned_watchpoint (&local_state
,
582 i386_update_inferior_debug_regs (&local_state
);
585 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
590 /* Remove a watchpoint that watched the memory region which starts at
591 address ADDR, whose length is LEN bytes, and for accesses of the
592 type TYPE. Return 0 on success, -1 on failure. */
594 i386_remove_watchpoint (struct target_ops
*self
,
595 CORE_ADDR addr
, int len
, int type
,
596 struct expression
*cond
)
598 struct i386_debug_reg_state
*state
599 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
601 /* Work on a local copy of the debug registers, and on success,
602 commit the change back to the inferior. */
603 struct i386_debug_reg_state local_state
= *state
;
605 if (((len
!= 1 && len
!= 2 && len
!= 4)
606 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
609 retval
= i386_handle_nonaligned_watchpoint (&local_state
,
615 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
617 retval
= i386_remove_aligned_watchpoint (&local_state
,
622 i386_update_inferior_debug_regs (&local_state
);
625 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
630 /* Return non-zero if we can watch a memory region that starts at
631 address ADDR and whose length is LEN bytes. */
634 i386_region_ok_for_watchpoint (struct target_ops
*self
,
635 CORE_ADDR addr
, int len
)
637 struct i386_debug_reg_state
*state
638 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
641 /* Compute how many aligned watchpoints we would need to cover this
643 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
644 addr
, len
, hw_write
);
645 return nregs
<= DR_NADDR
? 1 : 0;
648 /* If the inferior has some break/watchpoint that triggered, set the
649 address associated with that break/watchpoint and return non-zero.
650 Otherwise, return zero. */
653 i386_stopped_data_address (struct target_ops
*ops
, CORE_ADDR
*addr_p
)
655 struct i386_debug_reg_state
*state
656 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
660 /* The current thread's DR_STATUS. We always need to read this to
661 check whether some watchpoint caused the trap. */
663 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
664 data breakpoint trap. Only fetch it when necessary, to avoid an
665 unnecessary extra syscall when no watchpoint triggered. */
667 unsigned control
= 0;
669 /* In non-stop/async, threads can be running while we change the
670 global dr_mirror (and friends). Say, we set a watchpoint, and
671 let threads resume. Now, say you delete the watchpoint, or
672 add/remove watchpoints such that dr_mirror changes while threads
673 are running. On targets that support non-stop,
674 inserting/deleting watchpoints updates the global dr_mirror only.
675 It does not update the real thread's debug registers; that's only
676 done prior to resume. Instead, if threads are running when the
677 mirror changes, a temporary and transparent stop on all threads
678 is forced so they can get their copy of the debug registers
679 updated on re-resume. Now, say, a thread hit a watchpoint before
680 having been updated with the new dr_mirror contents, and we
681 haven't yet handled the corresponding SIGTRAP. If we trusted
682 dr_mirror below, we'd mistake the real trapped address (from the
683 last time we had updated debug registers in the thread) with
684 whatever was currently in dr_mirror. So to fix this, dr_mirror
685 always represents intention, what we _want_ threads to have in
686 debug registers. To get at the address and cause of the trap, we
687 need to read the state the thread still has in its debug
690 In sum, always get the current debug register values the current
691 thread has, instead of trusting the global mirror. If the thread
692 was running when we last changed watchpoints, the mirror no
693 longer represents what was set in this thread's debug
695 status
= i386_dr_low
.get_status ();
697 ALL_DEBUG_REGISTERS (i
)
699 if (!I386_DR_WATCH_HIT (status
, i
))
704 control
= i386_dr_low
.get_control ();
708 /* This second condition makes sure DRi is set up for a data
709 watchpoint, not a hardware breakpoint. The reason is that
710 GDB doesn't call the target_stopped_data_address method
711 except for data watchpoints. In other words, I'm being
713 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
715 addr
= i386_dr_low
.get_addr (i
);
718 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
722 if (maint_show_dr
&& addr
== 0)
723 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
730 /* Return non-zero if the inferior has some watchpoint that triggered.
731 Otherwise return zero. */
734 i386_stopped_by_watchpoint (struct target_ops
*ops
)
737 return i386_stopped_data_address (ops
, &addr
);
740 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
741 Return 0 on success, EBUSY on failure. */
743 i386_insert_hw_breakpoint (struct target_ops
*self
, struct gdbarch
*gdbarch
,
744 struct bp_target_info
*bp_tgt
)
746 struct i386_debug_reg_state
*state
747 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
748 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
749 CORE_ADDR addr
= bp_tgt
->placed_address
;
750 /* Work on a local copy of the debug registers, and on success,
751 commit the change back to the inferior. */
752 struct i386_debug_reg_state local_state
= *state
;
753 int retval
= i386_insert_aligned_watchpoint (&local_state
,
754 addr
, len_rw
) ? EBUSY
: 0;
757 i386_update_inferior_debug_regs (&local_state
);
760 i386_show_dr (state
, "insert_hwbp", addr
, 1, hw_execute
);
765 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
766 Return 0 on success, -1 on failure. */
769 i386_remove_hw_breakpoint (struct target_ops
*self
, struct gdbarch
*gdbarch
,
770 struct bp_target_info
*bp_tgt
)
772 struct i386_debug_reg_state
*state
773 = i386_debug_reg_state (ptid_get_pid (inferior_ptid
));
774 unsigned len_rw
= i386_length_and_rw_bits (1, hw_execute
);
775 CORE_ADDR addr
= bp_tgt
->placed_address
;
776 /* Work on a local copy of the debug registers, and on success,
777 commit the change back to the inferior. */
778 struct i386_debug_reg_state local_state
= *state
;
779 int retval
= i386_remove_aligned_watchpoint (&local_state
,
783 i386_update_inferior_debug_regs (&local_state
);
786 i386_show_dr (state
, "remove_hwbp", addr
, 1, hw_execute
);
791 /* Returns the number of hardware watchpoints of type TYPE that we can
792 set. Value is positive if we can set CNT watchpoints, zero if
793 setting watchpoints of type TYPE is not supported, and negative if
794 CNT is more than the maximum number of watchpoints of type TYPE
795 that we can support. TYPE is one of bp_hardware_watchpoint,
796 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
797 CNT is the number of such watchpoints used so far (including this
798 one). OTHERTYPE is non-zero if other types of watchpoints are
801 We always return 1 here because we don't have enough information
802 about possible overlap of addresses that they want to watch. As an
803 extreme example, consider the case where all the watchpoints watch
804 the same address and the same region length: then we can handle a
805 virtually unlimited number of watchpoints, due to debug register
806 sharing implemented via reference counts in i386-nat.c. */
809 i386_can_use_hw_breakpoint (struct target_ops
*self
,
810 int type
, int cnt
, int othertype
)
816 add_show_debug_regs_command (void)
818 /* A maintenance command to enable printing the internal DRi mirror
820 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
822 Set whether to show variables that mirror the x86 debug registers."), _("\
823 Show whether to show variables that mirror the x86 debug registers."), _("\
824 Use \"on\" to enable, \"off\" to disable.\n\
825 If enabled, the debug registers values are shown when GDB inserts\n\
826 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
827 triggers a breakpoint or watchpoint."),
830 &maintenance_set_cmdlist
,
831 &maintenance_show_cmdlist
);
834 /* There are only two global functions left. */
837 i386_use_watchpoints (struct target_ops
*t
)
839 /* After a watchpoint trap, the PC points to the instruction after the
840 one that caused the trap. Therefore we don't need to step over it.
841 But we do need to reset the status register to avoid another trap. */
842 t
->to_have_continuable_watchpoint
= 1;
844 t
->to_can_use_hw_breakpoint
= i386_can_use_hw_breakpoint
;
845 t
->to_region_ok_for_hw_watchpoint
= i386_region_ok_for_watchpoint
;
846 t
->to_stopped_by_watchpoint
= i386_stopped_by_watchpoint
;
847 t
->to_stopped_data_address
= i386_stopped_data_address
;
848 t
->to_insert_watchpoint
= i386_insert_watchpoint
;
849 t
->to_remove_watchpoint
= i386_remove_watchpoint
;
850 t
->to_insert_hw_breakpoint
= i386_insert_hw_breakpoint
;
851 t
->to_remove_hw_breakpoint
= i386_remove_hw_breakpoint
;
855 i386_set_debug_register_length (int len
)
857 /* This function should be called only once for each native target. */
858 gdb_assert (i386_dr_low
.debug_register_length
== 0);
859 gdb_assert (len
== 4 || len
== 8);
860 i386_dr_low
.debug_register_length
= len
;
861 add_show_debug_regs_command ();